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zpekic |
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16:51:58 02/19/2017
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-- Design Name:
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-- Module Name: tinyrom - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use STD.textio.all;
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use ieee.std_logic_textio.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use work.tinycpu_common.all;
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entity rom512x56 is
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Port ( address : in STD_LOGIC_VECTOR (8 downto 0);
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data : out STD_LOGIC_VECTOR (55 downto 0));
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end rom512x56;
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architecture Behavioral of rom512x56 is
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--type t_uinstruction is array (55 downto 0) of std_logic;
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type t_word is array(15 downto 0) of std_logic;
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type t_byte is array(7 downto 0) of std_logic;
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type t_uinstruction512 is array(0 to 511) of std_logic_vector(55 downto 0);
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constant uCode_nop: std_logic_vector(55 downto 0) := "11000000001011111010100111110000001101010101010001000000";
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constant uCode_default: std_logic_vector(55 downto 0) := "11111111111111111111111111111111111111111111111111111111";
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type t_string16x4 is array(0 to 15) of string(1 to 4);
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type t_string8x3 is array(0 to 7) of string(1 to 3);
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type t_string8x5 is array(0 to 7) of string(1 to 5);
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type t_string8x6 is array(0 to 7) of string(1 to 6);
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type t_string4x4 is array(0 to 3) of string(1 to 4);
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type t_string4x2 is array(0 to 3) of string(1 to 2);
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type t_string2x2 is array(0 to 1) of string(1 to 2);
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type t_string2x1 is array(0 to 1) of string(1 to 1);
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constant cond_decode: t_string16x4 := ("Z ", "CY ", "P ", "S ", "AC ", "?(5)", "?(6)", "?(7)", "INT ", "RDY ", "HOLD", "?(B)", "F3 ", "F=0 ", "CN4 ", "TRUE");
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constant reg_decode: t_string16x4 := ("R_BC", "R_CB", "R_DE", "R_ED", "R_HL", "R_LH", "R_?A", "R_A?", "R_SP", "R_9?", "RAS1", "RBS2", "RZ38", "R38Z", "RES3", "R_PC");
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constant src_decode: t_string8x3 := ("AQ ", "AB ", "ZQ ", "ZB ", "ZA ", "DA ", "DQ ", "DZ ");
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constant fct_decode: t_string8x5 := ("ADD ", "SUBR ", "SUBS ", "OR ", "AND ", "NOTRS", "EXOR ", "EXNOR");
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constant dst_decode: t_string8x5 := ("QREG ", "NOP ", "RAMA ", "RAMF ", "RAMQD", "RAMD ", "RAMQU", "RAMU ");
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constant next_decode: t_string8x6 := ("C/R ", "D/R ", "C/SBR ", "R/RTN ", "F/SBR ", "POP/PR", "R/PUSH", "R/F ");
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constant databusenable_decode: t_string4x2 := ("--", "YL", "YH", "FL");
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constant outputsteer_decode: t_string4x4 := ("----", "DATA", "ADDR", "INTE");
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constant immediatedatabus_decode: t_string2x1 := ("m", "-");
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constant size_decode: t_string2x2 := ("8 ", "16");
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constant instregenable_decode: t_string2x1 := ("i", "-");
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constant condpolarity_decode: t_string2x1 := ("-", "!");
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alias a8: std_logic_vector(8 downto 0) is address(8 downto 0);
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impure function char2hex(char: in character) return integer is
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begin
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case char is
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when '0' to '9' =>
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return character'pos(char) - character'pos('0');
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when 'a' to 'f' =>
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return character'pos(char) - character'pos('a') + 10;
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when 'A' to 'F' =>
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return character'pos(char) - character'pos('A') + 10;
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when others =>
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assert false report "char2hex(): unexpected character '" & char & "'" severity failure;
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end case;
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return 0;
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end char2hex;
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impure function decode_buscontrol(buscontrol: in std_logic_vector(5 downto 0)) return string is
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begin
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case buscontrol is
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when "111110" => return "NOC ";
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when "111100" => return "MEMW ";
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when "111010" => return "MEMR ";
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when "110110" => return "IOW ";
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when "101110" => return "IOR ";
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when "011110" => return "INTA ";
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when "111111" => return "HLDA ";
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when others =>
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return "??????";
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end case;
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end decode_buscontrol;
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impure function decode_reg(reg: in std_logic_vector(3 downto 0)) return string is
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begin
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return reg_decode(to_integer(unsigned(reg)));
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end decode_reg;
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impure function decode_cond(cond: in std_logic_vector(3 downto 0)) return string is
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begin
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return cond_decode(to_integer(unsigned(cond)));
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end decode_cond;
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impure function decode_src(src: in std_logic_vector(2 downto 0)) return string is
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begin
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return src_decode(to_integer(unsigned(src)));
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end decode_src;
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impure function decode_fct(fct: in std_logic_vector(2 downto 0)) return string is
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begin
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return fct_decode(to_integer(unsigned(fct)));
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end decode_fct;
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impure function decode_dst(dst: in std_logic_vector(2 downto 0)) return string is
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begin
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return dst_decode(to_integer(unsigned(dst)));
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end decode_dst;
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impure function decode_next(nxt: in std_logic_vector(2 downto 0)) return string is
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begin
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return next_decode(to_integer(unsigned(nxt)));
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end decode_next;
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impure function decode_databusenable(busenable: in std_logic_vector(1 downto 0)) return string is
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begin
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return databusenable_decode(to_integer(unsigned(busenable)));
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end decode_databusenable;
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impure function decode_outputsteer(outputsteer: in std_logic_vector(1 downto 0)) return string is
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begin
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return outputsteer_decode(to_integer(unsigned(outputsteer)));
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end decode_outputsteer;
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impure function decode_immediatedatabus(immediatedatabus: in std_logic) return string is
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begin
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return immediatedatabus_decode(to_integer(unsigned'("" & immediatedatabus)));
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end decode_immediatedatabus;
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impure function decode_size(size: in std_logic) return string is
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begin
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return size_decode(to_integer(unsigned'("" & size)));
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end decode_size;
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impure function decode_instregenable(instregenable: in std_logic) return string is
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begin
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return instregenable_decode(to_integer(unsigned'("" & instregenable)));
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end decode_instregenable;
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impure function decode_condpolarity(condpolarity: in std_logic) return string is
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begin
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return condpolarity_decode(to_integer(unsigned'("" & condpolarity)));
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end decode_condpolarity;
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procedure dump_wordmemory(out_file_name: in string; depth: in integer; temp_mem: in t_uinstruction512; base: in integer) is
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file out_file : text open write_mode is out_file_name;
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variable out_line : line;
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begin
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-- dump memory content in <address> <word> format for verification
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for i in 0 to (depth - 1) loop
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if ((i mod 32 = 0) and not ((base = 8) or (base = 16))) then
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write(out_line, string'("-----------------------------------------------------------------------------------------"));writeline(out_file, out_line);
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write(out_line, string'(" I D DIRECT-VALUE NXT P COND B SYSCTL OE OS A UK S C W AADR BADR DST FCT SRC"));writeline(out_file, out_line);
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write(out_line, string'("-----------------------------------------------------------------------------------------"));writeline(out_file, out_line);
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end if;
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hwrite(out_line, std_logic_vector(to_unsigned(i, 16)));
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write(out_line, string'(" "));
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if (temp_mem(i) = ucode_default) then
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write(out_line, string'("(uninitialized)"));
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else
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case base is
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when 2 =>
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write(out_line, temp_mem(i)(55));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(54));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(53 downto 42));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(41 downto 39));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(38));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(37 downto 34));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(33));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(32 downto 27));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(26 downto 25));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(24 downto 23));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(22));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(21 downto 20));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(19));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(18));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(17));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(16 downto 13));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(12 downto 9));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(8 downto 6));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(5 downto 3));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(2 downto 0));
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when 8 =>
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owrite(out_line, temp_mem(i));
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when 16 =>
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hwrite(out_line, temp_mem(i));
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when others => -- any other value will dump microcode "mnemonics"
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write(out_line, decode_instregenable(temp_mem(i)(55)));write(out_line, string'(" "));
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write(out_line, decode_immediatedatabus(temp_mem(i)(54)));write(out_line, string'(" "));
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if (unsigned(temp_mem(i)(53 downto 42)) = i) then
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write(out_line, string'("= location = "));
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else
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write(out_line, temp_mem(i)(53 downto 42));write(out_line, string'(" "));
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end if;
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write(out_line, decode_next(temp_mem(i)(41 downto 39)));write(out_line, string'(" "));
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write(out_line, decode_condpolarity(temp_mem(i)(38)));write(out_line, string'(" "));
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write(out_line, decode_cond(temp_mem(i)(37 downto 34)));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(33));write(out_line, string'(" "));
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write(out_line, decode_buscontrol(temp_mem(i)(32 downto 27)));write(out_line, string'(" "));
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write(out_line, decode_databusenable(temp_mem(i)(26 downto 25)));write(out_line, string'(" "));
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write(out_line, decode_outputsteer(temp_mem(i)(24 downto 23)));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(22));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(21 downto 20));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(19));write(out_line, string'(" "));
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write(out_line, temp_mem(i)(18));write(out_line, string'(" "));
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write(out_line, decode_size(temp_mem(i)(17)));write(out_line, string'(" "));
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write(out_line, decode_reg(temp_mem(i)(16 downto 13)));write(out_line, string'(" "));
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write(out_line, decode_reg(temp_mem(i)(12 downto 9)));write(out_line, string'(" "));
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write(out_line, decode_dst(temp_mem(i)(8 downto 6)));write(out_line, string'(" "));
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write(out_line, decode_fct(temp_mem(i)(5 downto 3)));write(out_line, string'(" "));
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write(out_line, decode_src(temp_mem(i)(2 downto 0)));
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end case;
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end if;
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writeline(out_file, out_line);
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end loop;
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file_close(out_file);
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end dump_wordmemory;
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impure function parseHex16(hex_str: in string) return std_logic_vector is
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variable intVal: integer := 0;
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begin
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--report "parseHex16(" & hex_str & ")" severity note;
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for i in hex_str'left to hex_str'right loop
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intVal := 16 * intVal + char2hex(hex_str(i));
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end loop;
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return std_logic_vector(to_unsigned(intVal, 16));
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end parseHex16;
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impure function parseBinary8(bin_str: in string) return std_logic_vector is
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variable val: std_logic_vector(7 downto 0) := "00000000";
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begin
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--report "parseBinary8(" & bin_str & ")" severity note;
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for i in bin_str'left to bin_str'right loop
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case bin_str(i) is
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when '0' =>
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val := val(6 downto 0) & "0";
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when '1'|'X' => -- interpret X as '1' due to bus signal being low active - this way is undefined microinstruction is executed, bus won't short!
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val := val(6 downto 0) & "1";
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when others =>
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assert false report "parseBinary8(): unexpected character '" & bin_str(i) & "'" severity failure;
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end case;
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end loop;
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return val;
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end parseBinary8;
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impure function parseBinary16(bin_str: in string) return std_logic_vector is
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begin
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--report "parseBinary16(" & bin_str & ")" severity note;
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return parseBinary8(bin_str(1 to 8)) & parseBinary8(bin_str(9 to 16));
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end parseBinary16;
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impure function init_wordmemory(input_file_name : in string; dump_file_name: in string; dump_file_base: in integer; depth: in integer; default_value: std_logic_vector(55 downto 0)) return t_uinstruction512 is
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variable temp_mem : t_uinstruction512;-- := (others => (others => default_value));
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-- mif file variables
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file input_file : text open read_mode is input_file_name;
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variable input_line : line;
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variable line_current: integer := 0;
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variable line_cnt_accepted, line_cnt_ignored: integer := 0;
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variable address: std_logic_vector(15 downto 0);
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variable word: std_logic_vector(55 downto 0);
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variable addr_str: string(1 to 3);
|
287 |
|
|
variable data16_str1, data16_str2, data16_str3: string(1 to 16);
|
288 |
|
|
variable data8_str: string(1 to 8);
|
289 |
|
|
variable addr_ok, data16_ok1, data16_ok2, data16_ok3, data8_ok : boolean;
|
290 |
|
|
variable firstChar: character;
|
291 |
|
|
|
292 |
|
|
begin
|
293 |
|
|
-- fill with default value
|
294 |
|
|
for i in 0 to depth - 1 loop
|
295 |
|
|
temp_mem(i) := default_value;
|
296 |
|
|
--temp_mem(i) := std_logic_vector(to_unsigned(i, 9)) & "00000000000000000000000000000000000000000000000";
|
297 |
|
|
end loop;
|
298 |
|
|
assert false report "init_bytememory(): initialized " & integer'image(depth) & " words of memory to default value " severity note;
|
299 |
|
|
|
300 |
|
|
-- parse the file for the data
|
301 |
|
|
assert false report "init_bytememory(): loading memory from file " & input_file_name severity note;
|
302 |
|
|
loop
|
303 |
|
|
exit when endfile(input_file); --till the end of file is reached continue.
|
304 |
|
|
line_current := line_current + 1;
|
305 |
|
|
readline (input_file, input_line);
|
306 |
|
|
--next when input_line'length = 0; -- Skip empty lines
|
307 |
|
|
report "init_mem(): parsing line " & integer'image(line_current) severity note;
|
308 |
|
|
--report "[" & integer'image(input_line'left) & "]" severity note;
|
309 |
|
|
address := X"0000";
|
310 |
|
|
word := X"00000000000000";
|
311 |
|
|
|
312 |
|
|
read(input_line, firstChar);
|
313 |
|
|
--exit when endline(input_line);
|
314 |
|
|
addr_ok := true;
|
315 |
|
|
report "addr_str='" & firstChar & "'" severity note;
|
316 |
|
|
case firstChar is
|
317 |
|
|
when ';' =>
|
318 |
|
|
--report "Semicolon detected, line is treated as comment" severity note;
|
319 |
|
|
line_cnt_ignored := line_cnt_ignored + 1;
|
320 |
|
|
when '0' to '9' | 'A' to 'F' =>
|
321 |
|
|
read(input_line, addr_str, addr_ok);
|
322 |
|
|
read(input_line, data16_str1, data16_ok1);
|
323 |
|
|
read(input_line, data16_str2, data16_ok2);
|
324 |
|
|
read(input_line, data16_str3, data16_ok3);
|
325 |
|
|
read(input_line, data8_str, data8_ok);
|
326 |
|
|
--if (addr_ok and data16_ok1 and data16_ok2 and data16_ok3 and data8_ok) then
|
327 |
|
|
address := parseHex16(firstChar & addr_str);
|
328 |
|
|
word := parseBinary16(data16_str1) & parseBinary16(data16_str2) & parseBinary16(data16_str3) & parseBinary8(data8_str);
|
329 |
|
|
|
330 |
|
|
temp_mem(to_integer(unsigned(address))) := word;
|
331 |
|
|
line_cnt_accepted := line_cnt_accepted + 1;
|
332 |
|
|
report "init_bytememory(): line " & integer'image(line_current) & " parsed and accepted for address " & integer'image(to_integer(unsigned(address))) severity note;
|
333 |
|
|
--else
|
334 |
|
|
-- report "init_bytememory(): line " & integer'image(line_current) & " is ignored due to missing data" severity note;
|
335 |
|
|
-- line_cnt_ignored := line_cnt_ignored + 1;
|
336 |
|
|
--end if;
|
337 |
|
|
when others =>
|
338 |
|
|
report "init_bytememory(): line " & integer'image(line_current) & " is ignored due to unrecognized 1st char" severity note;
|
339 |
|
|
line_cnt_ignored := line_cnt_ignored + 1;
|
340 |
|
|
end case;
|
341 |
|
|
end loop; -- next line in file
|
342 |
|
|
|
343 |
|
|
file_close(input_file);
|
344 |
|
|
|
345 |
|
|
report "init_bytememory(): " & integer'image(line_cnt_accepted) & " total lines parsed and accepted from file " & input_file_name severity note;
|
346 |
|
|
report "init_bytememory(): " & integer'image(line_cnt_ignored) & " total lines parsed and ignored from file " & input_file_name severity note;
|
347 |
|
|
|
348 |
|
|
dump_wordmemory(dump_file_name, depth, temp_mem, dump_file_base);
|
349 |
|
|
|
350 |
|
|
return temp_mem;
|
351 |
|
|
end init_wordmemory;
|
352 |
|
|
|
353 |
|
|
constant data_from_file: t_uinstruction512 := init_wordmemory("./prom/microcode.mif", "./prom/microcode.lst", 0, 512, uCode_default);
|
354 |
|
|
--constant data_from_file: rom_array := init_wordmemory("./prom/microcode.mif", "./prom/microcode.hex", 2, 512, uCode_default);
|
355 |
|
|
|
356 |
|
|
constant data_from_inline: t_uinstruction512 :=
|
357 |
|
|
(
|
358 |
|
|
|
359 |
|
|
others => uCode_nop
|
360 |
|
|
);
|
361 |
|
|
|
362 |
|
|
begin
|
363 |
|
|
data <= data_from_file(to_integer(unsigned(a8)));
|
364 |
|
|
|
365 |
|
|
end Behavioral;
|
366 |
|
|
|