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[/] [am9080_cpu_based_on_microcoded_am29xx_bit-slices/] [trunk/] [clock_divider.vhd] - Blame information for rev 6

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Line No. Rev Author Line
1 6 zpekic
----------------------------------------------------------------------------------
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-- Company: @Home
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-- Engineer: Zoltan Pekic (zpekic@hotmail.com)
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-- 
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-- Create Date:    16:56:54 02/13/2016 
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-- Design Name: 
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-- Module Name:    clock_divider - rtl 
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-- Project Name:   Alarm Clock
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-- Target Devices: Mercury FPGA + Baseboard (http://www.micro-nova.com/mercury/)
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-- Tool versions:  Xilinx ISE 14.7 (nt64)
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity clock_divider is
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    Port ( reset : in  STD_LOGIC;
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           clock : in  STD_LOGIC;
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           slow : out  STD_LOGIC_VECTOR (11 downto 0);
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                          fast : out STD_LOGIC_VECTOR(3 downto 0)
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                         );
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end clock_divider;
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architecture rtl of clock_divider is
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        constant max_count: integer := (100000000 / 4096); -- prescale 
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        signal count: integer range 0 to max_count := 0;
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        signal slow_cnt: unsigned(11 downto 0);
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        signal fast_cnt: unsigned(3 downto 0);
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begin
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        divider: process(clock, reset)
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                begin
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                if reset = '1' then
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                        count <= 0;
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                        slow_cnt <= "000000000000";
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                        fast_cnt <= "0000";
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                else
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                        if rising_edge(clock) then
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                                fast_cnt <= fast_cnt + 1;
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                                if count = max_count then
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                                        count <= 0;
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                                        slow_cnt <= slow_cnt + 1;
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                                else
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                                        count <= count + 1;
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                                end if;
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                        end if;
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                end if;
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        end process;
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   -- connect divider output with internal counter
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        slow <= std_logic_vector(slow_cnt);
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        fast <= std_logic_vector(fast_cnt);
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end rtl;
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