Subversion Repositories am9080_cpu_based_on_microcoded_am29xx_bit-slices

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-- You must compile the wrapper file ram4kx8.vhd when simulating

-- the core, ram4kx8. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified

-- below are supported by Xilinx, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- synthesis translate_off

LIBRARY XilinxCoreLib;

-- synthesis translate_on

ENTITY ram4kx8 IS

  PORT (

    clka : IN STD_LOGIC;

    ena : IN STD_LOGIC;

    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);

    addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

  );

END ram4kx8;

ARCHITECTURE ram4kx8_a OF ram4kx8 IS

-- synthesis translate_off

COMPONENT wrapped_ram4kx8

  PORT (

    clka : IN STD_LOGIC;

    ena : IN STD_LOGIC;

    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);

    addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

  );

END COMPONENT;

-- Configuration specification

  FOR ALL : wrapped_ram4kx8 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)

    GENERIC MAP (

      c_addra_width => 8,

      c_addrb_width => 8,

      c_algorithm => 1,

      c_axi_id_width => 4,

      c_axi_slave_type => 0,

      c_axi_type => 1,

      c_byte_size => 9,

      c_common_clk => 0,

      c_default_data => "FF",

      c_disable_warn_bhv_coll => 0,

      c_disable_warn_bhv_range => 0,

      c_enable_32bit_address => 0,

      c_family => "spartan3",

      c_has_axi_id => 0,

      c_has_ena => 1,

      c_has_enb => 0,

      c_has_injecterr => 0,

      c_has_mem_output_regs_a => 0,

      c_has_mem_output_regs_b => 0,

      c_has_mux_output_regs_a => 0,

      c_has_mux_output_regs_b => 0,

      c_has_regcea => 0,

      c_has_regceb => 0,

      c_has_rsta => 0,

      c_has_rstb => 0,

      c_has_softecc_input_regs_a => 0,

      c_has_softecc_output_regs_b => 0,

      c_init_file => "BlankString",

      c_init_file_name => "no_coe_file_loaded",

      c_inita_val => "0",

      c_initb_val => "0",

      c_interface_type => 0,

      c_load_init_file => 0,

      c_mem_type => 0,

      c_mux_pipeline_stages => 0,

      c_prim_type => 1,

      c_read_depth_a => 256,

      c_read_depth_b => 256,

      c_read_width_a => 8,

      c_read_width_b => 8,

      c_rst_priority_a => "CE",

      c_rst_priority_b => "CE",

      c_rst_type => "SYNC",

      c_rstram_a => 0,

      c_rstram_b => 0,

      c_sim_collision_check => "ALL",

      c_use_bram_block => 0,

      c_use_byte_wea => 0,

      c_use_byte_web => 0,

      c_use_default_data => 1,

      c_use_ecc => 0,

      c_use_softecc => 0,

      c_wea_width => 1,

      c_web_width => 1,

      c_write_depth_a => 256,

      c_write_depth_b => 256,

      c_write_mode_a => "WRITE_FIRST",

      c_write_mode_b => "WRITE_FIRST",

      c_write_width_a => 8,

      c_write_width_b => 8,

      c_xdevicefamily => "spartan3a"

    );

-- synthesis translate_on

BEGIN

-- synthesis translate_off

U0 : wrapped_ram4kx8

  PORT MAP (

    clka => clka,

    ena => ena,

    wea => wea,

    addra => addra,

    dina => dina,

    douta => douta

  );

-- synthesis translate_on

END ram4kx8_a;