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1. Run all hw tests using both A23 and A25 using all cache size configurations for Spartan6, Virtex6 and generic libs.
2. Synthesise both a23 and a25 cores.
   Both cores must pass timing; Spartan6 at 40MHz, Virtex6 at 80Mhz, with max caches
   Check all synthesis warnings, clean up as many as possible.
 
 
 

Line No.	Rev	Author	Line
1	36	csantifort	`1. Run all hw tests using both A23 and A25 using all cache size configurations for Spartan6, Virtex6 and generic libs.`
2	35	csantifort	`2. Synthesise both a23 and a25 cores.`
3			`Both cores must pass timing; Spartan6 at 40MHz, Virtex6 at 80Mhz, with max caches`
4			`Check all synthesis warnings, clean up as many as possible.`
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[/] [amber/] [trunk/] [doc/] [ReleaseChecklist.txt] - Blame information for rev 36