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# ----------------------------------------------------------------
#                                                               //
#   FPGA synthesis Makefile                                     //
#                                                               //
#   This file is part of the Amber project                      //
#   http://www.opencores.org/project,amber                      //
#                                                               //
#   Description                                                 //
#   Runs a full FPGA synthesis of the Amber system.             //
#                                                               //
#   Author(s):                                                  //
#       - Conor Santifort, csantifort.amber@gmail.com           //
#                                                               //
#/ ///////////////////////////////////////////////////////////////
#                                                               //
#  Copyright (C) 2010 Authors and OPENCORES.ORG                 //
#                                                               //
#  This source file may be used and distributed without         //
#  restriction provided that this copyright statement is not    //
#  removed from the file and that any derivative work contains  //
#  the original copyright notice and the associated disclaimer. //
#                                                               //
#  This source file is free software; you can redistribute it   //
#  and/or modify it under the terms of the GNU Lesser General   //
#  Public License as published by the Free Software Foundation; //
#  either version 2.1 of the License, or (at your option) any   //
#  later version.                                               //
#                                                               //
#  This source is distributed in the hope that it will be       //
#  useful, but WITHOUT ANY WARRANTY; without even the implied   //
#  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
#  PURPOSE.  See the GNU Lesser General Public License for more //
#  details.                                                     //
#                                                               //
#  You should have received a copy of the GNU Lesser General    //
#  Public License along with this source; if not, download it   //
#  from http://www.opencores.org/lgpl.shtml                     //
#                                                               //
# ----------------------------------------------------------------
 
# ----------------------------------------------------
# Environment Configuration
# ----------------------------------------------------
 
# Directories
BIN_FOLDER              = ../bin
LOG_FOLDER              = ../logs
BITFILE_FOLDER          = ../bitfiles
 
# Can supply different work directories
# for multiple runs in parallel
ifdef WORK
    WORK_FOLDER             = ../$(WORK)
else
    WORK_FOLDER             = ../work0
endif
 
VERILOG_INCLUDE_PATH    = ../../vlog/lib ../../../sw/boot-loader
 
# Name of top level verilog file (must be the same as its module name)
RTL_TOP         = system
 
 
 
# ----------------------------------------------------
# Build Configuration
# ----------------------------------------------------
 
# AMBER_CLK_DIVIDER
# Sets the system clock frequency
# For Spartan-6 divide 800MHz by this number to get the frequency
#   e.g. AMBER_CLK_DIVIDER=24
#   800 MHz / 24 = 33.33 MHz
# For Virtex-6 divide 1200MHz by this number to get the frequency
 
# Select either the A23 or A25 core
ifdef A25
    AMBER_CORE = AMBER_A25_CORE
else
    AMBER_CORE = AMBER_A23_CORE
endif
 
 
## FPGA type
ifdef VIRTEX6
    # Virtex-6 device
    XILINX_FPGA     = xc6vlx75tff784-3
    XST_DEFINES     = XILINX_FPGA XILINX_VIRTEX6_FPGA  $(AMBER_CORE) AMBER_CLK_DIVIDER=15
    # Xilinx placement and timing constraints
    XST_CONST_FILE  = xv6_constraints.ucf
    # List of verilog source files for Xilinx Virtex-6 device
    XST_PROJ_FILE   = xv6_source_files.prj
else
    # The spartan6 device used on SP605 Development board
    XILINX_FPGA     = xc6slx45tfgg484-3
    XST_DEFINES     = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20
    # Xilinx placement and timing constraints
    XST_CONST_FILE  = xs6_constraints.ucf
    # List of verilog source files for Xilinx Spartan-6 device
    XST_PROJ_FILE   = xs6_source_files.prj
endif
 
 
# ----------------------------------------------------
# Focus on speed or area
# ----------------------------------------------------
#OPT = area
OPT = speed
 
 
# ----------------------------------------------------
# Xilinx XST Compile Options
# ----------------------------------------------------
 
XST_OPTIONS   =  -vlgincdir {$(VERILOG_INCLUDE_PATH)}  \
                 -ifmt mixed                           \
                 -ofmt NGC                             \
                 -p $(XILINX_FPGA)                     \
                 -opt_mode $(OPT)                      \
                 -opt_level 2                          \
                 -power NO                             \
                 -iuc NO                               \
                 -keep_hierarchy NO                    \
                 -rtlview Yes                          \
                 -glob_opt AllClockNets                \
                 -read_cores YES                       \
                 -write_timing_constraints NO          \
                 -cross_clock_analysis NO              \
                 -hierarchy_separator /                \
                 -bus_delimiter \<\>                   \
                 -case maintain                        \
                 -slice_utilization_ratio 100          \
                 -bram_utilization_ratio 100           \
                 -dsp_utilization_ratio 100            \
                 -fsm_extract YES                      \
                 -fsm_encoding Auto                    \
                 -safe_implementation No               \
                 -fsm_style lut                        \
                 -ram_extract Yes                      \
                 -ram_style Auto                       \
                 -rom_extract Yes                      \
                 -shreg_extract YES                    \
                 -rom_style Auto                       \
                 -auto_bram_packing NO                 \
                 -resource_sharing YES                 \
                 -async_to_sync NO                     \
                 -max_fanout 10000                     \
                 -bufg 32                              \
                 -register_duplication YES             \
                 -register_balancing No                \
                 -optimize_primitives NO               \
                 -use_clock_enable Auto                \
                 -use_sync_set Auto                    \
                 -use_sync_reset Auto                  \
                 -iob auto                             \
                 -equivalent_register_removal YES      \
                 -slice_utilization_ratio_maxmargin 5
 
# ----------------------------------------------------
 
RUN_ID      = $(shell cat $(WORK_FOLDER)/run_id.txt)
MAP_SEED    = $(shell $(BIN_FOLDER)/increment_seed.sh $(WORK_FOLDER)/seed.txt)
# ----------------------------------------------------
 
 
all : bitgen trce
 
new : clean all
 
map : cleanmap all
 
help :
        @echo ""
        @echo "Valid targets:"
        @echo "              new        Start a new run with a new ID"
        @echo "              all        Continue last run from where ever it left off"
        @echo "              map        Rerun the map and par with a new seed"
        @echo "              clean      Delete all temporary files"
        @echo "              bitgen     Create a bitfile. Don't run trce"
        @echo "              trce       Running timing analysis. Don't run buitgen"
        @echo "              help       Print this message"
        @echo ""
        @echo "Optional switches: VIRTEX6=1 A25=1 WORK="
        @echo "e.g. > make VIRTEX6=1 WORK=work1 map"
 
clean :
        rm -Rf   $(WORK_FOLDER)/*
 
cleanmap :
        if [ -f $(WORK_FOLDER)/$(RTL_TOP).map.ncd ]; then rm $(WORK_FOLDER)/$(RTL_TOP).map.ncd; fi
 
bitgen : $(WORK_FOLDER)/$(RTL_TOP).bit
 
trce : $(WORK_FOLDER)/$(RTL_TOP).trc.twr
 
 
# ----------------------------------------------------
# trce
# ----------------------------------------------------
# Can be done before or after bitgen
$(WORK_FOLDER)/$(RTL_TOP).trc.twr : $(WORK_FOLDER)/$(RTL_TOP).ncd
        \
        cd $(WORK_FOLDER); \
        trce -v 5 -l 5 -n 5 -xml $(RTL_TOP) $(RTL_TOP).ncd \
          -o $(WORK_FOLDER)/$(RTL_TOP).trc.twr \
          $(RTL_TOP).pcf
        cp $(WORK_FOLDER)/$(RTL_TOP).trc.twr $(LOG_FOLDER)/$(RTL_TOP).trc.$(RUN_ID).twr
 
 
# ----------------------------------------------------
# bitgen
# ----------------------------------------------------
$(WORK_FOLDER)/$(RTL_TOP).bit : $(WORK_FOLDER)/$(RTL_TOP).ncd
        \
        cd $(WORK_FOLDER); \
        bitgen -intstyle xflow -f $(BIN_FOLDER)/bitfile_config.ut $(RTL_TOP).ncd
        cp $(WORK_FOLDER)/$(RTL_TOP).bit $(BITFILE_FOLDER)/$(RTL_TOP).$(RUN_ID).bit
        mv $(WORK_FOLDER)/$(RTL_TOP).bgn $(LOG_FOLDER)/$(RTL_TOP).bit.$(RUN_ID).bgn
 
 
# ----------------------------------------------------
# par
# ----------------------------------------------------
# -xe c  = Extra Effort, continue on Impossible
# -p means don't run the placer. We use map as the placer
# -k =  Re-entrant route. Keep the current placement. Continue the routing
#       using the existing routing as a starting point.
$(WORK_FOLDER)/$(RTL_TOP).ncd : $(WORK_FOLDER)/$(RTL_TOP).map.ncd
        \
        cd $(WORK_FOLDER); \
        par  -intstyle xflow -w -k -ol high $(RTL_TOP).map.ncd $(RTL_TOP).ncd $(RTL_TOP).pcf
        cp $(WORK_FOLDER)/$(RTL_TOP)_pad.txt $(LOG_FOLDER)/$(RTL_TOP).pad.$(RUN_ID).txt
 
# ----------------------------------------------------
# map
# ----------------------------------------------------
$(WORK_FOLDER)/$(RTL_TOP).map.ncd : $(WORK_FOLDER)/$(RTL_TOP).ngd
        cd $(WORK_FOLDER); \
        map -intstyle xflow        \
          -p $(XILINX_FPGA)        \
          -ol high                 \
          -t $(MAP_SEED)           \
          -w                       \
          -ignore_keep_hierarchy   \
          -detail                  \
          -timing                  \
          -register_duplication on \
          -lc auto                 \
          -xe c -mt off -ir off    \
          -pr off  -power off      \
          -o $(RTL_TOP).map.ncd    \
          $(RTL_TOP).ngd           \
          $(RTL_TOP).pcf
        cp $(WORK_FOLDER)/$(RTL_TOP).map.mrp $(LOG_FOLDER)/$(RTL_TOP).map.$(RUN_ID).mrp
 
 
# ----------------------------------------------------
# ngdbuild
# ----------------------------------------------------
$(WORK_FOLDER)/$(RTL_TOP).ngd : $(WORK_FOLDER)/$(RTL_TOP).ngc $(BIN_FOLDER)/$(XST_CONST_FILE)
        cd $(WORK_FOLDER); \
        ngdbuild -intstyle xflow -verbose -p $(XILINX_FPGA) \
          -dd _ngo  -nt on \
          -uc $(BIN_FOLDER)/$(XST_CONST_FILE) $(RTL_TOP).ngc $(RTL_TOP).ngd
 
 
# ----------------------------------------------------
# xst
# ----------------------------------------------------
 
# Note -iobuf YES is needed for the top-level verilog
# module synthesis
 
$(WORK_FOLDER)/$(RTL_TOP).ngc : $(WORK_FOLDER)/run_id.txt $(XST_PROJ_FILE)
        @echo "work: $(WORK_FOLDER)" > $(LOG_FOLDER)/$(RTL_TOP).cfg.$(RUN_ID).txt
        @echo "$(XST_DEFINES)" >> $(LOG_FOLDER)/$(RTL_TOP).cfg.$(RUN_ID).txt
        export XST_DESIGN=$(RTL_TOP)
        export XST_OFN=$(RTL_TOP)
        rm -Rf $(WORK_FOLDER)/$(RTL_TOP)xst $(WORK_FOLDER)/_ngo
        mkdir -p $(WORK_FOLDER)/$(RTL_TOP)xst/tmp $(WORK_FOLDER)/_ngo
        echo "work"                                         > $(WORK_FOLDER)/$(RTL_TOP).lso
        echo "set -tmpdir     ./$(RTL_TOP)xst/tmp"          > $(WORK_FOLDER)/$(RTL_TOP).xst
        echo "set -xsthdpdir  ./$(RTL_TOP)xst"             >> $(WORK_FOLDER)/$(RTL_TOP).xst
        echo "run -ifn $(BIN_FOLDER)/$(XST_PROJ_FILE)"     >> $(WORK_FOLDER)/$(RTL_TOP).xst
        echo "-ofn $(RTL_TOP) -top $(RTL_TOP)"             >> $(WORK_FOLDER)/$(RTL_TOP).xst
        echo "-lso ./$(RTL_TOP).lso"                       >> $(WORK_FOLDER)/$(RTL_TOP).xst
        echo $(XST_OPTIONS)                                >> $(WORK_FOLDER)/$(RTL_TOP).xst
        echo "-iobuf YES"                                  >> $(WORK_FOLDER)/$(RTL_TOP).xst
        echo "-define { $(XST_DEFINES) )}"                 >> $(WORK_FOLDER)/$(RTL_TOP).xst
        cd $(WORK_FOLDER); \
        xst -intstyle xflow -ifn ./$(RTL_TOP).xst -ofn $(LOG_FOLDER)/$(RTL_TOP).xst.$(RUN_ID).srp
 
 
# ----------------------------------------------------
# Generate the Run ID, initial Map seed
# Recompile the boot-loader program - it gets build
# into the FPGA's RamBlocks and uses the run_id as
# the version number
# ----------------------------------------------------
$(WORK_FOLDER)/run_id.txt :
        test -e $(WORK_FOLDER) || mkdir $(WORK_FOLDER)
        test -e $(LOG_FOLDER) || mkdir $(LOG_FOLDER)
        test -e $(BITFILE_FOLDER) || mkdir $(BITFILE_FOLDER)
        echo 0 > $(WORK_FOLDER)/seed.txt
        date +%Y%m%d%H%M%S > $(WORK_FOLDER)/run_id.txt
        $(BIN_FOLDER)/set_fpga_version.sh $(WORK_FOLDER)/run_id.txt
        $(MAKE) -C ../../../sw/boot-loader
 

Line No.	Rev	Author	Line
1	2	csantifort	`# ----------------------------------------------------------------`
2			`# //`
3			`# FPGA synthesis Makefile //`
4			`# //`
5			`# This file is part of the Amber project //`
6			`# http://www.opencores.org/project,amber //`
7			`# //`
8			`# Description //`
9			`# Runs a full FPGA synthesis of the Amber system. //`
10			`# //`
11			`# Author(s): //`
12			`# - Conor Santifort, csantifort.amber@gmail.com //`
13			`# //`
14			`#/ ///////////////////////////////////////////////////////////////`
15			`# //`
16			`# Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`# //`
18			`# This source file may be used and distributed without //`
19			`# restriction provided that this copyright statement is not //`
20			`# removed from the file and that any derivative work contains //`
21			`# the original copyright notice and the associated disclaimer. //`
22			`# //`
23			`# This source file is free software; you can redistribute it //`
24			`# and/or modify it under the terms of the GNU Lesser General //`
25			`# Public License as published by the Free Software Foundation; //`
26			`# either version 2.1 of the License, or (at your option) any //`
27			`# later version. //`
28			`# //`
29			`# This source is distributed in the hope that it will be //`
30			`# useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`# PURPOSE. See the GNU Lesser General Public License for more //`
33			`# details. //`
34			`# //`
35			`# You should have received a copy of the GNU Lesser General //`
36			`# Public License along with this source; if not, download it //`
37			`# from http://www.opencores.org/lgpl.shtml //`
38			`# //`
39			`# ----------------------------------------------------------------`
40
41			`# ----------------------------------------------------`
42			`# Environment Configuration`
43			`# ----------------------------------------------------`
44
45			`# Directories`
46			`BIN_FOLDER = ../bin`
47			`LOG_FOLDER = ../logs`
48			`BITFILE_FOLDER = ../bitfiles`
49
50			`# Can supply different work directories`
51			`# for multiple runs in parallel`
52			`ifdef WORK`
53			`WORK_FOLDER = ../$(WORK)`
54			`else`
55			`WORK_FOLDER = ../work0`
56			`endif`
57
58			`VERILOG_INCLUDE_PATH = ../../vlog/lib ../../../sw/boot-loader`
59
60			`# Name of top level verilog file (must be the same as its module name)`
61			`RTL_TOP = system`
62
63
64
65			`# ----------------------------------------------------`
66			`# Build Configuration`
67			`# ----------------------------------------------------`
68
69			`# AMBER_CLK_DIVIDER`
70			`# Sets the system clock frequency`
71			`# For Spartan-6 divide 800MHz by this number to get the frequency`
72			`# e.g. AMBER_CLK_DIVIDER=24`
73			`# 800 MHz / 24 = 33.33 MHz`
74	43	csantifort	`# For Virtex-6 divide 1200MHz by this number to get the frequency`
75	2	csantifort
76	15	csantifort	`# Select either the A23 or A25 core`
77			`ifdef A25`
78			`AMBER_CORE = AMBER_A25_CORE`
79			`else`
80	19	csantifort	`AMBER_CORE = AMBER_A23_CORE`
81	15	csantifort	`endif`
82
83
84	2	csantifort	`## FPGA type`
85			`ifdef VIRTEX6`
86			`# Virtex-6 device`
87			`XILINX_FPGA = xc6vlx75tff784-3`
88	43	csantifort	`XST_DEFINES = XILINX_FPGA XILINX_VIRTEX6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=15`
89	2	csantifort	`# Xilinx placement and timing constraints`
90			`XST_CONST_FILE = xv6_constraints.ucf`
91	23	csantifort	`# List of verilog source files for Xilinx Virtex-6 device`
92			`XST_PROJ_FILE = xv6_source_files.prj`
93	2	csantifort	`else`
94			`# The spartan6 device used on SP605 Development board`
95			`XILINX_FPGA = xc6slx45tfgg484-3`
96	43	csantifort	`XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20`
97	2	csantifort	`# Xilinx placement and timing constraints`
98			`XST_CONST_FILE = xs6_constraints.ucf`
99	23	csantifort	`# List of verilog source files for Xilinx Spartan-6 device`
100			`XST_PROJ_FILE = xs6_source_files.prj`
101	2	csantifort	`endif`
102
103
104			`# ----------------------------------------------------`
105			`# Focus on speed or area`
106			`# ----------------------------------------------------`
107			`#OPT = area`
108			`OPT = speed`
109
110
111			`# ----------------------------------------------------`
112			`# Xilinx XST Compile Options`
113			`# ----------------------------------------------------`
114
115			`XST_OPTIONS = -vlgincdir {$(VERILOG_INCLUDE_PATH)} \`
116			`-ifmt mixed \`
117			`-ofmt NGC \`
118			`-p $(XILINX_FPGA) \`
119			`-opt_mode $(OPT) \`
120			`-opt_level 2 \`
121			`-power NO \`
122			`-iuc NO \`
123			`-keep_hierarchy NO \`
124			`-rtlview Yes \`
125			`-glob_opt AllClockNets \`
126			`-read_cores YES \`
127			`-write_timing_constraints NO \`
128			`-cross_clock_analysis NO \`
129			`-hierarchy_separator / \`
130			`-bus_delimiter \<\> \`
131			`-case maintain \`
132			`-slice_utilization_ratio 100 \`
133			`-bram_utilization_ratio 100 \`
134			`-dsp_utilization_ratio 100 \`
135			`-fsm_extract YES \`
136			`-fsm_encoding Auto \`
137			`-safe_implementation No \`
138			`-fsm_style lut \`
139			`-ram_extract Yes \`
140			`-ram_style Auto \`
141			`-rom_extract Yes \`
142			`-shreg_extract YES \`
143			`-rom_style Auto \`
144			`-auto_bram_packing NO \`
145			`-resource_sharing YES \`
146			`-async_to_sync NO \`
147			`-max_fanout 10000 \`
148			`-bufg 32 \`
149			`-register_duplication YES \`
150			`-register_balancing No \`
151			`-optimize_primitives NO \`
152			`-use_clock_enable Auto \`
153			`-use_sync_set Auto \`
154			`-use_sync_reset Auto \`
155			`-iob auto \`
156			`-equivalent_register_removal YES \`
157			`-slice_utilization_ratio_maxmargin 5`
158
159			`# ----------------------------------------------------`
160
161			`RUN_ID = $(shell cat $(WORK_FOLDER)/run_id.txt)`
162			`MAP_SEED = $(shell $(BIN_FOLDER)/increment_seed.sh $(WORK_FOLDER)/seed.txt)`
163			`# ----------------------------------------------------`
164
165
166			`all : bitgen trce`
167
168			`new : clean all`
169
170			`map : cleanmap all`
171
172			`help :`
173			`@echo ""`
174			`@echo "Valid targets:"`
175			`@echo " new Start a new run with a new ID"`
176			`@echo " all Continue last run from where ever it left off"`
177			`@echo " map Rerun the map and par with a new seed"`
178			`@echo " clean Delete all temporary files"`
179			`@echo " bitgen Create a bitfile. Don't run trce"`
180			`@echo " trce Running timing analysis. Don't run buitgen"`
181			`@echo " help Print this message"`
182			`@echo ""`
183	15	csantifort	`@echo "Optional switches: VIRTEX6=1 A25=1 WORK="`
184	2	csantifort	`@echo "e.g. > make VIRTEX6=1 WORK=work1 map"`
185
186			`clean :`
187			`rm -Rf $(WORK_FOLDER)/*`
188
189			`cleanmap :`
190			`if [ -f $(WORK_FOLDER)/$(RTL_TOP).map.ncd ]; then rm $(WORK_FOLDER)/$(RTL_TOP).map.ncd; fi`
191
192			`bitgen : $(WORK_FOLDER)/$(RTL_TOP).bit`
193
194			`trce : $(WORK_FOLDER)/$(RTL_TOP).trc.twr`
195
196
197			`# ----------------------------------------------------`
198			`# trce`
199			`# ----------------------------------------------------`
200			`# Can be done before or after bitgen`
201			`$(WORK_FOLDER)/$(RTL_TOP).trc.twr : $(WORK_FOLDER)/$(RTL_TOP).ncd`
202			`\`
203			`cd $(WORK_FOLDER); \`
204	35	csantifort	`trce -v 5 -l 5 -n 5 -xml $(RTL_TOP) $(RTL_TOP).ncd \`
205	2	csantifort	`-o $(WORK_FOLDER)/$(RTL_TOP).trc.twr \`
206			`$(RTL_TOP).pcf`
207			`cp $(WORK_FOLDER)/$(RTL_TOP).trc.twr $(LOG_FOLDER)/$(RTL_TOP).trc.$(RUN_ID).twr`
208
209
210			`# ----------------------------------------------------`
211			`# bitgen`
212			`# ----------------------------------------------------`
213			`$(WORK_FOLDER)/$(RTL_TOP).bit : $(WORK_FOLDER)/$(RTL_TOP).ncd`
214			`\`
215			`cd $(WORK_FOLDER); \`
216			`bitgen -intstyle xflow -f $(BIN_FOLDER)/bitfile_config.ut $(RTL_TOP).ncd`
217			`cp $(WORK_FOLDER)/$(RTL_TOP).bit $(BITFILE_FOLDER)/$(RTL_TOP).$(RUN_ID).bit`
218			`mv $(WORK_FOLDER)/$(RTL_TOP).bgn $(LOG_FOLDER)/$(RTL_TOP).bit.$(RUN_ID).bgn`
219
220
221			`# ----------------------------------------------------`
222			`# par`
223			`# ----------------------------------------------------`
224			`# -xe c = Extra Effort, continue on Impossible`
225			`# -p means don't run the placer. We use map as the placer`
226			`# -k = Re-entrant route. Keep the current placement. Continue the routing`
227			`# using the existing routing as a starting point.`
228			`$(WORK_FOLDER)/$(RTL_TOP).ncd : $(WORK_FOLDER)/$(RTL_TOP).map.ncd`
229			`\`
230			`cd $(WORK_FOLDER); \`
231			`par -intstyle xflow -w -k -ol high $(RTL_TOP).map.ncd $(RTL_TOP).ncd $(RTL_TOP).pcf`
232			`cp $(WORK_FOLDER)/$(RTL_TOP)_pad.txt $(LOG_FOLDER)/$(RTL_TOP).pad.$(RUN_ID).txt`
233
234			`# ----------------------------------------------------`
235			`# map`
236			`# ----------------------------------------------------`
237			`$(WORK_FOLDER)/$(RTL_TOP).map.ncd : $(WORK_FOLDER)/$(RTL_TOP).ngd`
238			`cd $(WORK_FOLDER); \`
239	43	csantifort	`map -intstyle xflow \`
240			`-p $(XILINX_FPGA) \`
241			`-ol high \`
242			`-t $(MAP_SEED) \`
243			`-w \`
244			`-ignore_keep_hierarchy \`
245			`-detail \`
246			`-timing \`
247			`-register_duplication on \`
248			`-lc auto \`
249			`-xe c -mt off -ir off \`
250			`-pr off -power off \`
251			`-o $(RTL_TOP).map.ncd \`
252			`$(RTL_TOP).ngd \`
253	2	csantifort	`$(RTL_TOP).pcf`
254			`cp $(WORK_FOLDER)/$(RTL_TOP).map.mrp $(LOG_FOLDER)/$(RTL_TOP).map.$(RUN_ID).mrp`
255
256
257			`# ----------------------------------------------------`
258			`# ngdbuild`
259			`# ----------------------------------------------------`
260			`$(WORK_FOLDER)/$(RTL_TOP).ngd : $(WORK_FOLDER)/$(RTL_TOP).ngc $(BIN_FOLDER)/$(XST_CONST_FILE)`
261			`cd $(WORK_FOLDER); \`
262			`ngdbuild -intstyle xflow -verbose -p $(XILINX_FPGA) \`
263			`-dd _ngo -nt on \`
264			`-uc $(BIN_FOLDER)/$(XST_CONST_FILE) $(RTL_TOP).ngc $(RTL_TOP).ngd`
265
266
267			`# ----------------------------------------------------`
268			`# xst`
269			`# ----------------------------------------------------`
270
271			`# Note -iobuf YES is needed for the top-level verilog`
272			`# module synthesis`
273
274	21	csantifort	`$(WORK_FOLDER)/$(RTL_TOP).ngc : $(WORK_FOLDER)/run_id.txt $(XST_PROJ_FILE)`
275			`@echo "work: $(WORK_FOLDER)" > $(LOG_FOLDER)/$(RTL_TOP).cfg.$(RUN_ID).txt`
276			`@echo "$(XST_DEFINES)" >> $(LOG_FOLDER)/$(RTL_TOP).cfg.$(RUN_ID).txt`
277	2	csantifort	`export XST_DESIGN=$(RTL_TOP)`
278			`export XST_OFN=$(RTL_TOP)`
279			`rm -Rf $(WORK_FOLDER)/$(RTL_TOP)xst $(WORK_FOLDER)/_ngo`
280			`mkdir -p $(WORK_FOLDER)/$(RTL_TOP)xst/tmp $(WORK_FOLDER)/_ngo`
281			`echo "work" > $(WORK_FOLDER)/$(RTL_TOP).lso`
282			`echo "set -tmpdir ./$(RTL_TOP)xst/tmp" > $(WORK_FOLDER)/$(RTL_TOP).xst`
283			`echo "set -xsthdpdir ./$(RTL_TOP)xst" >> $(WORK_FOLDER)/$(RTL_TOP).xst`
284			`echo "run -ifn $(BIN_FOLDER)/$(XST_PROJ_FILE)" >> $(WORK_FOLDER)/$(RTL_TOP).xst`
285			`echo "-ofn $(RTL_TOP) -top $(RTL_TOP)" >> $(WORK_FOLDER)/$(RTL_TOP).xst`
286			`echo "-lso ./$(RTL_TOP).lso" >> $(WORK_FOLDER)/$(RTL_TOP).xst`
287			`echo $(XST_OPTIONS) >> $(WORK_FOLDER)/$(RTL_TOP).xst`
288			`echo "-iobuf YES" >> $(WORK_FOLDER)/$(RTL_TOP).xst`
289			`echo "-define { $(XST_DEFINES) )}" >> $(WORK_FOLDER)/$(RTL_TOP).xst`
290			`cd $(WORK_FOLDER); \`
291			`xst -intstyle xflow -ifn ./$(RTL_TOP).xst -ofn $(LOG_FOLDER)/$(RTL_TOP).xst.$(RUN_ID).srp`
292
293
294			`# ----------------------------------------------------`
295			`# Generate the Run ID, initial Map seed`
296			`# Recompile the boot-loader program - it gets build`
297			`# into the FPGA's RamBlocks and uses the run_id as`
298			`# the version number`
299			`# ----------------------------------------------------`
300			`$(WORK_FOLDER)/run_id.txt :`
301			`test -e $(WORK_FOLDER) \|\| mkdir $(WORK_FOLDER)`
302			`test -e $(LOG_FOLDER) \|\| mkdir $(LOG_FOLDER)`
303			`test -e $(BITFILE_FOLDER) \|\| mkdir $(BITFILE_FOLDER)`
304			`echo 0 > $(WORK_FOLDER)/seed.txt`
305			`date +%Y%m%d%H%M%S > $(WORK_FOLDER)/run_id.txt`
306			`$(BIN_FOLDER)/set_fpga_version.sh $(WORK_FOLDER)/run_id.txt`
307			`$(MAKE) -C ../../../sw/boot-loader`
308	19	csantifort

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