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csantifort |
# ----------------------------------------------------------------
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# //
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# Xilinx FPGA synthesis constraints file //
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# //
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# This file is part of the Amber project //
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# http://www.opencores.org/project,amber //
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# //
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# Description //
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# //
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# Author(s): //
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# - Conor Santifort, csantifort.amber@gmail.com //
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# //
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#/ ///////////////////////////////////////////////////////////////
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# //
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# Copyright (C) 2010 Authors and OPENCORES.ORG //
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# //
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# This source file may be used and distributed without //
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# restriction provided that this copyright statement is not //
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# removed from the file and that any derivative work contains //
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# the original copyright notice and the associated disclaimer. //
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# //
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# This source file is free software; you can redistribute it //
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# and/or modify it under the terms of the GNU Lesser General //
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# Public License as published by the Free Software Foundation; //
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# either version 2.1 of the License, or (at your option) any //
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# later version. //
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# //
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# This source is distributed in the hope that it will be //
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# useful, but WITHOUT ANY WARRANTY; without even the implied //
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# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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# PURPOSE. See the GNU Lesser General Public License for more //
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# details. //
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# //
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# You should have received a copy of the GNU Lesser General //
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# Public License along with this source; if not, download it //
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# from http://www.opencores.org/lgpl.shtml //
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# //
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# ----------------------------------------------------------------
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############################################################################
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# VCC AUX VOLTAGE
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############################################################################
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CONFIG VCCAUX=2.5;
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############################################################################
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## Clock constraints
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############################################################################
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# 200MHz board clock that feeds the PLL
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NET "u_clocks_resets/brd_clk_ibufg" TNM_NET = "BRD_CLK";
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TIMESPEC "TS_PLL_CLK" = PERIOD "BRD_CLK" 5.0 ns HIGH 50 %;
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# 25 MHz Ethernet MII transmit clock
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NET "mtx_clk_pad_i" TNM_NET = "MTX_CLK";
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TIMESPEC "TS_MTX_CLK" = PERIOD "MTX_CLK" 40.0 ns HIGH 50 %;
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# 25 MHz Ethernet MII receive clock
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NET "mrx_clk_pad_i" TNM_NET = "MRX_CLK";
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TIMESPEC "TS_MRX_CLK" = PERIOD "MRX_CLK" 40.0 ns HIGH 50 %;
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# False paths between clocks
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PIN "u_mcb_ddr3/memc3_infrastructure_inst/u_pll_adv.CLKOUT3" TNM = "DDR_CLK";
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PIN "u_clocks_resets/u_pll_adv.CLKOUT2" TNM = "SYS_CLK";
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TIMESPEC "TS_false1" = FROM "DDR_CLK" TO "SYS_CLK" TIG;
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############################################################################
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## I/O TERMINATION
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############################################################################
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NET "ddr3_dq[*]" IN_TERM = UNTUNED_SPLIT_50;
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NET "ddr3_dqs_p[*]" IN_TERM = UNTUNED_SPLIT_50;
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NET "ddr3_dqs_n[*]" IN_TERM = UNTUNED_SPLIT_50;
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############################################################################
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# I/O STANDARDS
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############################################################################
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NET "ddr3_dq[*]" IOSTANDARD = SSTL15_II;
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NET "ddr3_addr[*]" IOSTANDARD = SSTL15_II;
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NET "ddr3_ba[*]" IOSTANDARD = SSTL15_II;
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NET "ddr3_dqs_p[*]" IOSTANDARD = DIFF_SSTL15_II;
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NET "ddr3_dqs_n[*]" IOSTANDARD = DIFF_SSTL15_II;
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NET "ddr3_ck_p" IOSTANDARD = DIFF_SSTL15_II;
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NET "ddr3_ck_n" IOSTANDARD = DIFF_SSTL15_II;
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NET "ddr3_cke" IOSTANDARD = SSTL15_II;
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NET "ddr3_ras_n" IOSTANDARD = SSTL15_II;
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NET "ddr3_cas_n" IOSTANDARD = SSTL15_II;
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NET "ddr3_we_n" IOSTANDARD = SSTL15_II;
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NET "ddr3_odt" IOSTANDARD = SSTL15_II;
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NET "ddr3_reset_n" IOSTANDARD = SSTL15_II;
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NET "ddr3_dm[*]" IOSTANDARD = SSTL15_II;
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NET "mcb3_rzq" IOSTANDARD = SSTL15_II;
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NET "mcb3_zio" IOSTANDARD = SSTL15_II;
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NET "brd_clk_p" IOSTANDARD = LVDS_25;
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NET "brd_clk_n" IOSTANDARD = LVDS_25;
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NET "brd_rst" IOSTANDARD = LVCMOS15;
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NET "mtx_clk_pad_i" IOSTANDARD = LVCMOS25;
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NET "mtxd_pad_o[*]" IOSTANDARD = LVCMOS25;
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NET "mtxen_pad_o" IOSTANDARD = LVCMOS25;
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NET "mtxerr_pad_o" IOSTANDARD = LVCMOS25;
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NET "mrx_clk_pad_i" IOSTANDARD = LVCMOS25;
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NET "mrxd_pad_i[*]" IOSTANDARD = LVCMOS25;
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NET "mrxdv_pad_i" IOSTANDARD = LVCMOS25;
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NET "mrxerr_pad_i" IOSTANDARD = LVCMOS25;
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NET "mcoll_pad_i" IOSTANDARD = LVCMOS25;
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NET "mcrs_pad_i" IOSTANDARD = LVCMOS25;
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NET "md_pad_io" IOSTANDARD = LVCMOS25;
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NET "mdc_pad_o" IOSTANDARD = LVCMOS25;
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NET "phy_reset_n" IOSTANDARD = LVCMOS25;
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############################################################################
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# Pin Location Constraints
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############################################################################
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NET "brd_rst" LOC = H8;
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NET "brd_clk_n" LOC = K22;
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NET "brd_clk_p" LOC = K21;
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NET "o_uart0_cts" LOC = F18;
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NET "i_uart0_rts" LOC = F19;
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NET "o_uart0_rx" LOC = B21;
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NET "i_uart0_tx" LOC = H17;
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############################################################################
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# DDR3 Interface pin locations
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############################################################################
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NET "ddr3_addr[0]" LOC = "K2" ;
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NET "ddr3_addr[10]" LOC = "J4" ;
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NET "ddr3_addr[11]" LOC = "E1" ;
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NET "ddr3_addr[12]" LOC = "F1" ;
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NET "ddr3_addr[1]" LOC = "K1" ;
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NET "ddr3_addr[2]" LOC = "K5" ;
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NET "ddr3_addr[3]" LOC = "M6" ;
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NET "ddr3_addr[4]" LOC = "H3" ;
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NET "ddr3_addr[5]" LOC = "M3" ;
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NET "ddr3_addr[6]" LOC = "L4" ;
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NET "ddr3_addr[7]" LOC = "K6" ;
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NET "ddr3_addr[8]" LOC = "G3" ;
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NET "ddr3_addr[9]" LOC = "G1" ;
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NET "ddr3_ba[0]" LOC = "J3" ;
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NET "ddr3_ba[1]" LOC = "J1" ;
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NET "ddr3_ba[2]" LOC = "H1" ;
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NET "ddr3_cas_n" LOC = "M4" ;
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NET "ddr3_ck_p" LOC = "K4" ;
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NET "ddr3_ck_n" LOC = "K3" ;
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NET "ddr3_cke" LOC = "F2" ;
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NET "ddr3_dm[0]" LOC = "N4" ;
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NET "ddr3_dq[0]" LOC = "R3" ;
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NET "ddr3_dq[10]" LOC = "U3" ;
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NET "ddr3_dq[11]" LOC = "U1" ;
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NET "ddr3_dq[12]" LOC = "W3" ;
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NET "ddr3_dq[13]" LOC = "W1" ;
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NET "ddr3_dq[14]" LOC = "Y2" ;
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NET "ddr3_dq[15]" LOC = "Y1" ;
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NET "ddr3_dq[1]" LOC = "R1" ;
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NET "ddr3_dq[2]" LOC = "P2" ;
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NET "ddr3_dq[3]" LOC = "P1" ;
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NET "ddr3_dq[4]" LOC = "L3" ;
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NET "ddr3_dq[5]" LOC = "L1" ;
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NET "ddr3_dq[6]" LOC = "M2" ;
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NET "ddr3_dq[7]" LOC = "M1" ;
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NET "ddr3_dq[8]" LOC = "T2" ;
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NET "ddr3_dq[9]" LOC = "T1" ;
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NET "ddr3_dqs_p[0]" LOC = "N3" ;
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NET "ddr3_dqs_n[0]" LOC = "N1" ;
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NET "ddr3_odt" LOC = "L6" ;
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NET "ddr3_ras_n" LOC = "M5" ;
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NET "ddr3_reset_n" LOC = "E3" ;
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NET "ddr3_dm[1]" LOC = "P3" ;
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NET "ddr3_dqs_p[1]" LOC = "V2" ;
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NET "ddr3_dqs_n[1]" LOC = "V1" ;
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NET "ddr3_we_n" LOC = "H2" ;
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# The following pins are available for used as RZQ or ZIO pins#
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NET "mcb3_rzq" LOC = "K7" ;
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NET "mcb3_zio" LOC = "R7" ;
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############################################################################
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# Ethernet MII MAC to PHY interface
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############################################################################
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NET "mtx_clk_pad_i" LOC = "L20" ;
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NET "mtxd_pad_o[0]" LOC = "U10" ;
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NET "mtxd_pad_o[1]" LOC = "T10" ;
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NET "mtxd_pad_o[2]" LOC = "AB8" ;
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NET "mtxd_pad_o[3]" LOC = "AA8" ;
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NET "mtxen_pad_o" LOC = "T8" ;
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NET "mtxerr_pad_o" LOC = "U8" ;
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NET "mrx_clk_pad_i" LOC = "P20" ;
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NET "mrxd_pad_i[0]" LOC = "P19" ;
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NET "mrxd_pad_i[1]" LOC = "Y22" ;
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NET "mrxd_pad_i[2]" LOC = "Y21" ;
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NET "mrxd_pad_i[3]" LOC = "W22" ;
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NET "mrxdv_pad_i" LOC = "T22" ;
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NET "mrxerr_pad_i" LOC = "U20" ;
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NET "mcoll_pad_i" LOC = "M16" ;
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NET "mcrs_pad_i" LOC = "N15" ;
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NET "md_pad_io" LOC = "V20" ;
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NET "mdc_pad_o" LOC = "R19" ;
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NET "phy_reset_n" LOC = "J22" ;
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