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[/] [amber/] [trunk/] [hw/] [fpga/] [bin/] [xs6_source_files.prj] - Blame information for rev 61

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1 2 csantifort 
# ----------------------------------------------------------------
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#                                                               //
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#   Xilinx Spartan-6 FPGA synthesis Verilog source file list    //
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#                                                               //
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#   This file is part of the Amber project                      //
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#   http://www.opencores.org/project,amber                      //
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#                                                               //
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#   Description                                                 //
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#                                                               //
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#   Author(s):                                                  //
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#       - Conor Santifort, csantifort.amber@gmail.com           //
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#                                                               //
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#/ ///////////////////////////////////////////////////////////////
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#                                                               //
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#  Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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#                                                               //
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#  This source file may be used and distributed without         //
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#  restriction provided that this copyright statement is not    //
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#  removed from the file and that any derivative work contains  //
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#  the original copyright notice and the associated disclaimer. //
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#                                                               //
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#  This source file is free software; you can redistribute it   //
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#  and/or modify it under the terms of the GNU Lesser General   //
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#  Public License as published by the Free Software Foundation; //
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#  either version 2.1 of the License, or (at your option) any   //
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#  later version.                                               //
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#                                                               //
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#  This source is distributed in the hope that it will be       //
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#  useful, but WITHOUT ANY WARRANTY; without even the implied   //
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#  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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#  PURPOSE.  See the GNU Lesser General Public License for more //
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#  details.                                                     //
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#                                                               //
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#  You should have received a copy of the GNU Lesser General    //
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#  Public License along with this source; if not, download it   //
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#  from http://www.opencores.org/lgpl.shtml                     //
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#                                                               //
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# ----------------------------------------------------------------
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# System
41 36 csantifort 
verilog work ../../vlog/system/boot_mem32.v
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verilog work ../../vlog/system/boot_mem128.v
43 2 csantifort 
verilog work ../../vlog/system/clocks_resets.v
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verilog work ../../vlog/system/interrupt_controller.v
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verilog work ../../vlog/system/system.v
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verilog work ../../vlog/system/test_module.v
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verilog work ../../vlog/system/timer_module.v
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verilog work ../../vlog/system/uart.v
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verilog work ../../vlog/system/wb_xs6_ddr3_bridge.v
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verilog work ../../vlog/system/wb_xv6_ddr3_bridge.v
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verilog work ../../vlog/system/wishbone_arbiter.v
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verilog work ../../vlog/system/afifo.v
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verilog work ../../vlog/system/ddr3_afifo.v
54 35 csantifort 
verilog work ../../vlog/system/ethmac_wb.v
55 2 csantifort 
 
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# EthMac
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verilog work ../../vlog/ethmac/eth_clockgen.v
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verilog work ../../vlog/ethmac/eth_crc.v
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verilog work ../../vlog/ethmac/eth_fifo.v
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verilog work ../../vlog/ethmac/eth_maccontrol.v
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verilog work ../../vlog/ethmac/eth_macstatus.v
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verilog work ../../vlog/ethmac/eth_miim.v
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verilog work ../../vlog/ethmac/eth_outputcontrol.v
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verilog work ../../vlog/ethmac/eth_random.v
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verilog work ../../vlog/ethmac/eth_receivecontrol.v
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verilog work ../../vlog/ethmac/eth_registers.v
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verilog work ../../vlog/ethmac/eth_register.v
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verilog work ../../vlog/ethmac/eth_rxaddrcheck.v
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verilog work ../../vlog/ethmac/eth_rxcounters.v
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verilog work ../../vlog/ethmac/eth_rxethmac.v
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verilog work ../../vlog/ethmac/eth_rxstatem.v
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verilog work ../../vlog/ethmac/eth_shiftreg.v
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verilog work ../../vlog/ethmac/eth_spram_256x32.v
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verilog work ../../vlog/ethmac/eth_top.v
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verilog work ../../vlog/ethmac/eth_transmitcontrol.v
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verilog work ../../vlog/ethmac/eth_txcounters.v
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verilog work ../../vlog/ethmac/eth_txethmac.v
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verilog work ../../vlog/ethmac/eth_txstatem.v
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verilog work ../../vlog/ethmac/eth_wishbone.v
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verilog work ../../vlog/ethmac/xilinx_dist_ram_16x32.v
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82 15 csantifort 
# Amber 23
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verilog work ../../vlog/amber23/a23_alu.v
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verilog work ../../vlog/amber23/a23_barrel_shift.v
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verilog work ../../vlog/amber23/a23_cache.v
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verilog work ../../vlog/amber23/a23_coprocessor.v
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verilog work ../../vlog/amber23/a23_core.v
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verilog work ../../vlog/amber23/a23_decode.v
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verilog work ../../vlog/amber23/a23_execute.v
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verilog work ../../vlog/amber23/a23_fetch.v
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verilog work ../../vlog/amber23/a23_multiply.v
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verilog work ../../vlog/amber23/a23_register_bank.v
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verilog work ../../vlog/amber23/a23_wishbone.v
94 2 csantifort 
 
95 15 csantifort 
# Amber 25
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verilog work ../../vlog/amber25/a25_alu.v
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verilog work ../../vlog/amber25/a25_barrel_shift.v
98 35 csantifort 
verilog work ../../vlog/amber25/a25_shifter.v
99 15 csantifort 
verilog work ../../vlog/amber25/a25_coprocessor.v
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verilog work ../../vlog/amber25/a25_core.v
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verilog work ../../vlog/amber25/a25_dcache.v
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verilog work ../../vlog/amber25/a25_decode.v
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verilog work ../../vlog/amber25/a25_execute.v
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verilog work ../../vlog/amber25/a25_fetch.v
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verilog work ../../vlog/amber25/a25_icache.v
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verilog work ../../vlog/amber25/a25_mem.v
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verilog work ../../vlog/amber25/a25_multiply.v
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verilog work ../../vlog/amber25/a25_register_bank.v
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verilog work ../../vlog/amber25/a25_wishbone.v
110 35 csantifort 
verilog work ../../vlog/amber25/a25_wishbone_buf.v
111 15 csantifort 
verilog work ../../vlog/amber25/a25_write_back.v
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113 2 csantifort 
# Xilinx Spartan-6 FPGA Hardware wrappers
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verilog work ../../vlog/lib/xs6_addsub_n.v
115 61 csantifort 
verilog work ../../vlog/lib/xs6_sram_4096x32_byte_en.v
116 2 csantifort 
verilog work ../../vlog/lib/xs6_sram_256x128_byte_en.v
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verilog work ../../vlog/lib/xs6_sram_256x21_line_en.v
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verilog work ../../vlog/lib/xs6_sram_256x32_byte_en.v
119 36 csantifort 
verilog work ../../vlog/lib/xs6_sram_512x128_byte_en.v
120 61 csantifort 
verilog work ../../vlog/lib/xs6_sram_1024x128_byte_en.v
121 2 csantifort 
 
122 
# Xilinx Spartan-6 DDR3 I/F
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verilog work ../../vlog/xs6_ddr3/mcb_ddr3.v
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verilog work ../../vlog/xs6_ddr3/iodrp_controller.v
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verilog work ../../vlog/xs6_ddr3/iodrp_mcb_controller.v
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verilog work ../../vlog/xs6_ddr3/mcb_raw_wrapper.v
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verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration_top.v
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verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration.v
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verilog work ../../vlog/xs6_ddr3/memc3_infrastructure.v
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verilog work ../../vlog/xs6_ddr3/memc3_wrapper.v

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