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[/] [amber/] [trunk/] [hw/] [tests/] [addr_ex.S] - Blame information for rev 2

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/*****************************************************************
//                                                              //
//  Amber 2 Core Interrupt Test                                 //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests Address Exception Interrupt                           //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
        @ ---------------------
        @ Exception vectors
        @ ---------------------
        /* 0x00 Reset Interrupt vector address */
        b       start
 
        /* 0x04 Undefined Instruction Interrupt vector address */
        b       testfail
 
        /* 0x08 SWI Interrupt vector address */
        b       testfail
 
        /* 0x0c Prefetch abort Interrupt vector address */
        b       testfail
 
        /* 0x10 Data abort Interrupt vector address */
        b       testfail
 
        /* 0x14 Address Exception Interrupt vector */
        b       service_addr_ex
 
        /* 0x18 IRQ vector address */
        b       testfail
 
        /* 0x1c FIRQ vector address */
        b       testfail
 
 
start:
        @ Change to user mode
        teqp    pc, #0x0c000000
 
        @ count interrupts
        mov     r0, #0
        mov     r8, #0
 
        mov     r0, #0x4000000
        sub     r0, r0, #4
        ldr     r3, no_op
        str     r3, [r0], #4
        str     r3, [r0], #4
        str     r3, [r0], #4
 
        mov     r0, #0x4000000
        sub     r0, r0, #4
        mov     r1, pc
        ldr     r13, PCMask
        bic     r1, r1, r13
        orr     r2, r1, r0
 
        @ this jumps to 0x3ffffff
        @ then the core executes a nop at 0x3ffffff
        @ and increments the address to 0x4000000
        @ which triggers an address exception
pos1:   mov     pc, r2
 
        b       testfail
        b       testfail
 
no_op:  nop
        nop
 
 
service_addr_ex:
        @ Check that we're in supervisor mode again
        mov     r5, pc
        and     r5, r5, #3
        cmp     r5, #3
        movne   r10, #10
        bne     testfail
 
        @ Check the address
        ldr     r13, PCMask
        and     r13, r13, lr
        @ The exception occurs on address 0x4000000, so the
        @ interrupt return address is 0x4000008, but the msb
        @ is not recorded by the pc so it becomes just 0x8
        cmp     r13, #0x08
        movne   r10, #20
        bne     testfail
 
        @ Check that the irq and firq masks are shown correctly in the lr
        and     r13, lr, #0x0c000000
        cmp     r13, #0x0c000000
        movne   r10, #30
        bne     testfail
 
        b       testpass
 
@ ------------------------------------------
@ ------------------------------------------
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:              .word ADR_AMBER_TEST_STATUS
Adrpos1:                    .word pos1
PCMask:                     .word 0x03fffffc

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Interrupt Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests Address Exception Interrupt //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`*****************************************************************/`
40
41			`#include "amber_registers.h"`
42
43			`.section .text`
44			`.globl main`
45			`main:`
46			`@ ---------------------`
47			`@ Exception vectors`
48			`@ ---------------------`
49			`/* 0x00 Reset Interrupt vector address */`
50			`b start`
51
52			`/* 0x04 Undefined Instruction Interrupt vector address */`
53			`b testfail`
54
55			`/* 0x08 SWI Interrupt vector address */`
56			`b testfail`
57
58			`/* 0x0c Prefetch abort Interrupt vector address */`
59			`b testfail`
60
61			`/* 0x10 Data abort Interrupt vector address */`
62			`b testfail`
63
64			`/* 0x14 Address Exception Interrupt vector */`
65			`b service_addr_ex`
66
67			`/* 0x18 IRQ vector address */`
68			`b testfail`
69
70			`/* 0x1c FIRQ vector address */`
71			`b testfail`
72
73
74			`start:`
75			`@ Change to user mode`
76			`teqp pc, #0x0c000000`
77
78			`@ count interrupts`
79			`mov r0, #0`
80			`mov r8, #0`
81
82			`mov r0, #0x4000000`
83			`sub r0, r0, #4`
84			`ldr r3, no_op`
85			`str r3, [r0], #4`
86			`str r3, [r0], #4`
87			`str r3, [r0], #4`
88
89			`mov r0, #0x4000000`
90			`sub r0, r0, #4`
91			`mov r1, pc`
92			`ldr r13, PCMask`
93			`bic r1, r1, r13`
94			`orr r2, r1, r0`
95
96			`@ this jumps to 0x3ffffff`
97			`@ then the core executes a nop at 0x3ffffff`
98			`@ and increments the address to 0x4000000`
99			`@ which triggers an address exception`
100			`pos1: mov pc, r2`
101
102			`b testfail`
103			`b testfail`
104
105			`no_op: nop`
106			`nop`
107
108
109			`service_addr_ex:`
110			`@ Check that we're in supervisor mode again`
111			`mov r5, pc`
112			`and r5, r5, #3`
113			`cmp r5, #3`
114			`movne r10, #10`
115			`bne testfail`
116
117			`@ Check the address`
118			`ldr r13, PCMask`
119			`and r13, r13, lr`
120			`@ The exception occurs on address 0x4000000, so the`
121			`@ interrupt return address is 0x4000008, but the msb`
122			`@ is not recorded by the pc so it becomes just 0x8`
123			`cmp r13, #0x08`
124			`movne r10, #20`
125			`bne testfail`
126
127			`@ Check that the irq and firq masks are shown correctly in the lr`
128			`and r13, lr, #0x0c000000`
129			`cmp r13, #0x0c000000`
130			`movne r10, #30`
131			`bne testfail`
132
133			`b testpass`
134
135			`@ ------------------------------------------`
136			`@ ------------------------------------------`
137
138			`testfail:`
139			`ldr r11, AdrTestStatus`
140			`str r10, [r11]`
141			`b testfail`
142
143			`testpass:`
144			`ldr r11, AdrTestStatus`
145			`mov r10, #17`
146			`str r10, [r11]`
147			`b testpass`
148
149
150
151			`/* Write 17 to this address to generate a Test Passed message */`
152			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
153			`Adrpos1: .word pos1`
154			`PCMask: .word 0x03fffffc`

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[/] [amber/] [trunk/] [hw/] [tests/] [addr_ex.S] - Blame information for rev 2