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[/] [amber/] [trunk/] [hw/] [tests/] [barrel_shift.S] - Blame information for rev 36

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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests lsl, ror                                              //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
#include "amber_macros.h"
 
        .section .text
        .globl  main
main:
 
        @ Run through the test 4 times
        @ 1 - cache off
        @ 2 - cache on but empty
        @ 3 - cache on and loaded
        @ 4 - same as 3
        mov     r10, #4
 
 
/* lsl 0 */
1:      mov     r1, #1
        mov     r2, r1, lsl #0
        expect  r2, 1, __LINE__
 
/* lsl 1 */
        mov     r4, #1
        mov     r5, r4, lsl #1
        expect  r5, 2, __LINE__
 
/* lsl 31 */
        mov     r7, #1
        mov     r8, r1, lsl #31
        expect  r8, 0x80000000, __LINE__
 
/* lsr 1 */
        mov     r1, #2
        mov     r2, r1, lsr #1
        expect  r2, 1, __LINE__
 
/* lsr 8 */
        mov     r4, #0xff00
        mov     r5, r4, lsr #8
        expect  r5, 0xff, __LINE__
 
/* ror 8 */
        ldr     r6, Data1
        mov     r7, r6, ror #8
        ldr     r8, Data2
        compare r7, r8, __LINE__
 
 
        @ ---------------------
        @ Sequences of shift operations
        @ ---------------------
 
        @ lsl
        mov     r0, #0
        mov     r1, #1
        mov     r2, #2
        mov     r3, #3
        mov     r4, #4
        mov     r5, #5
 
        mov     r6, r3, lsl #31
        mov     r7, r0, lsl #2
        mov     r8, r1, lsl #11
        mov     r9, r2, lsl #17
 
        expect  r6, 0x80000000, __LINE__
        expect  r7, 0x00000000, __LINE__
        expect  r8, 0x00000800, __LINE__
        expect  r9, 0x00040000, __LINE__
 
        mov     r6, r3, lsl #30
        mov     r7, r1, lsl #2
        mov     r8, r2, lsl #4
        mov     r9, r3, lsl #5
 
        expect  r6, 0xc0000000, __LINE__
        expect  r7, 0x00000004, __LINE__
        expect  r8, 0x00000020, __LINE__
        expect  r9, 0x00000060, __LINE__
 
        @ lsr
        mov     r0, #0x80000000
        mov     r1, #0x7f000000
        mov     r2, #0x80000001
        mov     r3, #0x7fffffff
        mov     r4, #0x7ffffffe
        mov     r5, #0x55000000
        orr     r5, r5, #0x55
 
        mov     r6, r0, lsr #1
        mov     r7, r0, lsr #2
        mov     r8, r1, lsr #24
        mov     r9, r2, lsr #1
 
        expect  r6, 0x40000000, __LINE__
        expect  r7, 0x20000000, __LINE__
        expect  r8, 0x0000007f, __LINE__
        expect  r9, 0x40000000, __LINE__
 
        @ ---------------------
        @ Enable the cache
        @ ---------------------
        mvn     r0,  #0
        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
        mov     r0,  #1
        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
 
        subs    r10, r10, #1
        bne     1b
 
        b       testpass
 
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
Data1:          .word  0x12345678
Data2:          .word  0x78123456
 
/* ========================================================================= */
/* ========================================================================= */
 
 

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests lsl, ror //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`*****************************************************************/`
40
41			`#include "amber_registers.h"`
42	36	csantifort	`#include "amber_macros.h"`
43	2	csantifort
44			`.section .text`
45			`.globl main`
46			`main:`
47
48	36	csantifort	`@ Run through the test 4 times`
49			`@ 1 - cache off`
50			`@ 2 - cache on but empty`
51			`@ 3 - cache on and loaded`
52			`@ 4 - same as 3`
53			`mov r10, #4`
54
55
56	2	csantifort	`/* lsl 0 */`
57	36	csantifort	`1: mov r1, #1`
58	2	csantifort	`mov r2, r1, lsl #0`
59	36	csantifort	`expect r2, 1, __LINE__`
60	2	csantifort
61			`/* lsl 1 */`
62			`mov r4, #1`
63			`mov r5, r4, lsl #1`
64	36	csantifort	`expect r5, 2, __LINE__`
65	2	csantifort
66			`/* lsl 31 */`
67			`mov r7, #1`
68			`mov r8, r1, lsl #31`
69	36	csantifort	`expect r8, 0x80000000, __LINE__`
70	2	csantifort
71			`/* lsr 1 */`
72			`mov r1, #2`
73			`mov r2, r1, lsr #1`
74	36	csantifort	`expect r2, 1, __LINE__`
75	2	csantifort
76			`/* lsr 8 */`
77			`mov r4, #0xff00`
78			`mov r5, r4, lsr #8`
79	36	csantifort	`expect r5, 0xff, __LINE__`
80	2	csantifort
81			`/* ror 8 */`
82			`ldr r6, Data1`
83			`mov r7, r6, ror #8`
84			`ldr r8, Data2`
85	36	csantifort	`compare r7, r8, __LINE__`
86	2	csantifort
87
88	36	csantifort	`@ ---------------------`
89			`@ Sequences of shift operations`
90			`@ ---------------------`
91
92			`@ lsl`
93			`mov r0, #0`
94			`mov r1, #1`
95			`mov r2, #2`
96			`mov r3, #3`
97			`mov r4, #4`
98			`mov r5, #5`
99
100			`mov r6, r3, lsl #31`
101			`mov r7, r0, lsl #2`
102			`mov r8, r1, lsl #11`
103			`mov r9, r2, lsl #17`
104
105			`expect r6, 0x80000000, __LINE__`
106			`expect r7, 0x00000000, __LINE__`
107			`expect r8, 0x00000800, __LINE__`
108			`expect r9, 0x00040000, __LINE__`
109
110			`mov r6, r3, lsl #30`
111			`mov r7, r1, lsl #2`
112			`mov r8, r2, lsl #4`
113			`mov r9, r3, lsl #5`
114
115			`expect r6, 0xc0000000, __LINE__`
116			`expect r7, 0x00000004, __LINE__`
117			`expect r8, 0x00000020, __LINE__`
118			`expect r9, 0x00000060, __LINE__`
119
120			`@ lsr`
121			`mov r0, #0x80000000`
122			`mov r1, #0x7f000000`
123			`mov r2, #0x80000001`
124			`mov r3, #0x7fffffff`
125			`mov r4, #0x7ffffffe`
126			`mov r5, #0x55000000`
127			`orr r5, r5, #0x55`
128
129			`mov r6, r0, lsr #1`
130			`mov r7, r0, lsr #2`
131			`mov r8, r1, lsr #24`
132			`mov r9, r2, lsr #1`
133
134			`expect r6, 0x40000000, __LINE__`
135			`expect r7, 0x20000000, __LINE__`
136			`expect r8, 0x0000007f, __LINE__`
137			`expect r9, 0x40000000, __LINE__`
138
139			`@ ---------------------`
140			`@ Enable the cache`
141			`@ ---------------------`
142			`mvn r0, #0`
143			`mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area`
144			`mov r0, #1`
145			`mcr 15, 0, r0, cr2, cr0, 0 @ cache enable`
146
147			`subs r10, r10, #1`
148			`bne 1b`
149
150	2	csantifort	`b testpass`
151
152
153			`testfail:`
154			`ldr r11, AdrTestStatus`
155			`str r10, [r11]`
156			`b testfail`
157
158			`testpass:`
159			`ldr r11, AdrTestStatus`
160			`mov r10, #17`
161			`str r10, [r11]`
162			`b testpass`
163
164
165			`/* Write 17 to this address to generate a Test Passed message */`
166			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
167			`Data1: .word 0x12345678`
168			`Data2: .word 0x78123456`
169
170			`/* ========================================================================= */`
171			`/* ========================================================================= */`
172
173

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[/] [amber/] [trunk/] [hw/] [tests/] [barrel_shift.S] - Blame information for rev 36