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[/] [amber/] [trunk/] [hw/] [tests/] [cache3.S] - Blame information for rev 48

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1 2 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Cache Test                                     //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests that the cache can write to and read back multiple    //
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//  times from 2k words in sequence in memory - the size of     //
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//  the cache.                                                  //
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//                                                              //
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//  256 lines x 4 words x 1 way = 1024 words                    //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        @ ---------------------
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        @ Enable the cache
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        @ ---------------------
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        mov     r0,  #0xffffffff
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        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
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        mov     r0,  #1
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        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
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        nop
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        nop
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        @ ---------------------
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        @ Write to 2k locations
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        @ ---------------------
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        ldr     r2, AdrTestBase
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        mov     r3, #0
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write_loop:
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        str     r3, [r2], #4
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        add     r3, r3, #1
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        cmp     r3, #1024
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        bne     write_loop
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        @ ---------------------
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        @ Read back - caches the reads
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        @ ---------------------
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        ldr     r2, AdrTestBase
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        mov     r3, #0
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        mov     r0, #0
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read1_loop:
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        ldr     r1, [r2], #4
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        add     r0, r0, r1
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        add     r3, r3, #1
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        cmp     r3, #1024
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        bne     read1_loop
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        ldr     r4, MagicNumber1024
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        cmp     r0, r4
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        movne   r10, #10
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        bne     testfail
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        @ ---------------------
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        @ Read back a second time and check the values
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        @ These reads will all be from the cache
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        @ ---------------------
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        ldr     r2, AdrTestBase
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        mov     r3, #0
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        mov     r0, #0
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read2_loop:
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        ldr     r1, [r2], #4
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        add     r0, r0, r1
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        add     r3, r3, #1
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        cmp     r3, #1024
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        bne     read2_loop
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        ldr     r4, MagicNumber1024
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        cmp     r0, r4
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        movne   r10, #10
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        bne     testfail
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        b       testpass
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@ ------------------------------------------
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@ ------------------------------------------
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:              .word ADR_AMBER_TEST_STATUS
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AdrTestBase  :              .word 0x20000
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/* sum of numbers 0 to 2047 inclusive */
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MagicNumber1024  :          .word  523776
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MagicNumber2048  :          .word 2096128
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/* ========================================================================= */
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/* ========================================================================= */
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