OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] [cache3.S] - Blame information for rev 54

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 csantifort
/*****************************************************************
2
//                                                              //
3
//  Amber 2 Core Cache Test                                     //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Tests that the cache can write to and read back multiple    //
10
//  times from 2k words in sequence in memory - the size of     //
11
//  the cache.                                                  //
12
//                                                              //
13
//  256 lines x 4 words x 1 way = 1024 words                    //
14
//                                                              //
15
//  Author(s):                                                  //
16
//      - Conor Santifort, csantifort.amber@gmail.com           //
17
//                                                              //
18
//////////////////////////////////////////////////////////////////
19
//                                                              //
20
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
21
//                                                              //
22
// This source file may be used and distributed without         //
23
// restriction provided that this copyright statement is not    //
24
// removed from the file and that any derivative work contains  //
25
// the original copyright notice and the associated disclaimer. //
26
//                                                              //
27
// This source file is free software; you can redistribute it   //
28
// and/or modify it under the terms of the GNU Lesser General   //
29
// Public License as published by the Free Software Foundation; //
30
// either version 2.1 of the License, or (at your option) any   //
31
// later version.                                               //
32
//                                                              //
33
// This source is distributed in the hope that it will be       //
34
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
35
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
36
// PURPOSE.  See the GNU Lesser General Public License for more //
37
// details.                                                     //
38
//                                                              //
39
// You should have received a copy of the GNU Lesser General    //
40
// Public License along with this source; if not, download it   //
41
// from http://www.opencores.org/lgpl.shtml                     //
42
//                                                              //
43
*****************************************************************/
44
 
45
#include "amber_registers.h"
46
 
47
        .section .text
48
        .globl  main
49
main:
50
        @ ---------------------
51
        @ Enable the cache
52
        @ ---------------------
53
        mov     r0,  #0xffffffff
54 15 csantifort
        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
55 2 csantifort
        mov     r0,  #1
56 15 csantifort
        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
57 2 csantifort
        nop
58
        nop
59
 
60
        @ ---------------------
61
        @ Write to 2k locations
62
        @ ---------------------
63
        ldr     r2, AdrTestBase
64
        mov     r3, #0
65
 
66
write_loop:
67
        str     r3, [r2], #4
68
        add     r3, r3, #1
69
        cmp     r3, #1024
70
        bne     write_loop
71
 
72
        @ ---------------------
73
        @ Read back - caches the reads
74
        @ ---------------------
75
        ldr     r2, AdrTestBase
76
        mov     r3, #0
77
        mov     r0, #0
78
 
79
read1_loop:
80
        ldr     r1, [r2], #4
81
        add     r0, r0, r1
82
        add     r3, r3, #1
83
        cmp     r3, #1024
84
        bne     read1_loop
85
 
86
        ldr     r4, MagicNumber1024
87
        cmp     r0, r4
88
        movne   r10, #10
89
        bne     testfail
90
 
91
        @ ---------------------
92
        @ Read back a second time and check the values
93
        @ These reads will all be from the cache
94
        @ ---------------------
95
        ldr     r2, AdrTestBase
96
        mov     r3, #0
97
        mov     r0, #0
98
 
99
read2_loop:
100
        ldr     r1, [r2], #4
101
        add     r0, r0, r1
102
        add     r3, r3, #1
103
        cmp     r3, #1024
104
        bne     read2_loop
105
 
106
        ldr     r4, MagicNumber1024
107
        cmp     r0, r4
108
        movne   r10, #10
109
        bne     testfail
110
 
111
 
112
        b       testpass
113
@ ------------------------------------------
114
@ ------------------------------------------
115
 
116
testfail:
117
        ldr     r11, AdrTestStatus
118
        str     r10, [r11]
119
        b       testfail
120
 
121
testpass:
122
        ldr     r11, AdrTestStatus
123
        mov     r10, #17
124
        str     r10, [r11]
125
        b       testpass
126
 
127
 
128
/* Write 17 to this address to generate a Test Passed message */
129
AdrTestStatus:              .word ADR_AMBER_TEST_STATUS
130
AdrTestBase  :              .word 0x20000
131
 
132
/* sum of numbers 0 to 2047 inclusive */
133
MagicNumber1024  :          .word  523776
134
MagicNumber2048  :          .word 2096128
135
 
136
/* ========================================================================= */
137
/* ========================================================================= */
138
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.