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[/] [amber/] [trunk/] [hw/] [tests/] [cache_flush.S] - Blame information for rev 48

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1 2 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Instruction Test                               //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests the cache flush function. Does a flush in the middle  //
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//  of a sequence of data reads. Checks that all the data       //
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//  reads are correct.                                          //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        @ ---------------------
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        @ Enable the cache
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        @ ---------------------
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        mov     r0,  #0x00000001
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        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
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        mov     r0,  #1
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        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
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        nop
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        nop
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        @ Write to a block of memory that straddles
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        @ across a cache region boundary so that
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        @ the first 16 bytes are cacheable and
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        @ the second 16 are not
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        ldr     r0, AdrTestBase
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        mov     r2, #0x20
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1:      subs    r2, r2, #1
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        str     r2, [r0], #4
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        bne     1b
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        @ loop a few times so that
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        @ the instructions will be caches on the second and
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        @ subsequent passes
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        mov     r7, #7
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        @ Read back the same block
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loop:   ldr     r3, AdrTestBase
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        mov     r5, #0x20
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        mov     r6, #0
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2:      ldr     r4, [r3], #4
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        add     r6, r6, r4
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        @ Flush the cache when the r7 loop count value is even
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        @ a write of any value to cp15, reg 1 will trigger a flush
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        ands    r8, r7, #1
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        cmpeq   r5, #21
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        cmpne   r5, #0x100
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        mcreq   15, 0, r0, cr1, cr0, 0   @ cache enable
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        subs    r5, r5, #1
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        bne     2b
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        @ Check that the sum of the data reads is correct
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        cmp     r6, #0x1f0
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        movne   r10, #10
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        bne     testfail
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        subs    r7, r7, #1
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        bne     loop
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        b       testpass
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@ ------------------------------------------
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@ ------------------------------------------
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:              .word ADR_AMBER_TEST_STATUS
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AdrTestBase  :              .word 0x001fffc0
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/* sum of numbers 0 to 2047 inclusive */
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MagicNumber1024  :          .word  523776
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MagicNumber2048  :          .word 2096128
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/* ========================================================================= */
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/* ========================================================================= */
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