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[/] [amber/] [trunk/] [hw/] [tests/] [cache_swap.S] - Blame information for rev 54

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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Fills up the cache and then does a swap access to data in   //
//  the cache. That data should be invalidated. Check by        //
//  reading it again.                                           //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
        @ ---------------------
        @ Enable the cache
        @ ---------------------
        mov     r0,  #0xffffffff
        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
        mov     r0,  #1
        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
        nop
        nop
 
 
        @ ---------------------
        @ Write to 2k locations
        @ ---------------------
        ldr     r2, AdrTestBase
        mov     r3, #0
 
 
write_loop:
        str     r3, [r2], #4
        add     r3, r3, #1
        cmp     r3, #1024
        bne     write_loop
 
        @ ---------------------
        @ Read back - Loads the cache will all the read data
        @ ---------------------
        ldr     r2, AdrTestBase
        mov     r3, #0
        mov     r0, #0
 
read1_loop:
        ldr     r1, [r2], #4
        add     r0, r0, r1
        add     r3, r3, #1
        cmp     r3, #1024
        bne     read1_loop
 
        ldr     r4, MagicNumber1024
        cmp     r0, r4
        movne   r10, #10
        bne     testfail
 
        @ ---------------------
        @ swp     r2, r2, [r0]
        @ ---------------------
        ldr     r0, AdrTestBase
        mov     r2, #17
        swp     r2, r2, [r0]
 
        @ check the value read in
        mov     r3, #0
        cmp     r3, r2
        movne   r10, #20
        bne     testfail
 
        @ check the value written out
        ldr     r4, [r0]
        cmp     r4, #17
        movne   r10, #30
        bne     testfail
 
        b       testpass
@ ------------------------------------------
@ ------------------------------------------
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:              .word ADR_AMBER_TEST_STATUS
AdrTestBase  :              .word 0x20000
 
/* sum of numbers 0 to 2047 inclusive */
MagicNumber1024  :          .word  523776
MagicNumber2048  :          .word 2096128
 
/* ========================================================================= */
/* ========================================================================= */
 

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Fills up the cache and then does a swap access to data in //`
10			`// the cache. That data should be invalidated. Check by //`
11			`// reading it again. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`*****************************************************************/`
42
43			`#include "amber_registers.h"`
44
45			`.section .text`
46			`.globl main`
47			`main:`
48			`@ ---------------------`
49			`@ Enable the cache`
50			`@ ---------------------`
51			`mov r0, #0xffffffff`
52	15	csantifort	`mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area`
53	2	csantifort	`mov r0, #1`
54	15	csantifort	`mcr 15, 0, r0, cr2, cr0, 0 @ cache enable`
55	2	csantifort	`nop`
56			`nop`
57
58
59			`@ ---------------------`
60			`@ Write to 2k locations`
61			`@ ---------------------`
62			`ldr r2, AdrTestBase`
63			`mov r3, #0`
64
65
66			`write_loop:`
67			`str r3, [r2], #4`
68			`add r3, r3, #1`
69			`cmp r3, #1024`
70			`bne write_loop`
71
72			`@ ---------------------`
73			`@ Read back - Loads the cache will all the read data`
74			`@ ---------------------`
75			`ldr r2, AdrTestBase`
76			`mov r3, #0`
77			`mov r0, #0`
78
79			`read1_loop:`
80			`ldr r1, [r2], #4`
81			`add r0, r0, r1`
82			`add r3, r3, #1`
83			`cmp r3, #1024`
84			`bne read1_loop`
85
86			`ldr r4, MagicNumber1024`
87			`cmp r0, r4`
88			`movne r10, #10`
89			`bne testfail`
90
91			`@ ---------------------`
92			`@ swp r2, r2, [r0]`
93			`@ ---------------------`
94			`ldr r0, AdrTestBase`
95			`mov r2, #17`
96			`swp r2, r2, [r0]`
97
98			`@ check the value read in`
99			`mov r3, #0`
100			`cmp r3, r2`
101			`movne r10, #20`
102			`bne testfail`
103
104			`@ check the value written out`
105			`ldr r4, [r0]`
106			`cmp r4, #17`
107			`movne r10, #30`
108			`bne testfail`
109
110			`b testpass`
111			`@ ------------------------------------------`
112			`@ ------------------------------------------`
113
114			`testfail:`
115			`ldr r11, AdrTestStatus`
116			`str r10, [r11]`
117			`b testfail`
118
119			`testpass:`
120			`ldr r11, AdrTestStatus`
121			`mov r10, #17`
122			`str r10, [r11]`
123			`b testpass`
124
125
126
127			`/* Write 17 to this address to generate a Test Passed message */`
128			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
129			`AdrTestBase : .word 0x20000`
130
131			`/* sum of numbers 0 to 2047 inclusive */`
132			`MagicNumber1024 : .word 523776`
133			`MagicNumber2048 : .word 2096128`
134
135			`/* ========================================================================= */`
136			`/* ========================================================================= */`
137

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[/] [amber/] [trunk/] [hw/] [tests/] [cache_swap.S] - Blame information for rev 54