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[/] [amber/] [trunk/] [hw/] [tests/] [cache_swap_bug.S] - Blame information for rev 54

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/*****************************************************************
//                                                              //
//  Amber 2 Core Cache Test                                     //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests the interaction between a swap instruction            //
//  and the cache.                                              //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
/*
Bug is caused by very subtle timing interactions in the Cache
 
It does not detect a hit, which it should, on the read phase of the swap
operation. It doesnt detect the hit because it is still completing
a fill started by the memory request to load an instructuion
at swap instruction + 8.
This only occurs when the swap target address is in the cache
but the cache instruction address is not, and the instruction
address the third of a group of 4 instruction words.
 
Test copies sequence to another bit of memory and runs it.
Repeats this a few times moving the sequence to slightly
different memory locations each time
*/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
 
        @ ------------------------------------------
        @ Copy code
        @ ------------------------------------------
        @ Copy code sequence to another area in memory
        mov     r13, #4
 
big_loop:
        ldr     r9,  Loc1
        add     r9,  r9, r13
        mov     r11, r9
 
        ldr     r8,  Adrseq
        ldr     r10, Adrseqend
 
copy:
        ldmia   r8!,  {r0-r7}
        stmia   r11!, {r0-r7}
 
        cmp     r8, r10
        blt     copy
 
 
        @ ------------------------------------------
        @ Enable and clear cache
        @ ------------------------------------------
        @ Enable the cache
        mov     r0,  #0xffffffff
        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
        mov     r0,  #1
        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
        nop
        nop
 
        @ flush the cache
        mcr     15, 0, r0, cr1,  cr0,  0
        nop
        nop
 
 
        @ jump to special sequence
        @ want to return to the instruction immediately after mov pc, r9
        mov     lr, pc
        mov     pc, r9
return:
        ldr     r3, [r5]
 
        cmp     r3, #0
        movne   r10, #10
        bne     testfail
 
        cmp     r13, #40
        beq     testpass
        add     r13, r13, #4
        mov     r0, r13
        b       big_loop
 
        @ ------------------------------------------
        @ ------------------------------------------
        @ puts swap address into cache
        @ move 0x7ff32c0 into r5
seq:    mov     r5,     #0x000000c0
        orr     r5, r5, #0x00003200
        orr     r5, r5, #0x00ff0000
        orr     r5, r5, #0x07000000
        ldr     r8, [r5]
        mov     ip, #0
        mov     r2, #1
        str     r2, [r5]
        nop
        nop
        nop
        nop
 
        @ ------------------------------------------
        @ busybox code
        @ ------------------------------------------
        str     r2, [r5, #4]
        nop
        nop
        nop
        nop
        str     ip, [r5, #4]
        nop
        nop
        nop
        nop
        nop
        nop
        str     ip, [r5, #8]
        swp     r3, ip, [r5]
        nop
        nop
        nop
        nop
        ldr     r3, [r5, #8]
        nop
        nop
        nop
        nop
        mov     pc, lr
        nop
        nop
        nop
seqend: nop
 
        @ ------------------------------------------
        @ ------------------------------------------
 
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
 
Loc1:           .word  0x200
Adrseq:         .word  seq
Adrseqend:      .word  seqend
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
 
/* ========================================================================= */
/* ========================================================================= */
 
 

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Cache Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests the interaction between a swap instruction //`
10			`// and the cache. //`
11			`// //`
12			`// Author(s): //`
13			`// - Conor Santifort, csantifort.amber@gmail.com //`
14			`// //`
15			`//////////////////////////////////////////////////////////////////`
16			`// //`
17			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
18			`// //`
19			`// This source file may be used and distributed without //`
20			`// restriction provided that this copyright statement is not //`
21			`// removed from the file and that any derivative work contains //`
22			`// the original copyright notice and the associated disclaimer. //`
23			`// //`
24			`// This source file is free software; you can redistribute it //`
25			`// and/or modify it under the terms of the GNU Lesser General //`
26			`// Public License as published by the Free Software Foundation; //`
27			`// either version 2.1 of the License, or (at your option) any //`
28			`// later version. //`
29			`// //`
30			`// This source is distributed in the hope that it will be //`
31			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
32			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
33			`// PURPOSE. See the GNU Lesser General Public License for more //`
34			`// details. //`
35			`// //`
36			`// You should have received a copy of the GNU Lesser General //`
37			`// Public License along with this source; if not, download it //`
38			`// from http://www.opencores.org/lgpl.shtml //`
39			`// //`
40			`*****************************************************************/`
41
42			`/*`
43			`Bug is caused by very subtle timing interactions in the Cache`
44
45			`It does not detect a hit, which it should, on the read phase of the swap`
46			`operation. It doesnt detect the hit because it is still completing`
47			`a fill started by the memory request to load an instructuion`
48			`at swap instruction + 8.`
49			`This only occurs when the swap target address is in the cache`
50			`but the cache instruction address is not, and the instruction`
51			`address the third of a group of 4 instruction words.`
52
53			`Test copies sequence to another bit of memory and runs it.`
54			`Repeats this a few times moving the sequence to slightly`
55			`different memory locations each time`
56			`*/`
57
58			`#include "amber_registers.h"`
59
60			`.section .text`
61			`.globl main`
62			`main:`
63
64			`@ ------------------------------------------`
65			`@ Copy code`
66			`@ ------------------------------------------`
67			`@ Copy code sequence to another area in memory`
68			`mov r13, #4`
69
70			`big_loop:`
71			`ldr r9, Loc1`
72			`add r9, r9, r13`
73			`mov r11, r9`
74
75			`ldr r8, Adrseq`
76			`ldr r10, Adrseqend`
77
78			`copy:`
79			`ldmia r8!, {r0-r7}`
80			`stmia r11!, {r0-r7}`
81
82			`cmp r8, r10`
83			`blt copy`
84
85
86			`@ ------------------------------------------`
87			`@ Enable and clear cache`
88			`@ ------------------------------------------`
89			`@ Enable the cache`
90			`mov r0, #0xffffffff`
91	15	csantifort	`mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area`
92	2	csantifort	`mov r0, #1`
93	15	csantifort	`mcr 15, 0, r0, cr2, cr0, 0 @ cache enable`
94	2	csantifort	`nop`
95			`nop`
96
97			`@ flush the cache`
98	15	csantifort	`mcr 15, 0, r0, cr1, cr0, 0`
99	2	csantifort	`nop`
100			`nop`
101
102
103			`@ jump to special sequence`
104			`@ want to return to the instruction immediately after mov pc, r9`
105			`mov lr, pc`
106			`mov pc, r9`
107			`return:`
108			`ldr r3, [r5]`
109
110			`cmp r3, #0`
111			`movne r10, #10`
112			`bne testfail`
113
114			`cmp r13, #40`
115			`beq testpass`
116			`add r13, r13, #4`
117			`mov r0, r13`
118			`b big_loop`
119
120			`@ ------------------------------------------`
121			`@ ------------------------------------------`
122			`@ puts swap address into cache`
123			`@ move 0x7ff32c0 into r5`
124			`seq: mov r5, #0x000000c0`
125			`orr r5, r5, #0x00003200`
126			`orr r5, r5, #0x00ff0000`
127			`orr r5, r5, #0x07000000`
128			`ldr r8, [r5]`
129			`mov ip, #0`
130			`mov r2, #1`
131			`str r2, [r5]`
132			`nop`
133			`nop`
134			`nop`
135			`nop`
136
137			`@ ------------------------------------------`
138			`@ busybox code`
139			`@ ------------------------------------------`
140			`str r2, [r5, #4]`
141			`nop`
142			`nop`
143			`nop`
144			`nop`
145			`str ip, [r5, #4]`
146			`nop`
147			`nop`
148			`nop`
149			`nop`
150			`nop`
151			`nop`
152			`str ip, [r5, #8]`
153			`swp r3, ip, [r5]`
154			`nop`
155			`nop`
156			`nop`
157			`nop`
158			`ldr r3, [r5, #8]`
159			`nop`
160			`nop`
161			`nop`
162			`nop`
163			`mov pc, lr`
164			`nop`
165			`nop`
166			`nop`
167			`seqend: nop`
168
169			`@ ------------------------------------------`
170			`@ ------------------------------------------`
171
172
173			`testfail:`
174			`ldr r11, AdrTestStatus`
175			`str r10, [r11]`
176			`b testfail`
177
178			`testpass:`
179			`ldr r11, AdrTestStatus`
180			`mov r10, #17`
181			`str r10, [r11]`
182			`b testpass`
183
184
185
186			`Loc1: .word 0x200`
187			`Adrseq: .word seq`
188			`Adrseqend: .word seqend`
189
190			`/* Write 17 to this address to generate a Test Passed message */`
191			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
192
193			`/* ========================================================================= */`
194			`/* ========================================================================= */`
195
196

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[/] [amber/] [trunk/] [hw/] [tests/] [cache_swap_bug.S] - Blame information for rev 54