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csantifort |
/*****************************************************************
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// //
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// Amber 2 Core Instruction Test //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Tests teq, tst, cmp and cmn with the p flag set //
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// Starts in supervisor mode, changes to Interrupt mode, //
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// then Fast Interrupt mode, then supervisor mode again //
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// and finally User mode //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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*****************************************************************/
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#include "amber_registers.h"
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.section .text
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.globl main
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main:
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@ ------------------------------------------------------------
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@ Change to Interrupt mode using tstp
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@ tstp does an AND
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mov r4, #0xfffffffe
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@ When the pc is in the rn position, it includes the status bits
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tstp r4, pc
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@ Check that we're now in Interrupt mode
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mov r5, pc
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@ just want the mode bits
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and r5, r5, #0x3
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cmp r5, #2
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movne r10, #50
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bne testfail
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@ ------------------------------------------------------------
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@ Change to Fast Interrupt mode using cmpp
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@ cmpp does a subtract
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mov r6, pc
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cmpp r6, #1
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mov r7, pc
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and r8, r7, #3
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cmp r8, #1
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movne r10, #60
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bne testfail
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@ ------------------------------------------------------------
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@ Change back to Supervisor mode using cmnp
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@ cmnp does an add
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ldr r1, Status1
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cmnp pc, #0xf0000003
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nop
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mov r9, pc
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ldr r0, PCMask
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bic r13, r9, r0
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cmp r13, r1
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movne r10, #70
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bne testfail
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@ ------------------------------------------------------------
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@ Clear all the status bits and change to user mode
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@ teq does an XOR
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teqp pc, #0
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b 1f
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b testfail
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b testfail
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@ Check that all the status bits are now zero
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1: ldr r0, PCMask
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mov r1, pc
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bics r1, r1, r0
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movne r10, #10
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bne testfail
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@ ------------------------------------------------------------
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@ Now in user mode, so can't change back to supervisor mode
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@ But can set the condition flags
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teqp pc, #0xf0000003
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mov r2, #0
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orr r1, r2, pc
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bic r1, r1, r0
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cmp r1, #0xf0000000
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movne r10, #20
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bne testfail
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b testpass
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testfail:
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ldr r11, AdrTestStatus
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str r10, [r11]
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b testfail
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testpass:
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ldr r11, AdrTestStatus
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mov r10, #17
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str r10, [r11]
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b testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus: .word ADR_AMBER_TEST_STATUS
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PCMask: .word 0x03fffffc
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Status1: .word 0xf0000003
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/* ========================================================================= */
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/* ========================================================================= */
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