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[/] [amber/] [trunk/] [hw/] [tests/] [change_sbits.S] - Blame information for rev 45

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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests movs where the destination register is r15, the pc    //
//  Depending on the processor mode and whether the s bit is    //
//  set or not, some or none of the status bits will change.    //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
        @ ------------------------------------------------------------------------
        @ In supervisor mode, change to user mode
        ldr     r0, UserMode
        @ set the condition flags
        orr     r0, r0, #0xf0000000
        @ set one of the interrupt masks
        orr     r0, r0, #0x04000000
 
        ldr     r1, =1f
        ldr     r2, PCMask
        and     r2, r1, r2
        orr     r3, r2, r0
        movs    pc, r3
 
        @ Check that the jump works correctly
        b       testfail
        b       testfail
1:      b       2f
        b       testfail
        b       testfail
 
        @ Now check that the status bits are changed correctly
2:      mov     r8, pc
        ldr     r9, PCMask
        bic     r9, r8, r9
        ldr     r12, ExpectedBits1
        cmp     r9, r12
        movne   r10, #20
        bne     testfail
 
        @ ------------------------------------------------------------------------
        @ Test that in user mode, only the condition status bit
        @ and the pc can be changed
        @ In User mode, change to Supervisor mode (this isn't allowed and will fail)
        ldr     r0, SupervisorMode
        @ set the condition flags
        orr     r0, r0, #0x30000000
        @ set one of the interrupt masks
        orr     r0, r0, #0x08000000
 
        ldr     r1, =3f
        ldr     r2, PCMask
        and     r2, r1, r2
        orr     r3, r2, r0
        movs    pc, r3
 
        @ Check that the jump works correctly
        b       testfail
        b       testfail
3:      b       4f
        b       testfail
        b       testfail
 
        @ Now check that the status bits are changed correctly
4:      mov     r8, pc
        ldr     r9, PCMask
        bic     r9, r8, r9
        ldr     r12, ExpectedBits2
        cmp     r9, r12
        movne   r10, #30
        bne     testfail
 
        @ ------------------------------------------------------------------------
        @ Test that in user mode, only the pc changes when the s bit is not set
        mov     r12, pc     @ remeber the current pc status bits
        ldr     r9, PCMask
        bic     r12, r12, r9
 
        ldr     r0, UserMode
        @ set the condition flags
        orr     r0, r0, #0xc0000000
 
        ldr     r1, =5f
        ldr     r2, PCMask
        and     r2, r1, r2
        orr     r3, r2, r0
        mov     pc, r3
 
        @ Check that the jump works correctly
        b       testfail
        b       testfail
5:      b       6f
        b       testfail
        b       testfail
 
        @ Now check that the status bits are not changed
6:      mov     r8, pc
        ldr     r9, PCMask
        bic     r9, r8, r9
        cmp     r9, r12
        movne   r10, #40
        bne     testfail
 
        b       testpass
 
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
 
/* Switch to user mode */
UserMode:       .word  0x00000000
SupervisorMode: .word  0x00000003
PCMask:         .word  0x03fffffc
ExpectedBits1:  .word  0xf4000000
ExpectedBits2:  .word  0x34000000
ExpectedBits3:  .word  0x34000000
 
/* ========================================================================= */
/* ========================================================================= */
 
 

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests movs where the destination register is r15, the pc //`
10			`// Depending on the processor mode and whether the s bit is //`
11			`// set or not, some or none of the status bits will change. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`*****************************************************************/`
42
43			`#include "amber_registers.h"`
44
45			`.section .text`
46			`.globl main`
47			`main:`
48			`@ ------------------------------------------------------------------------`
49			`@ In supervisor mode, change to user mode`
50			`ldr r0, UserMode`
51			`@ set the condition flags`
52			`orr r0, r0, #0xf0000000`
53			`@ set one of the interrupt masks`
54			`orr r0, r0, #0x04000000`
55
56			`ldr r1, =1f`
57			`ldr r2, PCMask`
58			`and r2, r1, r2`
59			`orr r3, r2, r0`
60			`movs pc, r3`
61
62			`@ Check that the jump works correctly`
63			`b testfail`
64			`b testfail`
65			`1: b 2f`
66			`b testfail`
67			`b testfail`
68
69			`@ Now check that the status bits are changed correctly`
70			`2: mov r8, pc`
71			`ldr r9, PCMask`
72			`bic r9, r8, r9`
73			`ldr r12, ExpectedBits1`
74			`cmp r9, r12`
75			`movne r10, #20`
76			`bne testfail`
77
78			`@ ------------------------------------------------------------------------`
79			`@ Test that in user mode, only the condition status bit`
80			`@ and the pc can be changed`
81			`@ In User mode, change to Supervisor mode (this isn't allowed and will fail)`
82			`ldr r0, SupervisorMode`
83			`@ set the condition flags`
84			`orr r0, r0, #0x30000000`
85			`@ set one of the interrupt masks`
86			`orr r0, r0, #0x08000000`
87
88			`ldr r1, =3f`
89			`ldr r2, PCMask`
90			`and r2, r1, r2`
91			`orr r3, r2, r0`
92			`movs pc, r3`
93
94			`@ Check that the jump works correctly`
95			`b testfail`
96			`b testfail`
97			`3: b 4f`
98			`b testfail`
99			`b testfail`
100
101			`@ Now check that the status bits are changed correctly`
102			`4: mov r8, pc`
103			`ldr r9, PCMask`
104			`bic r9, r8, r9`
105			`ldr r12, ExpectedBits2`
106			`cmp r9, r12`
107			`movne r10, #30`
108			`bne testfail`
109
110			`@ ------------------------------------------------------------------------`
111			`@ Test that in user mode, only the pc changes when the s bit is not set`
112			`mov r12, pc @ remeber the current pc status bits`
113			`ldr r9, PCMask`
114			`bic r12, r12, r9`
115
116			`ldr r0, UserMode`
117			`@ set the condition flags`
118			`orr r0, r0, #0xc0000000`
119
120			`ldr r1, =5f`
121			`ldr r2, PCMask`
122			`and r2, r1, r2`
123			`orr r3, r2, r0`
124			`mov pc, r3`
125
126			`@ Check that the jump works correctly`
127			`b testfail`
128			`b testfail`
129			`5: b 6f`
130			`b testfail`
131			`b testfail`
132
133			`@ Now check that the status bits are not changed`
134			`6: mov r8, pc`
135			`ldr r9, PCMask`
136			`bic r9, r8, r9`
137			`cmp r9, r12`
138			`movne r10, #40`
139			`bne testfail`
140
141			`b testpass`
142
143
144			`testfail:`
145			`ldr r11, AdrTestStatus`
146			`str r10, [r11]`
147			`b testfail`
148
149			`testpass:`
150			`ldr r11, AdrTestStatus`
151			`mov r10, #17`
152			`str r10, [r11]`
153			`b testpass`
154
155
156			`/* Write 17 to this address to generate a Test Passed message */`
157			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
158
159			`/* Switch to user mode */`
160			`UserMode: .word 0x00000000`
161			`SupervisorMode: .word 0x00000003`
162			`PCMask: .word 0x03fffffc`
163			`ExpectedBits1: .word 0xf4000000`
164			`ExpectedBits2: .word 0x34000000`
165			`ExpectedBits3: .word 0x34000000`
166
167			`/* ========================================================================= */`
168			`/* ========================================================================= */`
169
170

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[/] [amber/] [trunk/] [hw/] [tests/] [change_sbits.S] - Blame information for rev 45