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[/] [amber/] [trunk/] [hw/] [tests/] [ddr33.S] - Blame information for rev 20

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/*****************************************************************
//                                                              //
//  Amber 2 Core DDR3 Memory Access                             //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Test back to back write-read accesses to DDR3 memory        //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
#define ARRAY_WORDS 0x40
 
        .section .text
        .globl  main
main:
        ldr     r10, DDRBase
        mov     r5, #40         @ main loop count
 
1:      ldr     r0,  AdrRanNum
        ldmia   r0,{r1-r2}
        orr     r2, r2, r1, lsl #8
        mov     r2, r2, lsl #2
        add     r2, r2, r10
 
        ldr     r3, Data0
        ldr     r6, Data1
        ldr     r8, Data2
 
        @ DDR accesses
        str     r3, [r2]
        ldr     r4, [r2], #4
        str     r6, [r2], #4
        str     r8, [r2], #-4
        ldr     r7, [r2], #4
        ldr     r9, [r2]
 
        cmp     r3, r4
        movne   r10, #10
        bne     testfail
 
        cmp     r6, r7
        movne   r10, #20
        bne     testfail
 
        cmp     r8, r9
        movne   r10, #30
        bne     testfail
 
        subs    r5, r5, #1
        bne     1b
 
        b       testpass
 
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word ADR_AMBER_TEST_STATUS
AdrRanNum:      .word ADR_AMBER_TEST_RANDOM_NUM
DDRBase:        .word 0x20000
Data0:          .word 0xff00cc55
Data1:          .word 0x7711ff17
Data2:          .word 0x12345678

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core DDR3 Memory Access //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Test back to back write-read accesses to DDR3 memory //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`*****************************************************************/`
40
41			`#include "amber_registers.h"`
42			`#define ARRAY_WORDS 0x40`
43
44			`.section .text`
45			`.globl main`
46			`main:`
47			`ldr r10, DDRBase`
48			`mov r5, #40 @ main loop count`
49
50			`1: ldr r0, AdrRanNum`
51			`ldmia r0,{r1-r2}`
52			`orr r2, r2, r1, lsl #8`
53			`mov r2, r2, lsl #2`
54			`add r2, r2, r10`
55
56			`ldr r3, Data0`
57			`ldr r6, Data1`
58			`ldr r8, Data2`
59
60			`@ DDR accesses`
61			`str r3, [r2]`
62			`ldr r4, [r2], #4`
63			`str r6, [r2], #4`
64			`str r8, [r2], #-4`
65			`ldr r7, [r2], #4`
66			`ldr r9, [r2]`
67
68			`cmp r3, r4`
69			`movne r10, #10`
70			`bne testfail`
71
72			`cmp r6, r7`
73			`movne r10, #20`
74			`bne testfail`
75
76			`cmp r8, r9`
77			`movne r10, #30`
78			`bne testfail`
79
80			`subs r5, r5, #1`
81			`bne 1b`
82
83			`b testpass`
84
85
86			`testfail:`
87			`ldr r11, AdrTestStatus`
88			`str r10, [r11]`
89			`b testfail`
90
91			`testpass:`
92			`ldr r11, AdrTestStatus`
93			`mov r10, #17`
94			`str r10, [r11]`
95			`b testpass`
96
97
98			`/* Write 17 to this address to generate a Test Passed message */`
99			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
100			`AdrRanNum: .word ADR_AMBER_TEST_RANDOM_NUM`
101			`DDRBase: .word 0x20000`
102			`Data0: .word 0xff00cc55`
103			`Data1: .word 0x7711ff17`
104			`Data2: .word 0x12345678`

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[/] [amber/] [trunk/] [hw/] [tests/] [ddr33.S] - Blame information for rev 20