| 1 |
2 |
csantifort |
/*****************************************************************
|
| 2 |
|
|
// //
|
| 3 |
|
|
// Amber 2 System Ethernet MAC Test //
|
| 4 |
|
|
// //
|
| 5 |
|
|
// This file is part of the Amber project //
|
| 6 |
|
|
// http://www.opencores.org/project,amber //
|
| 7 |
|
|
// //
|
| 8 |
|
|
// Description //
|
| 9 |
|
|
// Tests wishbone access to registers in the Ethernet MAC //
|
| 10 |
|
|
// module. //
|
| 11 |
|
|
// //
|
| 12 |
|
|
// Author(s): //
|
| 13 |
|
|
// - Conor Santifort, csantifort.amber@gmail.com //
|
| 14 |
|
|
// //
|
| 15 |
|
|
//////////////////////////////////////////////////////////////////
|
| 16 |
|
|
// //
|
| 17 |
|
|
// Copyright (C) 2010 Authors and OPENCORES.ORG //
|
| 18 |
|
|
// //
|
| 19 |
|
|
// This source file may be used and distributed without //
|
| 20 |
|
|
// restriction provided that this copyright statement is not //
|
| 21 |
|
|
// removed from the file and that any derivative work contains //
|
| 22 |
|
|
// the original copyright notice and the associated disclaimer. //
|
| 23 |
|
|
// //
|
| 24 |
|
|
// This source file is free software; you can redistribute it //
|
| 25 |
|
|
// and/or modify it under the terms of the GNU Lesser General //
|
| 26 |
|
|
// Public License as published by the Free Software Foundation; //
|
| 27 |
|
|
// either version 2.1 of the License, or (at your option) any //
|
| 28 |
|
|
// later version. //
|
| 29 |
|
|
// //
|
| 30 |
|
|
// This source is distributed in the hope that it will be //
|
| 31 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
| 32 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
| 33 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
| 34 |
|
|
// details. //
|
| 35 |
|
|
// //
|
| 36 |
|
|
// You should have received a copy of the GNU Lesser General //
|
| 37 |
|
|
// Public License along with this source; if not, download it //
|
| 38 |
|
|
// from http://www.opencores.org/lgpl.shtml //
|
| 39 |
|
|
// //
|
| 40 |
|
|
*****************************************************************/
|
| 41 |
|
|
|
| 42 |
|
|
#include "amber_registers.h"
|
| 43 |
|
|
|
| 44 |
|
|
.section .text
|
| 45 |
|
|
.globl main
|
| 46 |
|
|
main:
|
| 47 |
|
|
|
| 48 |
|
|
@ Test reading of a register in the ethmac module
|
| 49 |
|
|
ldr r0, AdrEthMacModer
|
| 50 |
|
|
ldr r1, [r0]
|
| 51 |
|
|
ldr r2, EthMacModerDefault
|
| 52 |
|
|
cmp r1, r2
|
| 53 |
|
|
movne r10, #10
|
| 54 |
|
|
bne testfail
|
| 55 |
|
|
|
| 56 |
|
|
@ Turn on Duplex Mode, bit 10, and write back new value
|
| 57 |
|
|
orr r1, r1, #0x400
|
| 58 |
|
|
str r1, [r0]
|
| 59 |
|
|
|
| 60 |
|
|
@ Read back again to check the value
|
| 61 |
|
|
ldr r3, [r0]
|
| 62 |
|
|
orr r2, r2, #0x400
|
| 63 |
|
|
cmp r3, r2
|
| 64 |
|
|
movne r10, #20
|
| 65 |
|
|
bne testfail
|
| 66 |
|
|
|
| 67 |
|
|
@ Set clock divider to 10 -> 3.3MHz MDC
|
| 68 |
|
|
ldr r4, AdrEthMacMIIModer
|
| 69 |
|
|
mov r5, #10
|
| 70 |
|
|
str r5, [r4]
|
| 71 |
|
|
|
| 72 |
|
|
@ Set MII address - device [4:0], register [12:8]
|
| 73 |
|
|
ldr r4, AdrEthMacMIIAddress
|
| 74 |
|
|
mov r5, #0x07
|
| 75 |
|
|
orr r5, r5, #0x1600
|
| 76 |
|
|
str r5, [r4]
|
| 77 |
|
|
|
| 78 |
|
|
@ receive (read PHY register) Command
|
| 79 |
|
|
ldr r4, AdrEthMacMIICommand
|
| 80 |
|
|
mov r5, #0x2
|
| 81 |
|
|
str r5, [r4]
|
| 82 |
|
|
|
| 83 |
|
|
@ wait for busy, bit 1, to go low
|
| 84 |
|
|
@ Use r6 as a timeout
|
| 85 |
|
|
ldr r4, AdrEthMacMIIStatus
|
| 86 |
|
|
mov r6, #0
|
| 87 |
|
|
wait_busy:
|
| 88 |
|
|
add r6, r6, #1
|
| 89 |
|
|
cmp r6, #0x400
|
| 90 |
|
|
@ Timeout error
|
| 91 |
|
|
moveq r10, #30
|
| 92 |
|
|
beq testfail
|
| 93 |
|
|
|
| 94 |
|
|
ldr r5, [r4]
|
| 95 |
|
|
ands r5, r5, #2
|
| 96 |
|
|
beq readback
|
| 97 |
|
|
b wait_busy
|
| 98 |
|
|
|
| 99 |
|
|
|
| 100 |
|
|
readback:
|
| 101 |
|
|
ldr r4, AdrEthMacMIIRxData
|
| 102 |
|
|
ldr r5, [r4]
|
| 103 |
|
|
ldr r6, ExpectedMIIReadBack
|
| 104 |
|
|
cmp r5, r6
|
| 105 |
|
|
movne r10, #100
|
| 106 |
|
|
bne testfail
|
| 107 |
|
|
b testpass
|
| 108 |
|
|
|
| 109 |
|
|
|
| 110 |
|
|
testfail:
|
| 111 |
|
|
ldr r11, AdrTestStatus
|
| 112 |
|
|
str r10, [r11]
|
| 113 |
|
|
b testfail
|
| 114 |
|
|
|
| 115 |
|
|
testpass:
|
| 116 |
|
|
ldr r11, AdrTestStatus
|
| 117 |
|
|
mov r10, #17
|
| 118 |
|
|
str r10, [r11]
|
| 119 |
|
|
b testpass
|
| 120 |
|
|
|
| 121 |
|
|
|
| 122 |
|
|
/* Write 17 to this address to generate a Test Passed message */
|
| 123 |
|
|
AdrTestStatus: .word ADR_AMBER_TEST_STATUS
|
| 124 |
|
|
AdrEthMacModer: .word ADR_ETHMAC_MODER
|
| 125 |
|
|
AdrEthMacMIIModer: .word ADR_ETHMAC_MIIMODER
|
| 126 |
|
|
AdrEthMacMIICommand: .word ADR_ETHMAC_MIICOMMAND
|
| 127 |
|
|
AdrEthMacMIIAddress: .word ADR_ETHMAC_MIIADDRESS
|
| 128 |
|
|
AdrEthMacMIITxData: .word ADR_ETHMAC_MIITXDATA
|
| 129 |
|
|
AdrEthMacMIIRxData: .word ADR_ETHMAC_MIIRXDATA
|
| 130 |
|
|
AdrEthMacMIIStatus: .word ADR_ETHMAC_MIISTATUS
|
| 131 |
|
|
|
| 132 |
|
|
EthMacModerDefault: .word 0x0000a000
|
| 133 |
|
|
ExpectedMIIReadBack: .word 0x0000ffff
|
| 134 |
|
|
|
| 135 |
|
|
|
| 136 |
|
|
/* ========================================================================= */
|
| 137 |
|
|
/* ========================================================================= */
|
| 138 |
|
|
|
