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[/] [amber/] [trunk/] [hw/] [tests/] [ethmac_tx.S] - Blame information for rev 67

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/*****************************************************************
//                                                              //
//  Amber 2 System Ethernet MAC Test                            //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests ethernet MAC frame transmit and receive functions     //
//  and Ethmac DMA access to hiboot mem. Ethmac is put in       //
//  loopback mode and a packet is transmitted and received.     //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
        ldr     r0, AdrEthMacMemBase
 
/* Write the Transmit Packet Buffer Descriptor */
        ldr     r1, TxBufferW0
        str     r1, [r0]
        ldr     r1, TxBufferW1
        add     r1, r1, #2      @ shift start by 2 bytes
        str     r1, [r0, #4]
 
/* Write the Receive Packet Buffer Descriptor */
        ldr     r1, RxBufferW0
        str     r1, [r0, #0x200]
        ldr     r1, RxBufferW1
        str     r1, [r0, #0x204]
 
/* Copy a Frame into the transmit buffer */
        ldr     r0, TxBufferW1
        ldr     r1, =TxFrame
        ldr     r2, =EndTxFrame
 
        @ copy 8 words at a time
1:      ldmia   r1!, {r3-r10}
        stmia   r0!, {r3-r10}
 
        cmp     r1, r2
        blt     1b
 
 
/*  Set Mode Register */
        ldr     r0, AdrEthMacModer
        ldr     r1, EthMacModerValue
        str     r1, [r0]
 
 
/* Start transmit */
        ldr     r0, AdrEthMacMemBase
        ldr     r1, TxBufferW0
        orr     r1, r1, #0x8000
        str     r1, [r0]
 
 
/* Check register values */
        ldr     r0, AdrEthMacModer
        ldr     r1, EthMacModerValue
        ldr     r2, [r0]
        cmp     r1, r2
        movne   r10, #200
        bne     testfail
 
        ldr     r0, AdrEthMacMemBase
        ldr     r1, TxBufferW0
        orr     r1, r1, #0x8000
        ldr     r2, [r0]
        cmp     r1, r2
        movne   r10, #220
        bne     testfail
 
 
/* Wait until receive complete - Wait for Empty bit to go low */
2:      ldr     r1, [r0, #0x200]
        ands    r1, r1, #0x8000
        bne     2b
 
/* Wait a bit */
        mov     r0, #80
3:      subs    r0, r0, #1
        bne     3b
 
 
/* Check receive buffer */
        ldr     r0, RxBufferW1
        add     r3, r0, #2
        ldr     r1, =TxFrame
        add     r1, r1, #4
        ldr     r2, =EndTxFrame
        @ end of frame is crc which is different so dont check it
        sub     r2, r2, #4
 
        @ there is a 2-byte shift from tx to rx buffer
        @ so load in the data from the rx buffer in 2 byte chunks
        @ and re-arrange to match the tx buffer
 4:     ldr     r4, [r0, #4]!
        mov     r6, r4, lsl #16
        ldr     r5, [r3], #4
        ldr     r12, LoMask
        and     r5, r5, r12
        orr     r7, r5, r6
 
        ldr     r8, [r1], #4
 
        cmp     r7, r8
        movne   r10, #100
        bne     testfail
 
        cmp     r1, r2
        blt     4b
 
 
        b       testpass
 
 
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:          .word  ADR_AMBER_TEST_STATUS
AdrEthMacModer:         .word  ADR_ETHMAC_MODER
AdrEthMacMIIModer:      .word  ADR_ETHMAC_MIIMODER
AdrEthMacMIICommand:    .word  ADR_ETHMAC_MIICOMMAND
AdrEthMacMIIAddress:    .word  ADR_ETHMAC_MIIADDRESS
AdrEthMacMIITxData:     .word  ADR_ETHMAC_MIITXDATA
AdrEthMacMIIRxData:     .word  ADR_ETHMAC_MIIRXDATA
AdrEthMacMIIStatus:     .word  ADR_ETHMAC_MIISTATUS
AdrEthMacMemBase:       .word  ADR_ETHMAC_BDBASE
EthMacModerDefault:     .word  0x0000a000
ExpectedMIIReadBack:    .word  0x0000ffff
LoMask:                 .word  0x0000ffff
 
/* [31:16] = length in bytes, Bit[15] = ready, Bit [13] = wrap bit */
TxBufferW0:             .word  0x00a02800
/* [31:16] = length in bytes, Bit[15] = empty, Bit [13] = wrap bit */
RxBufferW0:             .word  0x0000a800
 
 
/* Buffer Pointer in Main Memory */
TxBufferW1:             .word  0x00011000
RxBufferW1:             .word  0x00011200
 
 
/*
 Ethmac Mode Register
 [15] = Add pads to short frames
 [13] = CRCEN
 [7]  = loopback
 [5]  = 1 for promiscuous, 0 rx only frames that match mac address
 [1]  = txen
 [0]  = rxen
*/
EthMacModerValue:       .word  0xa0a3
 
TxFrame:
.word  0x0e000000
.word  0xa0583e0c  @ rx  1200: 3e0c 0e00
.word  0x554e5300  @ rx  1204: 5300 a058
.word  0x0008304c
.word  0x90000045
.word  0x00400000
.word  0xd5b61140
.word  0x0501a8c0
.word  0x3201a8c0
.word  0x01080203
.word  0xb6c47c00
.word  0xf67d4fc7
.word  0x00000000
.word  0x02000000
.word  0xa3860100
.word  0x03000000
.word  0x06000000
.word  0x01000000
.word  0x18000000
.word  0x025b8f02
.word  0x02000000
.word  0x00003170
.word  0x00000000
.word  0x00000000
.word  0x00000000
.word  0x00000000
.word  0x00000000
.word  0x24000000
.word  0x01070001
.word  0x00143ed5
.word  0x00000000
.word  0x2c043c7f
.word  0x6c41657c
.word  0x8cc37e87
.word  0x2340a928
.word  0x0026048e
.word  0xec587a0e
.word  0x00000000
.word  0x00080000
.word  0x00080000
.word  0x00000000
EndTxFrame:
.word  0
.word  0
.word  0
.word  0
.word  0
.word  0
.word  0
 
/* ========================================================================= */
/* ========================================================================= */
 

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[/] [amber/] [trunk/] [hw/] [tests/] [ethmac_tx.S] - Blame information for rev 67

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 System Ethernet MAC Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests ethernet MAC frame transmit and receive functions //`
10			`// and Ethmac DMA access to hiboot mem. Ethmac is put in //`
11			`// loopback mode and a packet is transmitted and received. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`*****************************************************************/`
42
43			`#include "amber_registers.h"`
44
45			`.section .text`
46			`.globl main`
47			`main:`
48			`ldr r0, AdrEthMacMemBase`
49
50			`/* Write the Transmit Packet Buffer Descriptor */`
51			`ldr r1, TxBufferW0`
52			`str r1, [r0]`
53			`ldr r1, TxBufferW1`
54			`add r1, r1, #2 @ shift start by 2 bytes`
55			`str r1, [r0, #4]`
56
57			`/* Write the Receive Packet Buffer Descriptor */`
58			`ldr r1, RxBufferW0`
59			`str r1, [r0, #0x200]`
60			`ldr r1, RxBufferW1`
61			`str r1, [r0, #0x204]`
62
63			`/* Copy a Frame into the transmit buffer */`
64			`ldr r0, TxBufferW1`
65			`ldr r1, =TxFrame`
66			`ldr r2, =EndTxFrame`
67
68			`@ copy 8 words at a time`
69			`1: ldmia r1!, {r3-r10}`
70			`stmia r0!, {r3-r10}`
71
72			`cmp r1, r2`
73			`blt 1b`
74
75
76			`/* Set Mode Register */`
77			`ldr r0, AdrEthMacModer`
78			`ldr r1, EthMacModerValue`
79			`str r1, [r0]`
80
81
82			`/* Start transmit */`
83			`ldr r0, AdrEthMacMemBase`
84			`ldr r1, TxBufferW0`
85			`orr r1, r1, #0x8000`
86			`str r1, [r0]`
87
88
89	35	csantifort	`/* Check register values */`
90			`ldr r0, AdrEthMacModer`
91			`ldr r1, EthMacModerValue`
92			`ldr r2, [r0]`
93			`cmp r1, r2`
94			`movne r10, #200`
95			`bne testfail`
96
97			`ldr r0, AdrEthMacMemBase`
98			`ldr r1, TxBufferW0`
99			`orr r1, r1, #0x8000`
100			`ldr r2, [r0]`
101			`cmp r1, r2`
102			`movne r10, #220`
103			`bne testfail`
104
105
106	2	csantifort	`/* Wait until receive complete - Wait for Empty bit to go low */`
107			`2: ldr r1, [r0, #0x200]`
108			`ands r1, r1, #0x8000`
109			`bne 2b`
110
111			`/* Wait a bit */`
112	35	csantifort	`mov r0, #80`
113	2	csantifort	`3: subs r0, r0, #1`
114			`bne 3b`
115
116
117			`/* Check receive buffer */`
118			`ldr r0, RxBufferW1`
119			`add r3, r0, #2`
120			`ldr r1, =TxFrame`
121			`add r1, r1, #4`
122			`ldr r2, =EndTxFrame`
123			`@ end of frame is crc which is different so dont check it`
124			`sub r2, r2, #4`
125
126			`@ there is a 2-byte shift from tx to rx buffer`
127			`@ so load in the data from the rx buffer in 2 byte chunks`
128			`@ and re-arrange to match the tx buffer`
129			`4: ldr r4, [r0, #4]!`
130			`mov r6, r4, lsl #16`
131			`ldr r5, [r3], #4`
132			`ldr r12, LoMask`
133			`and r5, r5, r12`
134			`orr r7, r5, r6`
135
136			`ldr r8, [r1], #4`
137
138			`cmp r7, r8`
139			`movne r10, #100`
140			`bne testfail`
141
142			`cmp r1, r2`
143			`blt 4b`
144
145
146			`b testpass`
147
148
149
150			`testfail:`
151			`ldr r11, AdrTestStatus`
152			`str r10, [r11]`
153			`b testfail`
154
155			`testpass:`
156			`ldr r11, AdrTestStatus`
157			`mov r10, #17`
158			`str r10, [r11]`
159			`b testpass`
160
161
162			`/* Write 17 to this address to generate a Test Passed message */`
163			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
164			`AdrEthMacModer: .word ADR_ETHMAC_MODER`
165			`AdrEthMacMIIModer: .word ADR_ETHMAC_MIIMODER`
166			`AdrEthMacMIICommand: .word ADR_ETHMAC_MIICOMMAND`
167			`AdrEthMacMIIAddress: .word ADR_ETHMAC_MIIADDRESS`
168			`AdrEthMacMIITxData: .word ADR_ETHMAC_MIITXDATA`
169			`AdrEthMacMIIRxData: .word ADR_ETHMAC_MIIRXDATA`
170			`AdrEthMacMIIStatus: .word ADR_ETHMAC_MIISTATUS`
171			`AdrEthMacMemBase: .word ADR_ETHMAC_BDBASE`
172			`EthMacModerDefault: .word 0x0000a000`
173			`ExpectedMIIReadBack: .word 0x0000ffff`
174			`LoMask: .word 0x0000ffff`
175
176			`/* [31:16] = length in bytes, Bit[15] = ready, Bit [13] = wrap bit */`
177			`TxBufferW0: .word 0x00a02800`
178			`/* [31:16] = length in bytes, Bit[15] = empty, Bit [13] = wrap bit */`
179			`RxBufferW0: .word 0x0000a800`
180
181
182	35	csantifort	`/* Buffer Pointer in Main Memory */`
183			`TxBufferW1: .word 0x00011000`
184			`RxBufferW1: .word 0x00011200`
185	2	csantifort
186
187			`/*`
188			`Ethmac Mode Register`
189			`[15] = Add pads to short frames`
190			`[13] = CRCEN`
191			`[7] = loopback`
192			`[5] = 1 for promiscuous, 0 rx only frames that match mac address`
193			`[1] = txen`
194			`[0] = rxen`
195			`*/`
196			`EthMacModerValue: .word 0xa0a3`
197
198			`TxFrame:`
199			`.word 0x0e000000`
200			`.word 0xa0583e0c @ rx 1200: 3e0c 0e00`
201			`.word 0x554e5300 @ rx 1204: 5300 a058`
202			`.word 0x0008304c`
203			`.word 0x90000045`
204			`.word 0x00400000`
205			`.word 0xd5b61140`
206			`.word 0x0501a8c0`
207			`.word 0x3201a8c0`
208			`.word 0x01080203`
209			`.word 0xb6c47c00`
210			`.word 0xf67d4fc7`
211			`.word 0x00000000`
212			`.word 0x02000000`
213			`.word 0xa3860100`
214			`.word 0x03000000`
215			`.word 0x06000000`
216			`.word 0x01000000`
217			`.word 0x18000000`
218			`.word 0x025b8f02`
219			`.word 0x02000000`
220			`.word 0x00003170`
221			`.word 0x00000000`
222			`.word 0x00000000`
223			`.word 0x00000000`
224			`.word 0x00000000`
225			`.word 0x00000000`
226			`.word 0x24000000`
227			`.word 0x01070001`
228			`.word 0x00143ed5`
229			`.word 0x00000000`
230			`.word 0x2c043c7f`
231			`.word 0x6c41657c`
232			`.word 0x8cc37e87`
233			`.word 0x2340a928`
234			`.word 0x0026048e`
235			`.word 0xec587a0e`
236			`.word 0x00000000`
237			`.word 0x00080000`
238			`.word 0x00080000`
239			`.word 0x00000000`
240			`EndTxFrame:`
241			`.word 0`
242			`.word 0`
243			`.word 0`
244			`.word 0`
245			`.word 0`
246			`.word 0`
247			`.word 0`
248
249			`/* ========================================================================= */`
250			`/* ========================================================================= */`
251