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[/] [amber/] [trunk/] [hw/] [tests/] [firq.S] - Blame information for rev 2

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/*****************************************************************
//                                                              //
//  Amber 2 Core Interrupt Test                                 //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests Fast Interrupt                                        //
//  Executes 20 FIRQs randomly while executing a small loop     //
//  of code. Test checks the full set of FIRQ registers (r8 to  //
//  r14) and will only pass if all interrupts are handled       //
//  correctly                                                   //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
 
        @ ---------------------
        @ Interrupt Vector Table
        @ ---------------------
        /* 0x00 Reset Interrupt vector address */
        b       start
 
        /* 0x04 Undefined Instruction Interrupt vector address */
        b       testfail
 
        /* 0x08 SWI Interrupt vector address */
        b       testfail
 
        /* 0x0c Prefetch abort Interrupt vector address */
        b       testfail
 
        /* 0x10 Data abort Interrupt vector address */
        b       testfail
        b       testfail
 
        /* 0x18 IRQ vector address */
        b       testfail
 
        /* 0x1c FIRQ vector address */
        b       service_firq
 
 
start:
        /* Switch to User Mode */
        /* and unset interrupt mask bits */
        mov     r0,   #0x00000000
        teqp    pc, r0
 
        @ Check that we're in user mode now
        mov     r2, pc
        ands    r2, r2, #3
        movne   r10, #10
        bne     testfail
 
 
        @ Set up
        mov     r1, #0
        mov     r3, #20    @ Number of times to run the outer loop of the test
 
        @ set the firq timer to trigger a firq request
mloop:
        ldr     r4, AdrRanNum
        ldr     r5, [r4]
        and     r5, r5, #0x3f
        add     r5, r5, #15
 
        ldr     r6, AdrFIRQTimer
        str     r5, [r6]
 
        @ loop forever
loop:   mov     r8,  #0x17
        mov     r9,  #0x39
        mov     r10, #0x87
        mov     r11, #0x14
        mov     r12, #0x97
        mov     r13, #0x52
 
        mov     r7, #0
        add     r7, r8, r7
        add     r7, r9, r7
        add     r7, r10, r7
        add     r7, r11, r7
        add     r7, r12, r7
        add     r7, r13, r7
 
        @ only jump to check regs after an interrupt has occurred.
        @ The interrupt service routine sets r1 to a 1
        @ and the check_regs sequence sets it back to 0
        cmp     r1,  #1
        beq     check_regs
        b       loop
        nop
 
loop1:  @ This lable needs to be 1 instruction after the end of the
        @ loop. The interrupt lr address is current instruction address + 4
        @ so if the interrupt hits on the b loop, then the FIRQ lr will
        @ be 2 instructions after the end of the loop
 
 
service_firq:
        @ Now in FIRQ mode
        @ Turn off the FIRQ interrupt count down trigger by writing a zero to it
        ldr     r10, AdrFIRQTimer
        mov     r11, #0
        str     r11, [r10]
 
        @ Check that the FIRQ Link Register (r14) got the correct return address
        @ Don't know exactly when the interrupt occurred so check the range loop to loop1
        ldr     r2, Adrloop
        ldr     r13, PCMask
        and     r13, lr, r13
        cmp     r13, r2
        movlt   r10, #100
        blt     testfail
 
        ldr     r2, Adrloop1
        cmp     r13, r2
        movgt   r10, #110
        bgt     testfail
 
        @ save a 1 to r1, this will exit the loop to testpass
        mov     r1, #1
 
        mov     r8,  #0x10
        mov     r9,  #0x20
        mov     r10, #0x30
        mov     r11, #0x40
        mov     r12, #0x50
        mov     r13, #0x60
 
        @ Jump straight back to normal execution, returning to user mode
        subs    pc, r14, #4
 
 
check_regs:
        mov     r1,  #0
 
        ldr     r6, Sum
        cmp     r7, r6
        movne   r10, #15
        bne     testfail
 
        cmp     r8,  #0x17
        movne   r10, #20
        bne     testfail
 
        cmp     r9,  #0x39
        movne   r10, #30
        bne     testfail
 
        cmp     r10, #0x87
        movne   r10, #40
        bne     testfail
 
        cmp     r11, #0x14
        movne   r10, #50
        bne     testfail
 
        cmp     r12, #0x97
        movne   r10, #60
        bne     testfail
 
        cmp     r13, #0x52
        movne   r10, #70
        bne     testfail
 
        cmp     r3, #0
 
        beq     testpass
        sub     r3, r3, #1
        b       mloop
 
@ ------------------------------------------
@ ------------------------------------------
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
@ ------------------------------------------
@ ------------------------------------------
 
AdrTestStatus:  .word ADR_AMBER_TEST_STATUS
AdrRanNum:      .word ADR_AMBER_TEST_RANDOM_NUM
AdrFIRQTimer:   .word ADR_AMBER_TEST_FIRQ_TIMER
Adrloop:        .word loop
Adrloop1:       .word loop1
Sum:            .word 0x1d4
PCMask:         .word 0x03fffffc

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[/] [amber/] [trunk/] [hw/] [tests/] [firq.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Interrupt Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests Fast Interrupt //`
10			`// Executes 20 FIRQs randomly while executing a small loop //`
11			`// of code. Test checks the full set of FIRQ registers (r8 to //`
12			`// r14) and will only pass if all interrupts are handled //`
13			`// correctly //`
14			`// //`
15			`// Author(s): //`
16			`// - Conor Santifort, csantifort.amber@gmail.com //`
17			`// //`
18			`//////////////////////////////////////////////////////////////////`
19			`// //`
20			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
21			`// //`
22			`// This source file may be used and distributed without //`
23			`// restriction provided that this copyright statement is not //`
24			`// removed from the file and that any derivative work contains //`
25			`// the original copyright notice and the associated disclaimer. //`
26			`// //`
27			`// This source file is free software; you can redistribute it //`
28			`// and/or modify it under the terms of the GNU Lesser General //`
29			`// Public License as published by the Free Software Foundation; //`
30			`// either version 2.1 of the License, or (at your option) any //`
31			`// later version. //`
32			`// //`
33			`// This source is distributed in the hope that it will be //`
34			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
35			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
36			`// PURPOSE. See the GNU Lesser General Public License for more //`
37			`// details. //`
38			`// //`
39			`// You should have received a copy of the GNU Lesser General //`
40			`// Public License along with this source; if not, download it //`
41			`// from http://www.opencores.org/lgpl.shtml //`
42			`// //`
43			`*****************************************************************/`
44
45			`#include "amber_registers.h"`
46
47			`.section .text`
48			`.globl main`
49			`main:`
50
51			`@ ---------------------`
52			`@ Interrupt Vector Table`
53			`@ ---------------------`
54			`/* 0x00 Reset Interrupt vector address */`
55			`b start`
56
57			`/* 0x04 Undefined Instruction Interrupt vector address */`
58			`b testfail`
59
60			`/* 0x08 SWI Interrupt vector address */`
61			`b testfail`
62
63			`/* 0x0c Prefetch abort Interrupt vector address */`
64			`b testfail`
65
66			`/* 0x10 Data abort Interrupt vector address */`
67			`b testfail`
68			`b testfail`
69
70			`/* 0x18 IRQ vector address */`
71			`b testfail`
72
73			`/* 0x1c FIRQ vector address */`
74			`b service_firq`
75
76
77			`start:`
78			`/* Switch to User Mode */`
79			`/* and unset interrupt mask bits */`
80			`mov r0, #0x00000000`
81			`teqp pc, r0`
82
83			`@ Check that we're in user mode now`
84			`mov r2, pc`
85			`ands r2, r2, #3`
86			`movne r10, #10`
87			`bne testfail`
88
89
90			`@ Set up`
91			`mov r1, #0`
92			`mov r3, #20 @ Number of times to run the outer loop of the test`
93
94			`@ set the firq timer to trigger a firq request`
95			`mloop:`
96			`ldr r4, AdrRanNum`
97			`ldr r5, [r4]`
98			`and r5, r5, #0x3f`
99			`add r5, r5, #15`
100
101			`ldr r6, AdrFIRQTimer`
102			`str r5, [r6]`
103
104			`@ loop forever`
105			`loop: mov r8, #0x17`
106			`mov r9, #0x39`
107			`mov r10, #0x87`
108			`mov r11, #0x14`
109			`mov r12, #0x97`
110			`mov r13, #0x52`
111
112			`mov r7, #0`
113			`add r7, r8, r7`
114			`add r7, r9, r7`
115			`add r7, r10, r7`
116			`add r7, r11, r7`
117			`add r7, r12, r7`
118			`add r7, r13, r7`
119
120			`@ only jump to check regs after an interrupt has occurred.`
121			`@ The interrupt service routine sets r1 to a 1`
122			`@ and the check_regs sequence sets it back to 0`
123			`cmp r1, #1`
124			`beq check_regs`
125			`b loop`
126			`nop`
127
128			`loop1: @ This lable needs to be 1 instruction after the end of the`
129			`@ loop. The interrupt lr address is current instruction address + 4`
130			`@ so if the interrupt hits on the b loop, then the FIRQ lr will`
131			`@ be 2 instructions after the end of the loop`
132
133
134			`service_firq:`
135			`@ Now in FIRQ mode`
136			`@ Turn off the FIRQ interrupt count down trigger by writing a zero to it`
137			`ldr r10, AdrFIRQTimer`
138			`mov r11, #0`
139			`str r11, [r10]`
140
141			`@ Check that the FIRQ Link Register (r14) got the correct return address`
142			`@ Don't know exactly when the interrupt occurred so check the range loop to loop1`
143			`ldr r2, Adrloop`
144			`ldr r13, PCMask`
145			`and r13, lr, r13`
146			`cmp r13, r2`
147			`movlt r10, #100`
148			`blt testfail`
149
150			`ldr r2, Adrloop1`
151			`cmp r13, r2`
152			`movgt r10, #110`
153			`bgt testfail`
154
155			`@ save a 1 to r1, this will exit the loop to testpass`
156			`mov r1, #1`
157
158			`mov r8, #0x10`
159			`mov r9, #0x20`
160			`mov r10, #0x30`
161			`mov r11, #0x40`
162			`mov r12, #0x50`
163			`mov r13, #0x60`
164
165			`@ Jump straight back to normal execution, returning to user mode`
166			`subs pc, r14, #4`
167
168
169			`check_regs:`
170			`mov r1, #0`
171
172			`ldr r6, Sum`
173			`cmp r7, r6`
174			`movne r10, #15`
175			`bne testfail`
176
177			`cmp r8, #0x17`
178			`movne r10, #20`
179			`bne testfail`
180
181			`cmp r9, #0x39`
182			`movne r10, #30`
183			`bne testfail`
184
185			`cmp r10, #0x87`
186			`movne r10, #40`
187			`bne testfail`
188
189			`cmp r11, #0x14`
190			`movne r10, #50`
191			`bne testfail`
192
193			`cmp r12, #0x97`
194			`movne r10, #60`
195			`bne testfail`
196
197			`cmp r13, #0x52`
198			`movne r10, #70`
199			`bne testfail`
200
201			`cmp r3, #0`
202
203			`beq testpass`
204			`sub r3, r3, #1`
205			`b mloop`
206
207			`@ ------------------------------------------`
208			`@ ------------------------------------------`
209
210			`testfail:`
211			`ldr r11, AdrTestStatus`
212			`str r10, [r11]`
213			`b testfail`
214
215			`testpass:`
216			`ldr r11, AdrTestStatus`
217			`mov r10, #17`
218			`str r10, [r11]`
219			`b testpass`
220
221
222			`@ ------------------------------------------`
223			`@ ------------------------------------------`
224
225			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
226			`AdrRanNum: .word ADR_AMBER_TEST_RANDOM_NUM`
227			`AdrFIRQTimer: .word ADR_AMBER_TEST_FIRQ_TIMER`
228			`Adrloop: .word loop`
229			`Adrloop1: .word loop1`
230			`Sum: .word 0x1d4`
231			`PCMask: .word 0x03fffffc`