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[/] [amber/] [trunk/] [hw/] [tests/] [flow2.S] - Blame information for rev 15

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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests instruction and data flow.                            //
//  Specifically tests that a stream of str instrutions writing //
//  to cached memory works correctly.                           //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
 
        @ Run through the test 4 times
        @ 1 - cache off
        @ 2 - cache on but empty
        @ 3 - cache on and loaded
        @ 4 - same as 3
 
        mov     r10, #40
 
1:      mov     r0, #0x1000
        ldr     r1, Data2
        str     r1, [r0]
 
        ldr     r2, [r0], #1
        ldr     r3, [r0], #1
        ldr     r4, [r0], #1
        ldr     r5, [r0]
 
        ldrb    r6, [r0], #-1
        ldrb    r7, [r0], #-1
        ldrb    r8, [r0], #-1
        ldrb    r9, [r0]
 
        cmp     r2, r1
        addne   r10, r10, #2
        bne     testfail
 
        mov     r1, r1, ror #8
        cmp     r3, r1
        addne   r10, r10, #3
        bne     testfail
 
        mov     r1, r1, ror #8
        cmp     r4, r1
        addne   r10, r10, #4
        bne     testfail
 
        mov     r1, r1, ror #8
        cmp     r5, r1
        addne   r10, r10, #5
        bne     testfail
 
        @ Test conflict detection
        mov     r1, #5
        ldr     r1, Data1
        mov     r2, r1
        cmp     r2, #3
        addne   r10, r10, #6
        bne     testfail
 
        @ Test ldm/stm with conflicts
 
        mov     r13, #0x1000
        orr     r13, r13, #0x08
 
        ldr     r0, =Data1
        ldmia   r0, {r1-r5}
        mov     r6,  r13
        str     r1, [r6], #4
        str     r2, [r6], #4
        str     r3, [r6], #4
        str     r4, [r6], #4
        str     r5, [r6], #4
 
        mov     r6,  r13
        ldr     r7,  [r6], #4
        ldr     r8,  [r6], #4
        ldr     r9,  [r6], #4
        ldr     r14, [r6], #4
        ldr     r11, [r6], #4
 
        cmp     r1, r7
        cmpeq   r2, r8
        cmpeq   r3, r9
        cmpeq   r4, r14
        cmpeq   r5, r11
        addne   r10, r10, #7
        bne     testfail
 
 
        @ Test conflict detection for a stm
        mov     r6,  r13
        mov     r2, #3
        mov     r0, #4
        ldr     r1, Data3
        stm     r6, {r0,r1,r2}
 
        mov     r6,  r13
        ldr     r4, [r6, #4]
        cmp     r1, r4
        addne   r10, r10, #8
        bne     testfail
 
        @ Test conflict detection for add
        ldr     r5, Data1
        add     r5, r5, #1
        cmp     r5, #4
        addne   r10, r10, #9
        bne     testfail
 
        @ Throw in an uncached memory access
        mov     r1, #0x99
        ldr     r0, AdrHiBootBase
        str     r1, [r0]
        ldr     r2, [r0]
        cmp     r2, #0x99
        addne   r10, r10, #100
        bne     testfail
 
        @ ---------------------
        @ Enable the cache
        @ ---------------------
        mvn     r0,  #0
        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
        mov     r0,  #1
        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
 
        subs    r10, r10, #10
        bne     1b
 
        b       testpass
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
AdrHiBootBase:  .word  ADR_HIBOOT_BASE
 
Data1:          .word  0x3
                .word  0x4
                .word  0x5
                .word  0x6
                .word  0x7
Data2:          .word  0x44332211
Data3:          .word  0x12345678
 
/* ========================================================================= */
/* ========================================================================= */
 

Line No.	Rev	Author	Line
1	15	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests instruction and data flow. //`
10			`// Specifically tests that a stream of str instrutions writing //`
11			`// to cached memory works correctly. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`*****************************************************************/`
42
43			`#include "amber_registers.h"`
44
45			`.section .text`
46			`.globl main`
47			`main:`
48
49			`@ Run through the test 4 times`
50			`@ 1 - cache off`
51			`@ 2 - cache on but empty`
52			`@ 3 - cache on and loaded`
53			`@ 4 - same as 3`
54
55			`mov r10, #40`
56
57			`1: mov r0, #0x1000`
58			`ldr r1, Data2`
59			`str r1, [r0]`
60
61			`ldr r2, [r0], #1`
62			`ldr r3, [r0], #1`
63			`ldr r4, [r0], #1`
64			`ldr r5, [r0]`
65
66			`ldrb r6, [r0], #-1`
67			`ldrb r7, [r0], #-1`
68			`ldrb r8, [r0], #-1`
69			`ldrb r9, [r0]`
70
71			`cmp r2, r1`
72			`addne r10, r10, #2`
73			`bne testfail`
74
75			`mov r1, r1, ror #8`
76			`cmp r3, r1`
77			`addne r10, r10, #3`
78			`bne testfail`
79
80			`mov r1, r1, ror #8`
81			`cmp r4, r1`
82			`addne r10, r10, #4`
83			`bne testfail`
84
85			`mov r1, r1, ror #8`
86			`cmp r5, r1`
87			`addne r10, r10, #5`
88			`bne testfail`
89
90			`@ Test conflict detection`
91			`mov r1, #5`
92			`ldr r1, Data1`
93			`mov r2, r1`
94			`cmp r2, #3`
95			`addne r10, r10, #6`
96			`bne testfail`
97
98			`@ Test ldm/stm with conflicts`
99
100			`mov r13, #0x1000`
101			`orr r13, r13, #0x08`
102
103			`ldr r0, =Data1`
104			`ldmia r0, {r1-r5}`
105			`mov r6, r13`
106			`str r1, [r6], #4`
107			`str r2, [r6], #4`
108			`str r3, [r6], #4`
109			`str r4, [r6], #4`
110			`str r5, [r6], #4`
111
112			`mov r6, r13`
113			`ldr r7, [r6], #4`
114			`ldr r8, [r6], #4`
115			`ldr r9, [r6], #4`
116			`ldr r14, [r6], #4`
117			`ldr r11, [r6], #4`
118
119			`cmp r1, r7`
120			`cmpeq r2, r8`
121			`cmpeq r3, r9`
122			`cmpeq r4, r14`
123			`cmpeq r5, r11`
124			`addne r10, r10, #7`
125			`bne testfail`
126
127
128			`@ Test conflict detection for a stm`
129			`mov r6, r13`
130			`mov r2, #3`
131			`mov r0, #4`
132			`ldr r1, Data3`
133			`stm r6, {r0,r1,r2}`
134
135			`mov r6, r13`
136			`ldr r4, [r6, #4]`
137			`cmp r1, r4`
138			`addne r10, r10, #8`
139			`bne testfail`
140
141			`@ Test conflict detection for add`
142			`ldr r5, Data1`
143			`add r5, r5, #1`
144			`cmp r5, #4`
145			`addne r10, r10, #9`
146			`bne testfail`
147
148			`@ Throw in an uncached memory access`
149			`mov r1, #0x99`
150			`ldr r0, AdrHiBootBase`
151			`str r1, [r0]`
152			`ldr r2, [r0]`
153			`cmp r2, #0x99`
154			`addne r10, r10, #100`
155			`bne testfail`
156
157			`@ ---------------------`
158			`@ Enable the cache`
159			`@ ---------------------`
160			`mvn r0, #0`
161			`mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area`
162			`mov r0, #1`
163			`mcr 15, 0, r0, cr2, cr0, 0 @ cache enable`
164
165			`subs r10, r10, #10`
166			`bne 1b`
167
168			`b testpass`
169
170			`testfail:`
171			`ldr r11, AdrTestStatus`
172			`str r10, [r11]`
173			`b testfail`
174
175			`testpass:`
176			`ldr r11, AdrTestStatus`
177			`mov r10, #17`
178			`str r10, [r11]`
179			`b testpass`
180
181
182			`/* Write 17 to this address to generate a Test Passed message */`
183			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
184			`AdrHiBootBase: .word ADR_HIBOOT_BASE`
185
186			`Data1: .word 0x3`
187			`.word 0x4`
188			`.word 0x5`
189			`.word 0x6`
190			`.word 0x7`
191			`Data2: .word 0x44332211`
192			`Data3: .word 0x12345678`
193
194			`/* ========================================================================= */`
195			`/* ========================================================================= */`
196

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[/] [amber/] [trunk/] [hw/] [tests/] [flow2.S] - Blame information for rev 15