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[/] [amber/] [trunk/] [hw/] [tests/] [flow3.S] - Blame information for rev 48

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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests ldm where the pc is loaded which causes a jump.       //
//  At the same time the mode is changed, This is repeated      //
//  with the cache enabled.                                     //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
 
        @ Run through the test 4 times
        @ 1 - cache off
        @ 2 - cache on but empty
        @ 3 - cache on and loaded
        @ 4 - same as 3
 
        mov     r7, #40
 
1:      mov     r0, #0x1000
        ldr     r6, =JumpHere
        bic     r6, r6, #0x3
        orr     r6, r6, #0x1 @ set the mode to jump to
        mov     r2, #17
        mov     r3, #46
        mov     r4, #99
        mov     r5, #123
 
        stm     r0, {r2-r6}
        ldm     r0, {r11-pc}^
 
        b       testfail
        b       testfail
        b       testfail
        b       testfail
        b       testfail
        b       testfail
        b       testfail
        b       testfail
        b       testfail
        b       testfail
 
JumpHere:
        b       2f
        b       testfail
        b       testfail
        b       testfail
 
2:
        @ Check the mode is 0x1
        mov     r0, pc
        and     r0, r0, #0x3
        cmp     r0, #0x1
        movne   r10, #10
        bne     testfail
 
        @ Switch back to supervisor mode
        teqp    pc, #0x3
 
        @ Test that the instructions immediately
        @ following a non-executed ldr pc are executed
        mov     r10, #20
        mov     r0, #5
        cmp     r0, #6
        ldreq   pc, =testfail  @ not executed
        teq     r0, #5
        bne     testfail
        b       3f
        b       testfail
        b       testfail
        b       testfail
3:
 
        @ Test that the instruction after two ldrs, where the second ldr depends on the first,
        @ is executed.
        mov     r0, #5
        cmp     r0, #6
        ldmeqia sp!, {r4,pc}
        ldr     r2, Data1
        ldr     r2, [r2]
        mov     r0, #7
        cmp     r0, #7
        movne   r10, #30
        bne     testfail
 
        cmp     r2, #0xff
        movne   r10, #40
        bne     testfail
 
 
        @ ---------------------
        @ Enable the cache
        @ ---------------------
        mvn     r0,  #0
        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
        mov     r0,  #1
        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
 
        subs    r7, r7, #10
        bne     1b
 
        b       testpass
 
        b       testfail
        b       testfail
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
Data1:          .word  Data2
Data2:          .word  0xff
 
/* ========================================================================= */
/* ========================================================================= */
 

Line No.	Rev	Author	Line
1	15	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests ldm where the pc is loaded which causes a jump. //`
10			`// At the same time the mode is changed, This is repeated //`
11			`// with the cache enabled. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`*****************************************************************/`
42
43			`#include "amber_registers.h"`
44
45			`.section .text`
46			`.globl main`
47			`main:`
48
49			`@ Run through the test 4 times`
50			`@ 1 - cache off`
51			`@ 2 - cache on but empty`
52			`@ 3 - cache on and loaded`
53			`@ 4 - same as 3`
54
55			`mov r7, #40`
56
57			`1: mov r0, #0x1000`
58			`ldr r6, =JumpHere`
59			`bic r6, r6, #0x3`
60			`orr r6, r6, #0x1 @ set the mode to jump to`
61			`mov r2, #17`
62			`mov r3, #46`
63			`mov r4, #99`
64			`mov r5, #123`
65
66			`stm r0, {r2-r6}`
67			`ldm r0, {r11-pc}^`
68
69			`b testfail`
70			`b testfail`
71			`b testfail`
72			`b testfail`
73			`b testfail`
74			`b testfail`
75			`b testfail`
76			`b testfail`
77			`b testfail`
78			`b testfail`
79
80			`JumpHere:`
81			`b 2f`
82			`b testfail`
83			`b testfail`
84			`b testfail`
85
86			`2:`
87			`@ Check the mode is 0x1`
88			`mov r0, pc`
89			`and r0, r0, #0x3`
90			`cmp r0, #0x1`
91			`movne r10, #10`
92			`bne testfail`
93
94			`@ Switch back to supervisor mode`
95			`teqp pc, #0x3`
96
97			`@ Test that the instructions immediately`
98			`@ following a non-executed ldr pc are executed`
99			`mov r10, #20`
100			`mov r0, #5`
101			`cmp r0, #6`
102			`ldreq pc, =testfail @ not executed`
103			`teq r0, #5`
104			`bne testfail`
105			`b 3f`
106			`b testfail`
107			`b testfail`
108			`b testfail`
109			`3:`
110
111			`@ Test that the instruction after two ldrs, where the second ldr depends on the first,`
112			`@ is executed.`
113			`mov r0, #5`
114			`cmp r0, #6`
115			`ldmeqia sp!, {r4,pc}`
116			`ldr r2, Data1`
117			`ldr r2, [r2]`
118			`mov r0, #7`
119			`cmp r0, #7`
120			`movne r10, #30`
121			`bne testfail`
122
123			`cmp r2, #0xff`
124			`movne r10, #40`
125			`bne testfail`
126
127
128			`@ ---------------------`
129			`@ Enable the cache`
130			`@ ---------------------`
131			`mvn r0, #0`
132			`mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area`
133			`mov r0, #1`
134			`mcr 15, 0, r0, cr2, cr0, 0 @ cache enable`
135
136			`subs r7, r7, #10`
137			`bne 1b`
138
139			`b testpass`
140
141			`b testfail`
142			`b testfail`
143
144			`testfail:`
145			`ldr r11, AdrTestStatus`
146			`str r10, [r11]`
147			`b testfail`
148
149			`testpass:`
150			`ldr r11, AdrTestStatus`
151			`mov r10, #17`
152			`str r10, [r11]`
153			`b testpass`
154
155
156			`/* Write 17 to this address to generate a Test Passed message */`
157			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
158			`Data1: .word Data2`
159			`Data2: .word 0xff`
160
161			`/* ========================================================================= */`
162			`/* ========================================================================= */`
163

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[/] [amber/] [trunk/] [hw/] [tests/] [flow3.S] - Blame information for rev 48