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[/] [amber/] [trunk/] [hw/] [tests/] [irq.S] - Blame information for rev 61

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/*****************************************************************
//                                                              //
//  Amber 2 Core Interrupt Test                                 //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests running a simple algorithm to add a bunch of numbers  //
//  and check that the result is correct. This algorithm runs   //
//  80 times. During this, a whole bunch of IRQ interrupts are  //
//  triggered using the random timer.                           //
//                                                              //
//  The test passes if the add algorithm runs successfully      //
//  each time.                                                  //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
 
        /* 0x00 Reset Interrupt vector address */
        b       start
 
        /* 0x04 Undefined Instruction Interrupt vector address */
        b       testfail
 
        /* 0x08 SWI Interrupt vector address */
        b       testfail
 
        /* 0x0c Prefetch abort Interrupt vector address */
        b       testfail
 
        /* 0x10 Data abort Interrupt vector address */
        b       testfail
        b       testfail
 
        /* 0x18 IRQ vector address */
        b       service_irq
 
        /* 0x1c FIRQ vector address */
        b       testfail
 
 
start:
        /* Set Supervisor Mode stack pointer */
        ldr     sp, AdrSVCStack
 
        /* Switch to IRQ Mode */
        mov     r0, #0x00000002
        teqp    pc, r0
        /* Set IRQ Mode stack pointer */
        ldr     sp, AdrIRQStack
 
        /* Switch to User Mode */
        /* and unset interrupt mask bits */
        mov     r0,   #0x00000000
        teqp    pc, r0
 
        /* Set User Mode stack pointer */
        ldr     sp, AdrUSRStack
 
        ldr     r4, AdrRanNum
        ldr     r5, [r4]
        and     r5, r5, #0x1c
        add     r5, r5, #5
        ldr     r6, AdrIRQTimer
        str     r5, [r6]
 
        mov     r2,     #0
 
loop:
        @ set some condition bits
        @ to test that these get preserved
        @ correctly through interrupts
        mov     r3,     #4
        subs    r3, r3, #4
 
        mov     r1,     #1
        add     r1, r1, #2
        add     r1, r1, #3
        add     r1, r1, #4
        addeq   r1, r1, #5
        add     r1, r1, #6
        add     r1, r1, #7
        addeq   r1, r1, #8
        add     r1, r1, #9
        add     r1, r1, #10
        add     r1, r1, #11
        add     r1, r1, #12
 
        mov     r7, #13
        mov     r8, #14
        mov     r9, #15
 
        stmfd   sp!, {r7, r8, r9}
        mov     r7, #0
        mov     r8, #0
        mov     r9, #0
        ldmfd   sp!, {r7, r8, r9}
 
        add     r1, r1, r7
        add     r1, r1, r8
        add     r1, r1, r9
 
        add     r1, r1, #16
        add     r1, r1, #17
        add     r1, r1, #18
        add     r1, r1, #19
        add     r1, r1, #20
        add     r1, r1, #21
        add     r1, r1, #22
        add     r1, r1, #23
        add     r1, r1, #24
        add     r1, r1, #25
        add     r1, r1, #26
        add     r1, r1, #27
        add     r1, r1, #28
        add     r1, r1, #29
        add     r1, r1, #30
        add     r1, r1, #47   @ adds up to exactly 512
 
        cmp     r1, #512
        movne   r10, r2
        bne     testfail
 
        cmp     r2, #80
        beq     testpass
 
        add     r2, r2, #1
        b       loop
 
        @ just put these here in case
        @ the cpu incorrectly executes some instructions
        b       testfail
        b       testfail
        b       testfail
 
 
service_irq:
        @ Save lr to the stack
        stmfd   sp!, {lr}
 
        @ Set the IRQ Timer to a random number
        ldr     r5, [r4]
        and     r5, r5, #0x7f
 
        @ Ensure that never set the IRQ timer to zero
        add     r5, r5, #30
        str     r5, [r6]
 
        @ Restore lr from the stack
        ldmfd   sp!, {lr}
 
        @ Jump straight back to normal execution
        subs    pc, lr, #4
 
@ ------------------------------------------
@ ------------------------------------------
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word ADR_AMBER_TEST_STATUS
AdrRanNum:      .word ADR_AMBER_TEST_RANDOM_NUM
AdrIRQTimer:    .word ADR_AMBER_TEST_IRQ_TIMER
 
AdrText1:       .word  Text1
 
AdrSVCStack:    .word  0x0800
AdrUSRStack:    .word  0x1000
AdrIRQStack:    .word  0x1800
 
 
        .align 2
Text1:  .ascii  "Interrupt!\n\000"
 
/* ========================================================================= */
/* ========================================================================= */
 
 

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[/] [amber/] [trunk/] [hw/] [tests/] [irq.S] - Blame information for rev 61

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Interrupt Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests running a simple algorithm to add a bunch of numbers //`
10			`// and check that the result is correct. This algorithm runs //`
11			`// 80 times. During this, a whole bunch of IRQ interrupts are //`
12			`// triggered using the random timer. //`
13			`// //`
14			`// The test passes if the add algorithm runs successfully //`
15			`// each time. //`
16			`// //`
17			`// Author(s): //`
18			`// - Conor Santifort, csantifort.amber@gmail.com //`
19			`// //`
20			`//////////////////////////////////////////////////////////////////`
21			`// //`
22			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
23			`// //`
24			`// This source file may be used and distributed without //`
25			`// restriction provided that this copyright statement is not //`
26			`// removed from the file and that any derivative work contains //`
27			`// the original copyright notice and the associated disclaimer. //`
28			`// //`
29			`// This source file is free software; you can redistribute it //`
30			`// and/or modify it under the terms of the GNU Lesser General //`
31			`// Public License as published by the Free Software Foundation; //`
32			`// either version 2.1 of the License, or (at your option) any //`
33			`// later version. //`
34			`// //`
35			`// This source is distributed in the hope that it will be //`
36			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
37			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
38			`// PURPOSE. See the GNU Lesser General Public License for more //`
39			`// details. //`
40			`// //`
41			`// You should have received a copy of the GNU Lesser General //`
42			`// Public License along with this source; if not, download it //`
43			`// from http://www.opencores.org/lgpl.shtml //`
44			`// //`
45			`*****************************************************************/`
46
47			`#include "amber_registers.h"`
48
49			`.section .text`
50			`.globl main`
51			`main:`
52
53			`/* 0x00 Reset Interrupt vector address */`
54			`b start`
55
56			`/* 0x04 Undefined Instruction Interrupt vector address */`
57			`b testfail`
58
59			`/* 0x08 SWI Interrupt vector address */`
60			`b testfail`
61
62			`/* 0x0c Prefetch abort Interrupt vector address */`
63			`b testfail`
64
65			`/* 0x10 Data abort Interrupt vector address */`
66			`b testfail`
67			`b testfail`
68
69			`/* 0x18 IRQ vector address */`
70			`b service_irq`
71
72			`/* 0x1c FIRQ vector address */`
73			`b testfail`
74
75
76			`start:`
77			`/* Set Supervisor Mode stack pointer */`
78			`ldr sp, AdrSVCStack`
79
80			`/* Switch to IRQ Mode */`
81			`mov r0, #0x00000002`
82			`teqp pc, r0`
83			`/* Set IRQ Mode stack pointer */`
84			`ldr sp, AdrIRQStack`
85
86			`/* Switch to User Mode */`
87			`/* and unset interrupt mask bits */`
88			`mov r0, #0x00000000`
89			`teqp pc, r0`
90
91			`/* Set User Mode stack pointer */`
92			`ldr sp, AdrUSRStack`
93
94			`ldr r4, AdrRanNum`
95			`ldr r5, [r4]`
96			`and r5, r5, #0x1c`
97			`add r5, r5, #5`
98			`ldr r6, AdrIRQTimer`
99			`str r5, [r6]`
100
101			`mov r2, #0`
102
103			`loop:`
104			`@ set some condition bits`
105			`@ to test that these get preserved`
106			`@ correctly through interrupts`
107			`mov r3, #4`
108			`subs r3, r3, #4`
109
110			`mov r1, #1`
111			`add r1, r1, #2`
112			`add r1, r1, #3`
113			`add r1, r1, #4`
114			`addeq r1, r1, #5`
115			`add r1, r1, #6`
116			`add r1, r1, #7`
117			`addeq r1, r1, #8`
118			`add r1, r1, #9`
119			`add r1, r1, #10`
120			`add r1, r1, #11`
121			`add r1, r1, #12`
122
123			`mov r7, #13`
124			`mov r8, #14`
125			`mov r9, #15`
126
127			`stmfd sp!, {r7, r8, r9}`
128			`mov r7, #0`
129			`mov r8, #0`
130			`mov r9, #0`
131			`ldmfd sp!, {r7, r8, r9}`
132
133			`add r1, r1, r7`
134			`add r1, r1, r8`
135			`add r1, r1, r9`
136
137			`add r1, r1, #16`
138			`add r1, r1, #17`
139			`add r1, r1, #18`
140			`add r1, r1, #19`
141			`add r1, r1, #20`
142			`add r1, r1, #21`
143			`add r1, r1, #22`
144			`add r1, r1, #23`
145			`add r1, r1, #24`
146			`add r1, r1, #25`
147			`add r1, r1, #26`
148			`add r1, r1, #27`
149			`add r1, r1, #28`
150			`add r1, r1, #29`
151			`add r1, r1, #30`
152			`add r1, r1, #47 @ adds up to exactly 512`
153
154			`cmp r1, #512`
155			`movne r10, r2`
156			`bne testfail`
157
158			`cmp r2, #80`
159			`beq testpass`
160
161			`add r2, r2, #1`
162			`b loop`
163
164			`@ just put these here in case`
165			`@ the cpu incorrectly executes some instructions`
166			`b testfail`
167			`b testfail`
168			`b testfail`
169
170
171			`service_irq:`
172			`@ Save lr to the stack`
173			`stmfd sp!, {lr}`
174
175			`@ Set the IRQ Timer to a random number`
176			`ldr r5, [r4]`
177			`and r5, r5, #0x7f`
178
179			`@ Ensure that never set the IRQ timer to zero`
180			`add r5, r5, #30`
181			`str r5, [r6]`
182
183			`@ Restore lr from the stack`
184			`ldmfd sp!, {lr}`
185
186			`@ Jump straight back to normal execution`
187			`subs pc, lr, #4`
188
189			`@ ------------------------------------------`
190			`@ ------------------------------------------`
191
192			`testfail:`
193			`ldr r11, AdrTestStatus`
194			`str r10, [r11]`
195			`b testfail`
196
197			`testpass:`
198			`ldr r11, AdrTestStatus`
199			`mov r10, #17`
200			`str r10, [r11]`
201			`b testpass`
202
203
204
205
206			`/* Write 17 to this address to generate a Test Passed message */`
207			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
208			`AdrRanNum: .word ADR_AMBER_TEST_RANDOM_NUM`
209			`AdrIRQTimer: .word ADR_AMBER_TEST_IRQ_TIMER`
210
211			`AdrText1: .word Text1`
212
213			`AdrSVCStack: .word 0x0800`
214			`AdrUSRStack: .word 0x1000`
215			`AdrIRQStack: .word 0x1800`
216
217
218			`.align 2`
219			`Text1: .ascii "Interrupt!\n\000"`
220
221			`/* ========================================================================= */`
222			`/* ========================================================================= */`
223
224