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[/] [amber/] [trunk/] [hw/] [tests/] [irq_disable.S] - Blame information for rev 72

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1 60 csantifort 
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Interrupt Test                                 //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests running a simple algorithm to add a bunch of numbers  //
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//  and check that the result is correct. This algorithm runs   //
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//  80 times. During this, a whole bunch of IRQ interrupts are  //
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//  triggered using the random timer.                           //
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//                                                              //
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//  The test passes if the add algorithm runs successfully      //
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//  each time.                                                  //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        /* 0x00 Reset Interrupt vector address */
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        b       start
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        /* 0x04 Undefined Instruction Interrupt vector address */
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        b       testfail
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        /* 0x08 SWI Interrupt vector address */
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        b       testfail
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        /* 0x0c Prefetch abort Interrupt vector address */
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        b       testfail
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        /* 0x10 Data abort Interrupt vector address */
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        b       testfail
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        b       testfail
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        /* 0x18 IRQ vector address */
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        b       service_irq
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        /* 0x1c FIRQ vector address */
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        b       testfail
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        /* This doesn't actually disabe the irq because
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           you can't disable it uin user mode */
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disable_irq:
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        orr lr, lr, #0x08000000
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        mov pc, lr
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start:
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        /* Set Supervisor Mode stack pointer */
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        ldr     sp, AdrSVCStack
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        /* Test that lr is immediately accessible after a mode switch */
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        mov     lr, #0x8000
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        mov     r0, #0x08000002
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        teqp    pc, r0 @ move to irq mode
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        nop
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        nop
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        @ Switch back to supervisor mode
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        mov     r0, #0x08000003
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        teqp    pc, r0
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        sub     lr, lr, #4  @ access lr immediately after mode switch
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        mov     r0, #0x8000
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        sub     r0, r0, #4
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        cmp     lr, r0
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        movne   r10, #200
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        bne     testfail
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        /* Switch to IRQ Mode */
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        mov     r0, #0x00000002
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        teqp    pc, r0
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        /* Set IRQ Mode stack pointer */
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        ldr     sp, AdrIRQStack
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        /* Switch to User Mode */
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        /* and unset interrupt mask bits */
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        mov     r0, #0x00000000
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        teqp    pc, r0
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        bl      disable_irq
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        /* Set User Mode stack pointer */
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        ldr     sp, AdrUSRStack
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        ldr     r4, AdrRanNum
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        ldr     r5, [r4]
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        and     r5, r5, #0x1c
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        add     r5, r5, #5
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        ldr     r6, AdrIRQTimer
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        str     r5, [r6]
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        mov     r2,     #0
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loop:
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        @ set some condition bits
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        @ to test that these get preserved
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        @ correctly through interrupts
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        mov     r3,     #4
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        subs    r3, r3, #4
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        mov     r1,     #1
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        add     r1, r1, #2
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        add     r1, r1, #3
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        add     r1, r1, #4
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        addeq   r1, r1, #5
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        add     r1, r1, #6
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        add     r1, r1, #7
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        addeq   r1, r1, #8
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        add     r1, r1, #9
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        add     r1, r1, #10
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        add     r1, r1, #11
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        add     r1, r1, #12
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        mov     r7, #13
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        mov     r8, #14
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        mov     r9, #15
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        stmfd   sp!, {r7, r8, r9}
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        mov     r7, #0
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        mov     r8, #0
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        mov     r9, #0
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        ldmfd   sp!, {r7, r8, r9}
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        add     r1, r1, r7
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        add     r1, r1, r8
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        add     r1, r1, r9
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        add     r1, r1, #16
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        add     r1, r1, #17
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        add     r1, r1, #18
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        add     r1, r1, #19
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        add     r1, r1, #20
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        add     r1, r1, #21
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        add     r1, r1, #22
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        add     r1, r1, #23
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        add     r1, r1, #24
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        add     r1, r1, #25
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        add     r1, r1, #26
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        add     r1, r1, #27
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        add     r1, r1, #28
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        add     r1, r1, #29
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        add     r1, r1, #30
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        add     r1, r1, #47   @ adds up to exactly 512
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        cmp     r1, #512
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        movne   r10, r2
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        bne     testfail
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        cmp     r2, #80
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        beq     testpass
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        add     r2, r2, #1
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        b       loop
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        @ just put these here in case
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        @ the cpu incorrectly executes some instructions
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        b       testfail
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        b       testfail
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        b       testfail
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service_irq:
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        @ Save lr to the stack
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        stmfd   sp!, {lr}
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        @ Set the IRQ Timer to a random number
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        ldr     r5, [r4]
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        and     r5, r5, #0x7f
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        @ Ensure that never set the IRQ timer to zero
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        add     r5, r5, #30
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        str     r5, [r6]
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        @ Restore lr from the stack
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        ldmfd   sp!, {lr}
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        @ Jump straight back to normal execution
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        subs    pc, lr, #4
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@ ------------------------------------------
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@ ------------------------------------------
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:  .word ADR_AMBER_TEST_STATUS
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AdrRanNum:      .word ADR_AMBER_TEST_RANDOM_NUM
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AdrIRQTimer:    .word ADR_AMBER_TEST_IRQ_TIMER
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AdrText1:       .word  Text1
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AdrSVCStack:    .word  0x0800
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AdrUSRStack:    .word  0x1000
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AdrIRQStack:    .word  0x1800
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        .align 2
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Text1:  .ascii  "Interrupt!\n\000"
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/* ========================================================================= */
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/* ========================================================================= */
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