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[/] [amber/] [trunk/] [hw/] [tests/] [irq_stm.S] - Blame information for rev 50

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/*****************************************************************
//                                                              //
//  Amber 2 Core Interrupt Test                                 //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests executes a loop of stm instructions. During this,     //
//  a whole bunch of IRQ interrupts are triggered using         //
//  the random timer. The test checks that the stm is           //
//  not executed twice in a row, once before the interrupt      //
//  and again after the interrupt.                              //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
#include "amber_macros.h"
 
        .section .text
        .globl  main
main:
 
        /* 0x00 Reset Interrupt vector address */
        b       start
 
        /* 0x04 Undefined Instruction Interrupt vector address */
        b       testfail
 
        /* 0x08 SWI Interrupt vector address */
        b       testfail
 
        /* 0x0c Prefetch abort Interrupt vector address */
        b       testfail
 
        /* 0x10 Data abort Interrupt vector address */
        b       testfail
        b       testfail
 
        /* 0x18 IRQ vector address */
        b       service_irq
 
        /* 0x1c FIRQ vector address */
        b       testfail
 
 
start:
        @ ---------------------
        @ Enable the cache
        @ ---------------------
        mvn     r0,  #0
        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
        mov     r0,  #1
        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
 
        /* Set Supervisor Mode stack pointer */
        ldr     sp, AdrSVCStack
 
        /* Switch to IRQ Mode */
        mov     r0, #0x00000002
        teqp    pc, r0
        /* Set IRQ Mode stack pointer */
        ldr     sp, AdrIRQStack
 
        /* Switch to User Mode */
        /* and unset interrupt mask bits */
        mov     r0,   #0x00000000
        teqp    pc, r0
 
        /* Set User Mode stack pointer */
        ldr     sp, AdrUSRStack
 
        /* Configure IRQ Timer with a random time */
        ldr     r4, AdrRanNum
        ldr     r5, [r4]
        and     r5, r5, #0x1c
        add     r5, r5, #5
        ldr     r6, AdrIRQTimer
        str     r5, [r6]
 
        mov     r2, #40
        mov     r3, #7
        mov     r7, #0x700
        mov     r13, r7
        @ fill area with zeros
        mov     r8, #0x200
 
1:      str     r8, [r7, -r8]
        subs    r8, r8, #4
        beq     loop
        b       1b
 
 
 
loop:
 
        mov     r3, #5
        ldmdb   r7!, {r8-r11}
        orr     r3,  r3,  r11, lsr #8
        mov     r11, r11, lsl #24
 
        @ Follow the r7 address pointer and make
        @ sure it decrements correctly on each
        @ iteration of the loop
        sub     r13, r13, #16
        compare r7, r13, __LINE__
 
        subs    r2, r2, #1
        beq     testpass
        b       loop
 
        @ just put these here in case
        @ the cpu incorrectly executes some instructions
        b       testfail
        b       testfail
        b       testfail
 
 
service_irq:
        @ Save lr to the stack
        stmfd   sp!, {lr}
 
        @ Set the IRQ Timer to a random number
        ldr     r5, [r4]
        and     r5, r5, #0x7f
 
        @ Ensure that never set the IRQ timer to zero
        add     r5, r5, #30
        str     r5, [r6]
 
        @ Restore lr from the stack
        ldmfd   sp!, {lr}
 
        @ Jump straight back to normal execution
        subs    pc, lr, #4
 
@ ------------------------------------------
@ ------------------------------------------
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word ADR_AMBER_TEST_STATUS
AdrRanNum:      .word ADR_AMBER_TEST_RANDOM_NUM
AdrIRQTimer:    .word ADR_AMBER_TEST_IRQ_TIMER
 
AdrText1:       .word  Text1
 
AdrSVCStack:    .word  0x0800
AdrUSRStack:    .word  0x1000
AdrIRQStack:    .word  0x1800
 
 
        .align 2
Text1:  .ascii  "Interrupt!\n\000"
 
/* ========================================================================= */
/* ========================================================================= */
 
 

Line No.	Rev	Author	Line
1	17	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Interrupt Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests executes a loop of stm instructions. During this, //`
10			`// a whole bunch of IRQ interrupts are triggered using //`
11			`// the random timer. The test checks that the stm is //`
12			`// not executed twice in a row, once before the interrupt //`
13			`// and again after the interrupt. //`
14			`// //`
15			`// Author(s): //`
16			`// - Conor Santifort, csantifort.amber@gmail.com //`
17			`// //`
18			`//////////////////////////////////////////////////////////////////`
19			`// //`
20			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
21			`// //`
22			`// This source file may be used and distributed without //`
23			`// restriction provided that this copyright statement is not //`
24			`// removed from the file and that any derivative work contains //`
25			`// the original copyright notice and the associated disclaimer. //`
26			`// //`
27			`// This source file is free software; you can redistribute it //`
28			`// and/or modify it under the terms of the GNU Lesser General //`
29			`// Public License as published by the Free Software Foundation; //`
30			`// either version 2.1 of the License, or (at your option) any //`
31			`// later version. //`
32			`// //`
33			`// This source is distributed in the hope that it will be //`
34			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
35			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
36			`// PURPOSE. See the GNU Lesser General Public License for more //`
37			`// details. //`
38			`// //`
39			`// You should have received a copy of the GNU Lesser General //`
40			`// Public License along with this source; if not, download it //`
41			`// from http://www.opencores.org/lgpl.shtml //`
42			`// //`
43			`*****************************************************************/`
44
45			`#include "amber_registers.h"`
46	35	csantifort	`#include "amber_macros.h"`
47	17	csantifort
48			`.section .text`
49			`.globl main`
50			`main:`
51
52			`/* 0x00 Reset Interrupt vector address */`
53			`b start`
54
55			`/* 0x04 Undefined Instruction Interrupt vector address */`
56			`b testfail`
57
58			`/* 0x08 SWI Interrupt vector address */`
59			`b testfail`
60
61			`/* 0x0c Prefetch abort Interrupt vector address */`
62			`b testfail`
63
64			`/* 0x10 Data abort Interrupt vector address */`
65			`b testfail`
66			`b testfail`
67
68			`/* 0x18 IRQ vector address */`
69			`b service_irq`
70
71			`/* 0x1c FIRQ vector address */`
72			`b testfail`
73
74
75			`start:`
76			`@ ---------------------`
77			`@ Enable the cache`
78			`@ ---------------------`
79			`mvn r0, #0`
80			`mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area`
81			`mov r0, #1`
82			`mcr 15, 0, r0, cr2, cr0, 0 @ cache enable`
83
84			`/* Set Supervisor Mode stack pointer */`
85			`ldr sp, AdrSVCStack`
86
87			`/* Switch to IRQ Mode */`
88			`mov r0, #0x00000002`
89			`teqp pc, r0`
90			`/* Set IRQ Mode stack pointer */`
91			`ldr sp, AdrIRQStack`
92
93			`/* Switch to User Mode */`
94			`/* and unset interrupt mask bits */`
95			`mov r0, #0x00000000`
96			`teqp pc, r0`
97
98			`/* Set User Mode stack pointer */`
99			`ldr sp, AdrUSRStack`
100
101			`/* Configure IRQ Timer with a random time */`
102			`ldr r4, AdrRanNum`
103			`ldr r5, [r4]`
104			`and r5, r5, #0x1c`
105			`add r5, r5, #5`
106			`ldr r6, AdrIRQTimer`
107			`str r5, [r6]`
108
109			`mov r2, #40`
110			`mov r3, #7`
111			`mov r7, #0x700`
112			`mov r13, r7`
113			`@ fill area with zeros`
114			`mov r8, #0x200`
115
116			`1: str r8, [r7, -r8]`
117			`subs r8, r8, #4`
118			`beq loop`
119			`b 1b`
120
121
122
123			`loop:`
124
125			`mov r3, #5`
126			`ldmdb r7!, {r8-r11}`
127			`orr r3, r3, r11, lsr #8`
128			`mov r11, r11, lsl #24`
129
130			`@ Follow the r7 address pointer and make`
131			`@ sure it decrements correctly on each`
132			`@ iteration of the loop`
133			`sub r13, r13, #16`
134	35	csantifort	`compare r7, r13, __LINE__`
135	17	csantifort
136			`subs r2, r2, #1`
137			`beq testpass`
138			`b loop`
139
140			`@ just put these here in case`
141			`@ the cpu incorrectly executes some instructions`
142			`b testfail`
143			`b testfail`
144			`b testfail`
145
146
147			`service_irq:`
148			`@ Save lr to the stack`
149			`stmfd sp!, {lr}`
150
151			`@ Set the IRQ Timer to a random number`
152			`ldr r5, [r4]`
153			`and r5, r5, #0x7f`
154
155			`@ Ensure that never set the IRQ timer to zero`
156			`add r5, r5, #30`
157			`str r5, [r6]`
158
159			`@ Restore lr from the stack`
160			`ldmfd sp!, {lr}`
161
162			`@ Jump straight back to normal execution`
163			`subs pc, lr, #4`
164
165			`@ ------------------------------------------`
166			`@ ------------------------------------------`
167
168			`testfail:`
169			`ldr r11, AdrTestStatus`
170			`str r10, [r11]`
171			`b testfail`
172
173			`testpass:`
174			`ldr r11, AdrTestStatus`
175			`mov r10, #17`
176			`str r10, [r11]`
177			`b testpass`
178
179
180
181
182			`/* Write 17 to this address to generate a Test Passed message */`
183			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
184			`AdrRanNum: .word ADR_AMBER_TEST_RANDOM_NUM`
185			`AdrIRQTimer: .word ADR_AMBER_TEST_IRQ_TIMER`
186
187			`AdrText1: .word Text1`
188
189			`AdrSVCStack: .word 0x0800`
190			`AdrUSRStack: .word 0x1000`
191			`AdrIRQStack: .word 0x1800`
192
193
194			`.align 2`
195			`Text1: .ascii "Interrupt!\n\000"`
196
197			`/* ========================================================================= */`
198			`/* ========================================================================= */`
199
200

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[/] [amber/] [trunk/] [hw/] [tests/] [irq_stm.S] - Blame information for rev 50