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[/] [amber/] [trunk/] [hw/] [tests/] [ldm1.S] - Blame information for rev 72

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1 2 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Instruction Test                               //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests the standard form of ldm.                             //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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@ ------------------------------------------
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@ 1. ldmda   r14!, {r0-r12}
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@ ------------------------------------------
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        ldr     r14, StaticEnd
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        ldmda   r14!, {r0-r12}
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        @ check that the base register, r14 was correctly updated
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        ldr     r13, StaticEnd
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        sub     r13, r13, #52 @ 13 x 4
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        cmp     r13, r14
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        movne   r10, #10
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        bne     testfail
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        @check the values loaded into r0 to r12
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        @r0
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        mov     r13, #0x05
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        cmp     r13, r0
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        movne   r10, #20
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        bne     testfail
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        @r1
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        mov     r13, #0x06
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        cmp     r13, r1
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        movne   r10, #30
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        bne     testfail
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        @r2
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        mov     r13, #0x07
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        cmp     r13, r2
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        movne   r10, #40
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        bne     testfail
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        @r3
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        mov     r13, #0x08
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        cmp     r13, r3
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        movne   r10, #50
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        bne     testfail
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        @r4
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        mov     r13, #0x09
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        cmp     r13, r4
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        movne   r10, #60
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        bne     testfail
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        @r5
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        mov     r13, #0x0a
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        cmp     r13, r5
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        movne   r10, #70
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        bne     testfail
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        @r6
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        mov     r13, #0x0b
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        cmp     r13, r6
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        movne   r10, #80
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        bne     testfail
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        @r7
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        mov     r13, #0x0c
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        cmp     r13, r7
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        movne   r10, #90
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        bne     testfail
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        @r8
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        mov     r13, #0x0d
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        cmp     r13, r8
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        movne   r10, #100
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        bne     testfail
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        @r9
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        mov     r13, #0x0e
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        cmp     r13, r9
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        movne   r10, #110
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        bne     testfail
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        @r10
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        mov     r13, #0x0f
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        cmp     r13, r10
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        movne   r10, #120
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        bne     testfail
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        @r11
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        mov     r13, #0x10
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        cmp     r13, r11
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        movne   r10, #130
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        bne     testfail
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        @r12
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        mov     r13, #0x11
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        cmp     r13, r12
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        movne   r10, #140
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        bne     testfail
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@ ------------------------------------------
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@ 2. ldmia   r0, {pc}
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@ Test loading the pc
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@ ------------------------------------------
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        ldr     r0, StoreBase
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        ldr     r1, =jump2
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        str     r1, [r0]
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        ldmia   r0, {pc}    @ causes a jump to 'jump2'
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        @ these should never be executed
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        b       testfail
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        b       testfail
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        b       testfail
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        b       testfail
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jump2:  b       start3
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@ ------------------------------------------
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@ 2. ldmia   r0, {r5, pc}
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@ Test loading the pc, as part of a group
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@ ------------------------------------------
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start3:
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        ldr     r0, StoreBase
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        mov     r1, #17
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        str     r1, [r0], #4
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        ldr     r1, =jump3
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        str     r1, [r0]
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        ldr     r0, StoreBase
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        ldmia   r0, {r5, pc}    @ causes a jump to 'jump2'
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        @ these should never be executed
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        b       testfail
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        b       testfail
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        b       testfail
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        b       testfail
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        @ Check that r5 was loaded with the correct value
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jump3:  mov     r7, #17
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        cmp     r5, r7
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        movne   r10, #200
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        bne     testfail
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@ ------------------------------------------
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@ ------------------------------------------
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        b       testpass
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
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StoreBase:      .word  0x800
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StaticBase:     .word  Data1
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StaticEnd:      .word  Data18
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Data1:          .word  0x00
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                .word  0x01
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                .word  0x02
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                .word  0x03
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                .word  0x04
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                .word  0x05
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                .word  0x06
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                .word  0x07
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                .word  0x08
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                .word  0x09
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                .word  0x0a
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                .word  0x0b
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                .word  0x0c
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                .word  0x0d
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                .word  0x0e
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                .word  0x0f
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                .word  0x10
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Data18:         .word  0x11
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/* ========================================================================= */
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/* ========================================================================= */
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