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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests ldm where the user mode registers are loaded          //
//  whilst in a privileged mode.                                //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
 
        @ Start in Supervisor Mode
 
        @ Load values directly into the two dedicated supervisor mode registers
        @ and then check they are unaffected by the ldm instruction
        mov     r13, #17
        mov     r14, #34
 
        @ Load user mode registers with some values from memory
        ldr     r3, StaticBase
        ldmia   r3, {r0-r14}^
 
        cmp     r13, #17
        movne   r10, #200
        bne     testfail
 
        cmp     r14, #34
        movne   r10, #210
        bne     testfail
 
 
        @ Jump into user mode
        @ and check that the user mode registers
        @ were all loaded
        mov     r2, #0x00000000
        teqp    pc, r2
        nop
 
        @ the value 14 comes from the dataset below
        @ thats used by ldm above
        cmp     r14, #0xe
        movne   r10, #10
        bne     testfail
 
        cmp     r13, #0xd
        movne   r10, #20
        bne     testfail
 
        cmp     r12, #0xc
        movne   r10, #30
        bne     testfail
 
        cmp     r11, #0xb
        movne   r10, #40
        bne     testfail
 
        cmp     r10, #0xa
        movne   r10, #40
        bne     testfail
 
        cmp     r9,  #0x9
        movne   r10, #50
        bne     testfail
 
        cmp     r8,  #0x8
        movne   r10, #60
        bne     testfail
 
        cmp     r7,  #0x7
        movne   r10, #70
        bne     testfail
 
        cmp     r6,  #0x6
        movne   r10, #80
        bne     testfail
 
        cmp     r5,  #0x5
        movne   r10, #90
        bne     testfail
 
        cmp     r4,  #0x4
        movne   r10, #100
        bne     testfail
 
        cmp     r3,  #0x3
        movne   r10, #110
        bne     testfail
 
        cmp     r1,  #0x1
        movne   r10, #130
        bne     testfail
 
        cmp     r0,  #0x0
        movne   r10, #140
        bne     testfail
 
@ ------------------------------------------
@ ------------------------------------------
 
        b       testpass
 
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
StoreBase:      .word  0x800
StaticBase:     .word  Data1
StaticEnd:      .word  Data18
 
Data1:          .word  0x00
                .word  0x01
                .word  0x02
                .word  0x03
                .word  0x04
                .word  0x05
                .word  0x06
                .word  0x07
                .word  0x08
                .word  0x09
                .word  0x0a
                .word  0x0b
                .word  0x0c
                .word  0x0d
                .word  0x0e
                .word  0x0f
                .word  0x10
Data18:         .word  0x11
 
/* ========================================================================= */
/* ========================================================================= */
 
 

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests ldm where the user mode registers are loaded //`
10			`// whilst in a privileged mode. //`
11			`// //`
12			`// Author(s): //`
13			`// - Conor Santifort, csantifort.amber@gmail.com //`
14			`// //`
15			`//////////////////////////////////////////////////////////////////`
16			`// //`
17			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
18			`// //`
19			`// This source file may be used and distributed without //`
20			`// restriction provided that this copyright statement is not //`
21			`// removed from the file and that any derivative work contains //`
22			`// the original copyright notice and the associated disclaimer. //`
23			`// //`
24			`// This source file is free software; you can redistribute it //`
25			`// and/or modify it under the terms of the GNU Lesser General //`
26			`// Public License as published by the Free Software Foundation; //`
27			`// either version 2.1 of the License, or (at your option) any //`
28			`// later version. //`
29			`// //`
30			`// This source is distributed in the hope that it will be //`
31			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
32			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
33			`// PURPOSE. See the GNU Lesser General Public License for more //`
34			`// details. //`
35			`// //`
36			`// You should have received a copy of the GNU Lesser General //`
37			`// Public License along with this source; if not, download it //`
38			`// from http://www.opencores.org/lgpl.shtml //`
39			`// //`
40			`*****************************************************************/`
41
42			`#include "amber_registers.h"`
43
44			`.section .text`
45			`.globl main`
46			`main:`
47
48			`@ Start in Supervisor Mode`
49
50			`@ Load values directly into the two dedicated supervisor mode registers`
51			`@ and then check they are unaffected by the ldm instruction`
52			`mov r13, #17`
53			`mov r14, #34`
54
55			`@ Load user mode registers with some values from memory`
56			`ldr r3, StaticBase`
57			`ldmia r3, {r0-r14}^`
58
59			`cmp r13, #17`
60			`movne r10, #200`
61			`bne testfail`
62
63			`cmp r14, #34`
64			`movne r10, #210`
65			`bne testfail`
66
67
68			`@ Jump into user mode`
69			`@ and check that the user mode registers`
70			`@ were all loaded`
71			`mov r2, #0x00000000`
72			`teqp pc, r2`
73			`nop`
74
75			`@ the value 14 comes from the dataset below`
76			`@ thats used by ldm above`
77			`cmp r14, #0xe`
78			`movne r10, #10`
79			`bne testfail`
80
81			`cmp r13, #0xd`
82			`movne r10, #20`
83			`bne testfail`
84
85			`cmp r12, #0xc`
86			`movne r10, #30`
87			`bne testfail`
88
89			`cmp r11, #0xb`
90			`movne r10, #40`
91			`bne testfail`
92
93			`cmp r10, #0xa`
94			`movne r10, #40`
95			`bne testfail`
96
97			`cmp r9, #0x9`
98			`movne r10, #50`
99			`bne testfail`
100
101			`cmp r8, #0x8`
102			`movne r10, #60`
103			`bne testfail`
104
105			`cmp r7, #0x7`
106			`movne r10, #70`
107			`bne testfail`
108
109			`cmp r6, #0x6`
110			`movne r10, #80`
111			`bne testfail`
112
113			`cmp r5, #0x5`
114			`movne r10, #90`
115			`bne testfail`
116
117			`cmp r4, #0x4`
118			`movne r10, #100`
119			`bne testfail`
120
121			`cmp r3, #0x3`
122			`movne r10, #110`
123			`bne testfail`
124
125			`cmp r1, #0x1`
126			`movne r10, #130`
127			`bne testfail`
128
129			`cmp r0, #0x0`
130			`movne r10, #140`
131			`bne testfail`
132
133			`@ ------------------------------------------`
134			`@ ------------------------------------------`
135
136			`b testpass`
137
138
139			`testfail:`
140			`ldr r11, AdrTestStatus`
141			`str r10, [r11]`
142			`b testfail`
143
144			`testpass:`
145			`ldr r11, AdrTestStatus`
146			`mov r10, #17`
147			`str r10, [r11]`
148			`b testpass`
149
150
151			`/* Write 17 to this address to generate a Test Passed message */`
152			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
153			`StoreBase: .word 0x800`
154			`StaticBase: .word Data1`
155			`StaticEnd: .word Data18`
156
157			`Data1: .word 0x00`
158			`.word 0x01`
159			`.word 0x02`
160			`.word 0x03`
161			`.word 0x04`
162			`.word 0x05`
163			`.word 0x06`
164			`.word 0x07`
165			`.word 0x08`
166			`.word 0x09`
167			`.word 0x0a`
168			`.word 0x0b`
169			`.word 0x0c`
170			`.word 0x0d`
171			`.word 0x0e`
172			`.word 0x0f`
173			`.word 0x10`
174			`Data18: .word 0x11`
175
176			`/* ========================================================================= */`
177			`/* ========================================================================= */`
178
179

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[/] [amber/] [trunk/] [hw/] [tests/] [ldm2.S] - Blame information for rev 14