URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] [ldm_stm_onetwo.S] - Blame information for rev 50

Go to most recent revision | Details | Compare with Previous | View Log


/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests ldm and stm of single registers with cache enabled.   //
//  Tests ldm and stm of 2 registers with cache enabled.        //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
 
        @ Run through the test 4 times
        @ 1 - cache off
        @ 2 - cache on but empty
        @ 3 - cache on and loaded
        @ 4 - same as 3
 
        mov     r10, #400
 
        @ stm 1 -------------------------------------
1:      mov     r0, #0x1000
        mov     r1, r0
 
        ldr     r2, Data2
        stmia   r1!, {r2}
        ldr     r3, [r0], #4
 
        @ Check that the address pointers were both incremented correctly
        cmp     r0, r1
        addne   r10, r10, #1
        bne     testfail
 
        @ Check that the correct value was saved to memory
        cmp     r2, r3
        addne   r10, r10, #2
        bne     testfail
 
 
        @ ldm 1 -------------------------------------
        mov     r0, #0x1000
        mov     r1, r0
 
        ldr     r2, Data2
        str     r2, [r1], #4
        ldmia   r0!, {r3}
 
        @ Check that the address pointers were both incremented correctly
        cmp     r0, r1
        addne   r10, r10, #3
        bne     testfail
 
        @ Check that the correct value was saved to memory
        cmp     r2, r3
        addne   r10, r10, #4
        bne     testfail
 
 
 
        @ ldm 1, pc -------------------------------------
        mov     r0, #0x1000
        mov     r1, r0
 
        ldr     r2, =jpc1
        str     r2, [r1], #4
        ldmia   r0!, {pc}
 
        b       testfail
        b       testfail
        b       testfail
        b       testfail
jpc1:   b       2f
        b       testfail
        b       testfail
        b       testfail
        b       testfail
 
 
        @ Check that the address pointers were both incremented correctly
 2:     cmp     r0, r1
        addne   r10, r10, #5
        bne     testfail
 
 
        @ stm 2 -------------------------------------
        mov     r0, #0x1000
        mov     r1, r0
 
        mov     r4, #0x33
        mov     r6, #0x44
        stmia   r1!, {r4, r6}
        ldr     r7, [r0], #4
        ldr     r8, [r0], #4
 
        @ Check that the address pointers were both incremented correctly
        cmp     r0, r1
        addne   r10, r10, #6
        bne     testfail
 
        @ Check that the correct value was saved to memory
        cmp     r4, r7
        addne   r10, r10, #7
        bne     testfail
        cmp     r6, r8
        addne   r10, r10, #8
        bne     testfail
 
 
        @ ldm 2 -------------------------------------
        mov     r0, #0x1000
        mov     r1, r0
 
        mov     r4, #0x33
        mov     r5, #0x44
        str     r4, [r0], #4
        str     r5, [r0], #4
        ldmia   r1!, {r6, r7}
 
        @ Check that the address pointers were both incremented correctly
        cmp     r0, r1
        addne   r10, r10, #9
        bne     testfail
 
        @ Check that the correct value was saved to memory
        cmp     r4, r6
        addne   r10, r10, #10
        bne     testfail
        cmp     r5, r7
        addne   r10, r10, #11
        bne     testfail
 
 
        @ ldm 2, pc -------------------------------------
        mov     r0, #0x1000
        mov     r1, r0
 
        mov     r4, #0x33
        ldr     r5, =jpc2
        str     r4, [r0], #4
        str     r5, [r0], #4
        ldmia   r1!, {r6, pc}
 
        b       testfail
        b       testfail
        b       testfail
        b       testfail
        b       testfail
jpc2:   b       2f
        b       testfail
        b       testfail
        b       testfail
        b       testfail
        b       testfail
 
 
        @ Check that the address pointers were both incremented correctly
2:      cmp     r0, r1
        addne   r10, r10, #12
        bne     testfail
 
 
        @ ---------------------
        @ Enable the cache
        @ ---------------------
        mvn     r13,  #0
        mcr     15, 0, r13, cr3, cr13, 0   @ cacheable area
        mov     r13,  #1
        mcr     15, 0, r13, cr2, cr13, 0   @ cache enable
 
        subs    r10, r10, #100
        bne     1b
 
        b       testpass
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
AdrHiBootBase:  .word  ADR_HIBOOT_BASE
 
Data1:          .word  0x3
                .word  0x4
                .word  0x5
                .word  0x6
                .word  0x7
Data2:          .word  0x44332211
Data3:          .word  0x12345678
 
/* ========================================================================= */
/* ========================================================================= */
 

Browse

Tools

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] [ldm_stm_onetwo.S] - Blame information for rev 50

Line No.	Rev	Author	Line
1	15	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests ldm and stm of single registers with cache enabled. //`
10			`// Tests ldm and stm of 2 registers with cache enabled. //`
11			`// //`
12			`// Author(s): //`
13			`// - Conor Santifort, csantifort.amber@gmail.com //`
14			`// //`
15			`//////////////////////////////////////////////////////////////////`
16			`// //`
17			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
18			`// //`
19			`// This source file may be used and distributed without //`
20			`// restriction provided that this copyright statement is not //`
21			`// removed from the file and that any derivative work contains //`
22			`// the original copyright notice and the associated disclaimer. //`
23			`// //`
24			`// This source file is free software; you can redistribute it //`
25			`// and/or modify it under the terms of the GNU Lesser General //`
26			`// Public License as published by the Free Software Foundation; //`
27			`// either version 2.1 of the License, or (at your option) any //`
28			`// later version. //`
29			`// //`
30			`// This source is distributed in the hope that it will be //`
31			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
32			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
33			`// PURPOSE. See the GNU Lesser General Public License for more //`
34			`// details. //`
35			`// //`
36			`// You should have received a copy of the GNU Lesser General //`
37			`// Public License along with this source; if not, download it //`
38			`// from http://www.opencores.org/lgpl.shtml //`
39			`// //`
40			`*****************************************************************/`
41
42			`#include "amber_registers.h"`
43
44			`.section .text`
45			`.globl main`
46			`main:`
47
48			`@ Run through the test 4 times`
49			`@ 1 - cache off`
50			`@ 2 - cache on but empty`
51			`@ 3 - cache on and loaded`
52			`@ 4 - same as 3`
53
54			`mov r10, #400`
55
56			`@ stm 1 -------------------------------------`
57			`1: mov r0, #0x1000`
58			`mov r1, r0`
59
60			`ldr r2, Data2`
61			`stmia r1!, {r2}`
62			`ldr r3, [r0], #4`
63
64			`@ Check that the address pointers were both incremented correctly`
65			`cmp r0, r1`
66			`addne r10, r10, #1`
67			`bne testfail`
68
69			`@ Check that the correct value was saved to memory`
70			`cmp r2, r3`
71			`addne r10, r10, #2`
72			`bne testfail`
73
74
75			`@ ldm 1 -------------------------------------`
76			`mov r0, #0x1000`
77			`mov r1, r0`
78
79			`ldr r2, Data2`
80			`str r2, [r1], #4`
81			`ldmia r0!, {r3}`
82
83			`@ Check that the address pointers were both incremented correctly`
84			`cmp r0, r1`
85			`addne r10, r10, #3`
86			`bne testfail`
87
88			`@ Check that the correct value was saved to memory`
89			`cmp r2, r3`
90			`addne r10, r10, #4`
91			`bne testfail`
92
93
94
95			`@ ldm 1, pc -------------------------------------`
96			`mov r0, #0x1000`
97			`mov r1, r0`
98
99			`ldr r2, =jpc1`
100			`str r2, [r1], #4`
101			`ldmia r0!, {pc}`
102
103			`b testfail`
104			`b testfail`
105			`b testfail`
106			`b testfail`
107			`jpc1: b 2f`
108			`b testfail`
109			`b testfail`
110			`b testfail`
111			`b testfail`
112
113
114			`@ Check that the address pointers were both incremented correctly`
115			`2: cmp r0, r1`
116			`addne r10, r10, #5`
117			`bne testfail`
118
119
120			`@ stm 2 -------------------------------------`
121			`mov r0, #0x1000`
122			`mov r1, r0`
123
124			`mov r4, #0x33`
125			`mov r6, #0x44`
126			`stmia r1!, {r4, r6}`
127			`ldr r7, [r0], #4`
128			`ldr r8, [r0], #4`
129
130			`@ Check that the address pointers were both incremented correctly`
131			`cmp r0, r1`
132			`addne r10, r10, #6`
133			`bne testfail`
134
135			`@ Check that the correct value was saved to memory`
136			`cmp r4, r7`
137			`addne r10, r10, #7`
138			`bne testfail`
139			`cmp r6, r8`
140			`addne r10, r10, #8`
141			`bne testfail`
142
143
144			`@ ldm 2 -------------------------------------`
145			`mov r0, #0x1000`
146			`mov r1, r0`
147
148			`mov r4, #0x33`
149			`mov r5, #0x44`
150			`str r4, [r0], #4`
151			`str r5, [r0], #4`
152			`ldmia r1!, {r6, r7}`
153
154			`@ Check that the address pointers were both incremented correctly`
155			`cmp r0, r1`
156			`addne r10, r10, #9`
157			`bne testfail`
158
159			`@ Check that the correct value was saved to memory`
160			`cmp r4, r6`
161			`addne r10, r10, #10`
162			`bne testfail`
163			`cmp r5, r7`
164			`addne r10, r10, #11`
165			`bne testfail`
166
167
168			`@ ldm 2, pc -------------------------------------`
169			`mov r0, #0x1000`
170			`mov r1, r0`
171
172			`mov r4, #0x33`
173			`ldr r5, =jpc2`
174			`str r4, [r0], #4`
175			`str r5, [r0], #4`
176			`ldmia r1!, {r6, pc}`
177
178			`b testfail`
179			`b testfail`
180			`b testfail`
181			`b testfail`
182			`b testfail`
183			`jpc2: b 2f`
184			`b testfail`
185			`b testfail`
186			`b testfail`
187			`b testfail`
188			`b testfail`
189
190
191			`@ Check that the address pointers were both incremented correctly`
192			`2: cmp r0, r1`
193			`addne r10, r10, #12`
194			`bne testfail`
195
196
197			`@ ---------------------`
198			`@ Enable the cache`
199			`@ ---------------------`
200			`mvn r13, #0`
201			`mcr 15, 0, r13, cr3, cr13, 0 @ cacheable area`
202			`mov r13, #1`
203			`mcr 15, 0, r13, cr2, cr13, 0 @ cache enable`
204
205			`subs r10, r10, #100`
206			`bne 1b`
207
208			`b testpass`
209
210			`testfail:`
211			`ldr r11, AdrTestStatus`
212			`str r10, [r11]`
213			`b testfail`
214
215			`testpass:`
216			`ldr r11, AdrTestStatus`
217			`mov r10, #17`
218			`str r10, [r11]`
219			`b testpass`
220
221
222			`/* Write 17 to this address to generate a Test Passed message */`
223			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
224			`AdrHiBootBase: .word ADR_HIBOOT_BASE`
225
226			`Data1: .word 0x3`
227			`.word 0x4`
228			`.word 0x5`
229			`.word 0x6`
230			`.word 0x7`
231			`Data2: .word 0x44332211`
232			`Data3: .word 0x12345678`
233
234			`/* ========================================================================= */`
235			`/* ========================================================================= */`
236