OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] [ldr_str_pc.S] - Blame information for rev 64

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 csantifort
/*****************************************************************
2
//                                                              //
3
//  Amber 2 Core Instruction Test                               //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Tests lrd and str of r15                                    //
10
//                                                              //
11
//  Author(s):                                                  //
12
//      - Conor Santifort, csantifort.amber@gmail.com           //
13
//                                                              //
14
//////////////////////////////////////////////////////////////////
15
//                                                              //
16
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
17
//                                                              //
18
// This source file may be used and distributed without         //
19
// restriction provided that this copyright statement is not    //
20
// removed from the file and that any derivative work contains  //
21
// the original copyright notice and the associated disclaimer. //
22
//                                                              //
23
// This source file is free software; you can redistribute it   //
24
// and/or modify it under the terms of the GNU Lesser General   //
25
// Public License as published by the Free Software Foundation; //
26
// either version 2.1 of the License, or (at your option) any   //
27
// later version.                                               //
28
//                                                              //
29
// This source is distributed in the hope that it will be       //
30
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
31
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
32
// PURPOSE.  See the GNU Lesser General Public License for more //
33
// details.                                                     //
34
//                                                              //
35
// You should have received a copy of the GNU Lesser General    //
36
// Public License along with this source; if not, download it   //
37
// from http://www.opencores.org/lgpl.shtml                     //
38
//                                                              //
39
*****************************************************************/
40
 
41
#include "amber_registers.h"
42
 
43
        .section .text
44
        .globl  main
45
main:
46
        mov     r0, #0x800
47
 
48
        @ this saves with pc and status bits
49
1:      str     pc, [r0]
50
        nop
51
        nop
52
        ldr     r1, [r0]
53
 
54
        @ Check that the mode (supervisor) was saved
55
        and     r2, r1, #3
56
        cmp     r2, #3
57
        movne   r10, #10
58
        bne     testfail
59
 
60
        @ Check that the correct pc value (location + 12) was saved
61
        ldr     r6, FilterPC
62
        and     r3, r1, r6
63
        ldr     r4, =1b
64
        add     r4, r4, #12
65
        cmp     r3, r4
66
        movne   r10, #20
67
        bne     testfail
68
 
69
 
70
        @ loading the pc with ldr only changes the pc values,
71
        @ not the status bits
72
        ldr     pc, =pcx
73
        b       testfail
74
        b       testfail
75
        b       testfail
76
        b       testfail
77
        @ if the jump is 1 ahead or 1 behind the
78
        @ test will fail
79
pcx:    b       2f
80
        b       testfail
81
        b       testfail
82
        b       testfail
83
        b       testfail
84
 
85
        @ Check that the pc load did not change the status bits,
86
        @ - that we're still in supervisor mode
87
2:      mov     r1, pc
88
        and     r2, r1, #3
89
        cmp     r2, #3
90
        movne   r10, #30
91
        bne     testfail
92
 
93
        b       testpass
94
 
95
 
96
testfail:
97
        ldr     r11, AdrTestStatus
98
        str     r10, [r11]
99
        b       testfail
100
 
101
testpass:
102
        ldr     r11, AdrTestStatus
103
        mov     r10, #17
104
        str     r10, [r11]
105
        b       testpass
106
 
107
 
108
/* Write 17 to this address to generate a Test Passed message */
109
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
110
 
111
/* Mark the location of the pc bits of r15 */
112
FilterPC:       .word  0x03fffffc
113
LoadPC:         .word  =pcx
114
 
115
/* ========================================================================= */
116
/* ========================================================================= */
117
 
118
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.