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[/] [amber/] [trunk/] [hw/] [tests/] [mlas_bug.S] - Blame information for rev 2

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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Bug with Multiply Accumulate. The flags were gettting set   //
//  1 cycle early. So in an operation with ( 0 x n ) + 1, the   //
//  Z flag was set because it didn't take into account the      //
//  addition done right at the end.                             //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
 
        .section .text
        .globl  main
main:
 
  @ r6 = mode
  @ r3 = inode->i_mode
 
        @ setup
        mov     r0, #0
        mov     r1, #4
 
        @ -------------------------------------
        @ Replicated code from Linux Kernel
        @ chip.c / set_irq_chip
 
        stmda   sp,{r4, r5, r6, lr}
        ldr     r3, [pc, #120]  @ 2e53ac 
        ldr     r3, [r3]
        cmp     r0, r3
        mov     r5, r1
        bcs     j1
        ldr     r2, [pc, #104]  @ 2e53b0 
        mov     r3, #60 @ 0x3c
        mlas    r6, r0, r3, r2  @ if result == 0 -> warn_slowpath
        bne     j2
j1:
        mov     r3, r0
        mov     r1, #95 @ 0x5f
        ldr     r0, [pc, #84]   @ 2e53b4 
        ldr     r2, [pc, #84]   @ 2e53b8 
        bl      warn_slowpath
        mvn     r0, #21 @ 0x15
        ldmib   sp, {r4, r5, r6, pc}
j2:
        ldr     r3, [pc, #72]   @ 2e53bc 
        cmp     r1, #0  @ 0x0
        moveq   r5, r3
        mov     r4, pc
        orr     r3, r4, #128    @ 0x80
        teqp    pc, r3
        mov     r0, r5
        bl      irq_chip_set_defaults
        ands    r0, r4, #128    @ 0x80
        str     r5, [r6, #8]
        beq     j3
        teqp    pc, r4
        mov     r0, #0  @ 0x0
        ldmib   sp, {r4, r5, r6, pc}
j3:
        teqp    pc, r4
        ldmib   sp,     {r4, r5, r6, pc}
        .word   nr_irqs
        .word   0xc04c6ce4
        .word   0xc0482c14
        .word   0xc0482c28
        .word   0xc04c77e8
 
nr_irqs:
        .word   47
 
        b       testpass
 
        @ -------------------------------------
warn_slowpath:
        mov     r10, #20
        b       testfail
 
irq_chip_set_defaults:
        b       testpass
 
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:              .word ADR_AMBER_TEST_STATUS
 

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Bug with Multiply Accumulate. The flags were gettting set //`
10			`// 1 cycle early. So in an operation with ( 0 x n ) + 1, the //`
11			`// Z flag was set because it didn't take into account the //`
12			`// addition done right at the end. //`
13			`// //`
14			`// Author(s): //`
15			`// - Conor Santifort, csantifort.amber@gmail.com //`
16			`// //`
17			`//////////////////////////////////////////////////////////////////`
18			`// //`
19			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
20			`// //`
21			`// This source file may be used and distributed without //`
22			`// restriction provided that this copyright statement is not //`
23			`// removed from the file and that any derivative work contains //`
24			`// the original copyright notice and the associated disclaimer. //`
25			`// //`
26			`// This source file is free software; you can redistribute it //`
27			`// and/or modify it under the terms of the GNU Lesser General //`
28			`// Public License as published by the Free Software Foundation; //`
29			`// either version 2.1 of the License, or (at your option) any //`
30			`// later version. //`
31			`// //`
32			`// This source is distributed in the hope that it will be //`
33			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
34			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
35			`// PURPOSE. See the GNU Lesser General Public License for more //`
36			`// details. //`
37			`// //`
38			`// You should have received a copy of the GNU Lesser General //`
39			`// Public License along with this source; if not, download it //`
40			`// from http://www.opencores.org/lgpl.shtml //`
41			`// //`
42			`*****************************************************************/`
43
44			`#include "amber_registers.h"`
45
46
47			`.section .text`
48			`.globl main`
49			`main:`
50
51			`@ r6 = mode`
52			`@ r3 = inode->i_mode`
53
54			`@ setup`
55			`mov r0, #0`
56			`mov r1, #4`
57
58			`@ -------------------------------------`
59			`@ Replicated code from Linux Kernel`
60			`@ chip.c / set_irq_chip`
61
62			`stmda sp,{r4, r5, r6, lr}`
63			`ldr r3, [pc, #120] @ 2e53ac`
64			`ldr r3, [r3]`
65			`cmp r0, r3`
66			`mov r5, r1`
67			`bcs j1`
68			`ldr r2, [pc, #104] @ 2e53b0`
69			`mov r3, #60 @ 0x3c`
70			`mlas r6, r0, r3, r2 @ if result == 0 -> warn_slowpath`
71			`bne j2`
72			`j1:`
73			`mov r3, r0`
74			`mov r1, #95 @ 0x5f`
75			`ldr r0, [pc, #84] @ 2e53b4`
76			`ldr r2, [pc, #84] @ 2e53b8`
77			`bl warn_slowpath`
78			`mvn r0, #21 @ 0x15`
79			`ldmib sp, {r4, r5, r6, pc}`
80			`j2:`
81			`ldr r3, [pc, #72] @ 2e53bc`
82			`cmp r1, #0 @ 0x0`
83			`moveq r5, r3`
84			`mov r4, pc`
85			`orr r3, r4, #128 @ 0x80`
86			`teqp pc, r3`
87			`mov r0, r5`
88			`bl irq_chip_set_defaults`
89			`ands r0, r4, #128 @ 0x80`
90			`str r5, [r6, #8]`
91			`beq j3`
92			`teqp pc, r4`
93			`mov r0, #0 @ 0x0`
94			`ldmib sp, {r4, r5, r6, pc}`
95			`j3:`
96			`teqp pc, r4`
97			`ldmib sp, {r4, r5, r6, pc}`
98			`.word nr_irqs`
99			`.word 0xc04c6ce4`
100			`.word 0xc0482c14`
101			`.word 0xc0482c28`
102			`.word 0xc04c77e8`
103
104			`nr_irqs:`
105			`.word 47`
106
107			`b testpass`
108
109			`@ -------------------------------------`
110			`warn_slowpath:`
111			`mov r10, #20`
112			`b testfail`
113
114			`irq_chip_set_defaults:`
115			`b testpass`
116
117
118			`testfail:`
119			`ldr r11, AdrTestStatus`
120			`str r10, [r11]`
121			`b testfail`
122
123			`testpass:`
124			`ldr r11, AdrTestStatus`
125			`mov r10, #17`
126			`str r10, [r11]`
127			`b testpass`
128
129
130			`/* Write 17 to this address to generate a Test Passed message */`
131			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
132

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[/] [amber/] [trunk/] [hw/] [tests/] [mlas_bug.S] - Blame information for rev 2