URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] [stm2.S] - Blame information for rev 20

Go to most recent revision | Details | Compare with Previous | View Log


/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Test jumps into user mode, loads some values into           //
//  registers r8 - r14, then jumps to FIRQ and                  //
//  saves the user mode registers to memory                     //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
        /* 0x00 Reset Interrupt vector address */
        b       start
 
        /* 0x04 Undefined Instruction Interrupt vector address */
        b       testfail
 
        /* 0x08 SWI Interrupt vector address */
        b       testfail
 
        /* 0x0c Prefetch abort Interrupt vector address */
        b       testfail
 
        /* 0x10 Data abort Interrupt vector address */
        b       testfail
 
        /* Address exception Interrupt vector address */
        b       testfail
 
        /* 0x18 IRQ vector address */
        b       testfail
 
        /* 0x1c FIRQ vector address */
        b       service_firq
 
 
start:
        @ Jump into user mode
        mov     r2, #0x00000010
        teqp    pc, r2
 
        ldr     r3, StaticBase
        ldmia   r3, {r8-r14}
 
        @ Jumo into FIRQ mode by triggering a Fast Interrupt
        @ set the firq timer to trigger a firq request
        ldr     r5, AdrFIRQTimer
        mov     r6, #10
        str     r6, [r5]
 
        @ loop waiting for the interrupt
        @ to trigger
loop:   nop
        nop
        nop
        b       loop
 
        @ These should never get executed
        b       testfail
        b       testfail
        b       testfail
 
@ ------------------------------------------
@ ------------------------------------------
service_firq:
        @ Disable the FIRQ Timer
        ldr     r10, AdrFIRQTimer
        mov     r11, #0
        str     r11, [r10]
 
 
        @ load a couple of numbers
        @ into FIRQ registers
        mov     r9,  #50
        mov     r10, #60
        mov     r11, #70
        mov     r12, #80
        mov     r13, #90
        mov     r14, #100
 
        movs    r1, #0
        ldr     r2, StoreBase
 
        @ execute the stm instruction
        @ and check that its conditional execution works
        @ Now in firq mode but this instruction saves the
        @ user mode register values
        stmeqia r2, {r8-pc}^
 
        mov     r4, #4
 
        ldr     r3, [r2], #4
        cmp     r3, #8
        movne   r10, #20
        bne     testfail
 
        ldr     r3, [r2], #4
        cmp     r3, #9
        movne   r10, #30
        bne     testfail
 
        ldr     r3, [r2], #4
        cmp     r3, #10
        movne   r10, #40
        bne     testfail
 
        ldr     r3, [r2], #4
        cmp     r3, #11
        movne   r10, #50
        bne     testfail
 
        ldr     r3, [r2], #4
        cmp     r3, #12
        movne   r10, #60
        bne     testfail
 
        ldr     r3, [r2], #4
        cmp     r3, #13
        movne   r10, #70
        bne     testfail
 
        ldr     r3, [r2], #4
        cmp     r3, #14
        movne   r10, #80
        bne     testfail
 
        b       testpass
 
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
AdrFIRQTimer:   .word  ADR_AMBER_TEST_FIRQ_TIMER
StoreBase:      .word  0x800
StaticBase:     .word  Data1
StaticEnd:      .word  Data18
 
Data1:          .word  0x08
                .word  0x09
                .word  0x0a
                .word  0x0b
                .word  0x0c
                .word  0x0d
                .word  0x0e
                .word  0x0f
                .word  0x10
Data18:         .word  0x11
 
/* ========================================================================= */
/* ========================================================================= */
 
 

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Test jumps into user mode, loads some values into //`
10			`// registers r8 - r14, then jumps to FIRQ and //`
11			`// saves the user mode registers to memory //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`*****************************************************************/`
42
43			`#include "amber_registers.h"`
44
45			`.section .text`
46			`.globl main`
47			`main:`
48			`/* 0x00 Reset Interrupt vector address */`
49			`b start`
50
51			`/* 0x04 Undefined Instruction Interrupt vector address */`
52			`b testfail`
53
54			`/* 0x08 SWI Interrupt vector address */`
55			`b testfail`
56
57			`/* 0x0c Prefetch abort Interrupt vector address */`
58			`b testfail`
59
60			`/* 0x10 Data abort Interrupt vector address */`
61			`b testfail`
62
63			`/* Address exception Interrupt vector address */`
64			`b testfail`
65
66			`/* 0x18 IRQ vector address */`
67			`b testfail`
68
69			`/* 0x1c FIRQ vector address */`
70			`b service_firq`
71
72
73			`start:`
74			`@ Jump into user mode`
75			`mov r2, #0x00000010`
76			`teqp pc, r2`
77
78			`ldr r3, StaticBase`
79			`ldmia r3, {r8-r14}`
80
81			`@ Jumo into FIRQ mode by triggering a Fast Interrupt`
82			`@ set the firq timer to trigger a firq request`
83			`ldr r5, AdrFIRQTimer`
84			`mov r6, #10`
85			`str r6, [r5]`
86
87			`@ loop waiting for the interrupt`
88			`@ to trigger`
89			`loop: nop`
90			`nop`
91			`nop`
92			`b loop`
93
94			`@ These should never get executed`
95			`b testfail`
96			`b testfail`
97			`b testfail`
98
99			`@ ------------------------------------------`
100			`@ ------------------------------------------`
101			`service_firq:`
102			`@ Disable the FIRQ Timer`
103			`ldr r10, AdrFIRQTimer`
104			`mov r11, #0`
105			`str r11, [r10]`
106
107
108			`@ load a couple of numbers`
109			`@ into FIRQ registers`
110			`mov r9, #50`
111			`mov r10, #60`
112			`mov r11, #70`
113			`mov r12, #80`
114			`mov r13, #90`
115			`mov r14, #100`
116
117			`movs r1, #0`
118			`ldr r2, StoreBase`
119
120			`@ execute the stm instruction`
121			`@ and check that its conditional execution works`
122			`@ Now in firq mode but this instruction saves the`
123			`@ user mode register values`
124			`stmeqia r2, {r8-pc}^`
125
126			`mov r4, #4`
127
128			`ldr r3, [r2], #4`
129			`cmp r3, #8`
130			`movne r10, #20`
131			`bne testfail`
132
133			`ldr r3, [r2], #4`
134			`cmp r3, #9`
135			`movne r10, #30`
136			`bne testfail`
137
138			`ldr r3, [r2], #4`
139			`cmp r3, #10`
140			`movne r10, #40`
141			`bne testfail`
142
143			`ldr r3, [r2], #4`
144			`cmp r3, #11`
145			`movne r10, #50`
146			`bne testfail`
147
148			`ldr r3, [r2], #4`
149			`cmp r3, #12`
150			`movne r10, #60`
151			`bne testfail`
152
153			`ldr r3, [r2], #4`
154			`cmp r3, #13`
155			`movne r10, #70`
156			`bne testfail`
157
158			`ldr r3, [r2], #4`
159			`cmp r3, #14`
160			`movne r10, #80`
161			`bne testfail`
162
163			`b testpass`
164
165
166			`testfail:`
167			`ldr r11, AdrTestStatus`
168			`str r10, [r11]`
169			`b testfail`
170
171			`testpass:`
172			`ldr r11, AdrTestStatus`
173			`mov r10, #17`
174			`str r10, [r11]`
175			`b testpass`
176
177
178			`/* Write 17 to this address to generate a Test Passed message */`
179			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
180			`AdrFIRQTimer: .word ADR_AMBER_TEST_FIRQ_TIMER`
181			`StoreBase: .word 0x800`
182			`StaticBase: .word Data1`
183			`StaticEnd: .word Data18`
184
185			`Data1: .word 0x08`
186			`.word 0x09`
187			`.word 0x0a`
188			`.word 0x0b`
189			`.word 0x0c`
190			`.word 0x0d`
191			`.word 0x0e`
192			`.word 0x0f`
193			`.word 0x10`
194			`Data18: .word 0x11`
195
196			`/* ========================================================================= */`
197			`/* ========================================================================= */`
198
199

Browse

Tools

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] [stm2.S] - Blame information for rev 20