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[/] [amber/] [trunk/] [hw/] [tests/] [stm_stream.S] - Blame information for rev 15

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1 15 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Instruction Test                               //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Generates as dense a stream of writes as possible to check  //
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//  that the memory subsystem can cope with this worst case.    //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        @ ---------------------
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        @ Enable the cache
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        @ ---------------------
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        @ The instruction space is cached and the data space is not.
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        @ So when the written data is read back, it comes from
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        @ main memory and not the dcache.
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        mov     r0,  #0x1
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        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
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        mov     r0,  #1
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        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
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        mov     r14, #3
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loop:   mov     r0, #0x1000000
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        add     r1, r14, #0x1
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        add     r2, r14, #0x2
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        add     r3, r14, #0x3
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        add     r4, r14, #0x4
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        add     r5, r14, #0x5
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        add     r6, r14, #0x6
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        add     r7, r14, #0x7
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        add     r8, r14, #0x8
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        @ ---------------------
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        @ write 1024 bytes
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        stm     r0!, {r1-r8}
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        @ Read back and check
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        mov     r0, #0x1000000
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        mov     r13, #320
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1:      mov     r9, r14
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2:      add     r9, r9, #1
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        ldr     r12, [r0], #4
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        cmp     r12, r9
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        addne   r10, r9, r13
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        bne     testfail
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        add     r10, r14, #8
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        cmp     r9, r10
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        bne     2b
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        subs    r13, r13, #10
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        bne     1b
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        subs    r14, r14, #1
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        bne     loop
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        b       testpass
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
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Data1:          .word  Data2
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Data2:          .word  0xff
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/* ========================================================================= */
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/* ========================================================================= */
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