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[/] [amber/] [trunk/] [hw/] [tests/] [swp_lock_bug.S] - Blame information for rev 72

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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Bug broke an instruction read immediately after a swp       //
//  instruction.                                                //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
 
        @ setup
        ldr     r5, Data
        mov     r0, #0
        str     r0, [r5]
 
 
        @ ------------------------------
        mov     r3,  #1
        mov     r0,  r5
        mov     r2,  r3
 
        swp     r1, r2, [r0]
        cmp     r1,  #1
        movcc   r2,  #0
        swphi   r2, r1, [r0]
        cmp     r2,  #0
        bne     testfail
 
 
        b       testpass
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
Data:           .word  0x0011b5c4
 
 
/* ========================================================================= */
/* ========================================================================= */
 
 

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Bug broke an instruction read immediately after a swp //`
10			`// instruction. //`
11			`// //`
12			`// Author(s): //`
13			`// - Conor Santifort, csantifort.amber@gmail.com //`
14			`// //`
15			`//////////////////////////////////////////////////////////////////`
16			`// //`
17			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
18			`// //`
19			`// This source file may be used and distributed without //`
20			`// restriction provided that this copyright statement is not //`
21			`// removed from the file and that any derivative work contains //`
22			`// the original copyright notice and the associated disclaimer. //`
23			`// //`
24			`// This source file is free software; you can redistribute it //`
25			`// and/or modify it under the terms of the GNU Lesser General //`
26			`// Public License as published by the Free Software Foundation; //`
27			`// either version 2.1 of the License, or (at your option) any //`
28			`// later version. //`
29			`// //`
30			`// This source is distributed in the hope that it will be //`
31			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
32			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
33			`// PURPOSE. See the GNU Lesser General Public License for more //`
34			`// details. //`
35			`// //`
36			`// You should have received a copy of the GNU Lesser General //`
37			`// Public License along with this source; if not, download it //`
38			`// from http://www.opencores.org/lgpl.shtml //`
39			`// //`
40			`*****************************************************************/`
41
42			`#include "amber_registers.h"`
43
44			`.section .text`
45			`.globl main`
46			`main:`
47
48			`@ setup`
49			`ldr r5, Data`
50			`mov r0, #0`
51			`str r0, [r5]`
52
53
54			`@ ------------------------------`
55			`mov r3, #1`
56			`mov r0, r5`
57			`mov r2, r3`
58
59			`swp r1, r2, [r0]`
60			`cmp r1, #1`
61			`movcc r2, #0`
62			`swphi r2, r1, [r0]`
63			`cmp r2, #0`
64			`bne testfail`
65
66
67			`b testpass`
68
69			`testfail:`
70			`ldr r11, AdrTestStatus`
71			`str r10, [r11]`
72			`b testfail`
73
74			`testpass:`
75			`ldr r11, AdrTestStatus`
76			`mov r10, #17`
77			`str r10, [r11]`
78			`b testpass`
79
80
81			`/* Write 17 to this address to generate a Test Passed message */`
82			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
83			`Data: .word 0x0011b5c4`
84
85
86			`/* ========================================================================= */`
87			`/* ========================================================================= */`
88
89

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[/] [amber/] [trunk/] [hw/] [tests/] [swp_lock_bug.S] - Blame information for rev 72