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[/] [amber/] [trunk/] [hw/] [tests/] [tst.S] - Blame information for rev 87

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/*****************************************************************
//                                                              //
//  Amber 2 Core Instruction Test                               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests add with carry                                        //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
#include "amber_macros.h"
 
        .section .text
        .globl  main
main:
        // sets all four flags
        // Cant use p version of instrustion in 32-bit CPU because it writes the upper 4 bits of PC
        teqp    pc, #0xf0000000
 
        //
        // Check that they are set
        bvc     testfail  // V flag
        bpl     testfail  // N flag
        bne     testfail  // Z flag
        bcc     testfail  // C flag
 
        mov     r1, #0
 
        // should not unset the V flag value
        tst     r1, #0
 
        // Check the V flag and Z flag are still set, the C flag
        // is set to the carry out, and the N flag gets cleared
        bvc     testfail
        bne     testfail
        bcc     testfail
        bmi     testfail
 
        // Test "Strange issue with r12 after TEQLSP"
        mov     r1,  #0x1
        mov     r2,  #0x1
        mov     r8,  #0
        mov     r6,  #10
        mov     r10, #13
        mov     r12, #100
        nop
 
        add     r6,  r6,#1
        cmp     r6,  r8
        ldrls   r3,  [r9,r6,lsl #2]
        movls   r4,  r11
        movhi   r3,  #0
        teqp    r1,  r2 // r1 XOR r2 = 0x1 -> sets the mode bits of the PC to 1
        mov     r12, r6 // normal r12 or FIRQ r12 ?
 
 
        // test if carry flag correctly set
        // set the carry up
        mov     r1,  #0xffffffff
        adds    r1,  r1, #1
 
        // do the test
        mov     r1,  #0x00800000
        tst     r1,  #0x00ff0000
        movcc   r0,  #0
        movcs   r0,  #1
 
        // test carry flag
        mov     r0,  #2
        mov     r1,  #1
        mov     r3,  #0x930
        cmp     r0,  #1
        mov     r1,  r3
        tst     r1,  #0x10
 
        bcc     testfail
        bcc     testfail
        bcc     testfail
 
 
        // clears all four flags
        // Cant use p version of instrustion in 32-bit CPU because it writes the upper 4 bits of PC
        teqp    pc, #0x00000000
 
        mov     r0, #2
        mov     r1, #1
        mov     r3, #0x930
        // next instruction sets the carry flag
        // compare subtracts a 1 from the r0 value of 2
        // means 2's compliment of '1' gets added to '2', so the carry bit is set
        cmp     r0, #1
        mov     r1, r3
 
        // leaves carry flag at previous value
        tst     r1, #0x10
        bcc     testfail
 
        b       testpass
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
 

Line No.	Rev	Author	Line
1	82	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Instruction Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests add with carry //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`*****************************************************************/`
40
41			`#include "amber_registers.h"`
42			`#include "amber_macros.h"`
43
44			`.section .text`
45			`.globl main`
46			`main:`
47			`// sets all four flags`
48			`// Cant use p version of instrustion in 32-bit CPU because it writes the upper 4 bits of PC`
49			`teqp pc, #0xf0000000`
50
51			`//`
52			`// Check that they are set`
53			`bvc testfail // V flag`
54			`bpl testfail // N flag`
55			`bne testfail // Z flag`
56			`bcc testfail // C flag`
57
58			`mov r1, #0`
59
60			`// should not unset the V flag value`
61			`tst r1, #0`
62
63			`// Check the V flag and Z flag are still set, the C flag`
64	87	csantifort	`// is set to the carry out, and the N flag gets cleared`
65	82	csantifort	`bvc testfail`
66			`bne testfail`
67	87	csantifort	`bcc testfail`
68	82	csantifort	`bmi testfail`
69
70			`// Test "Strange issue with r12 after TEQLSP"`
71			`mov r1, #0x1`
72			`mov r2, #0x1`
73			`mov r8, #0`
74			`mov r6, #10`
75			`mov r10, #13`
76			`mov r12, #100`
77			`nop`
78
79			`add r6, r6,#1`
80			`cmp r6, r8`
81			`ldrls r3, [r9,r6,lsl #2]`
82			`movls r4, r11`
83			`movhi r3, #0`
84	83	csantifort	`teqp r1, r2 // r1 XOR r2 = 0x1 -> sets the mode bits of the PC to 1`
85	82	csantifort	`mov r12, r6 // normal r12 or FIRQ r12 ?`
86
87	83	csantifort
88			`// test if carry flag correctly set`
89			`// set the carry up`
90			`mov r1, #0xffffffff`
91			`adds r1, r1, #1`
92
93			`// do the test`
94			`mov r1, #0x00800000`
95			`tst r1, #0x00ff0000`
96			`movcc r0, #0`
97			`movcs r0, #1`
98
99	87	csantifort	`// test carry flag`
100			`mov r0, #2`
101			`mov r1, #1`
102			`mov r3, #0x930`
103			`cmp r0, #1`
104			`mov r1, r3`
105			`tst r1, #0x10`
106
107			`bcc testfail`
108			`bcc testfail`
109			`bcc testfail`
110
111
112			`// clears all four flags`
113			`// Cant use p version of instrustion in 32-bit CPU because it writes the upper 4 bits of PC`
114			`teqp pc, #0x00000000`
115
116			`mov r0, #2`
117			`mov r1, #1`
118			`mov r3, #0x930`
119			`// next instruction sets the carry flag`
120			`// compare subtracts a 1 from the r0 value of 2`
121			`// means 2's compliment of '1' gets added to '2', so the carry bit is set`
122			`cmp r0, #1`
123			`mov r1, r3`
124
125			`// leaves carry flag at previous value`
126			`tst r1, #0x10`
127			`bcc testfail`
128
129	82	csantifort	`b testpass`
130
131			`testfail:`
132			`ldr r11, AdrTestStatus`
133			`str r10, [r11]`
134			`b testfail`
135
136			`testpass:`
137			`ldr r11, AdrTestStatus`
138			`mov r10, #17`
139			`str r10, [r11]`
140			`b testpass`
141
142
143			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
144

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[/] [amber/] [trunk/] [hw/] [tests/] [tst.S] - Blame information for rev 87