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[/] [amber/] [trunk/] [hw/] [tests/] [undefined_ins.S] - Blame information for rev 2

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/*****************************************************************
//                                                              //
//  Amber 2 Core Interrupt Test                                 //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Tests Undefined Instruction Interrupt                       //
//  Fires a few FP instructions into the core. These            //
//  cause undefined instruction interrupts when executed.       //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
*****************************************************************/
 
#include "amber_registers.h"
 
        .section .text
        .globl  main
main:
        /* 0x00 Reset Interrupt vector address */
        b       start
 
        /* 0x04 Undefined Instruction Interrupt vector address */
        b       service_undefined_instruction
 
        /* 0x08 SWI Interrupt vector address */
        b       testfail
 
        /* 0x0c Prefetch abort Interrupt vector address */
        b       testfail
 
        /* 0x10 Data abort Interrupt vector address */
        b       testfail
 
        /* 0x14 whats this one for? */
        b       testfail
 
        /* 0x18 IRQ vector address */
        b       testfail
 
        /* 0x1c FIRQ vector address */
        b       testfail
 
 
start:
        @ count interrupts
        mov     r0, #0
        mov     r8, #0
 
        @ set the flags to not equal so some undefined instructions tested below
        @ won't execute (which we want)
        cmp     r0, #1
 
        @ save status bits so can check value in isr
        ldr     r3, PCMask
        mov     r4, pc
        bic     r4, r4, r3
 
        @ floating point instruction
        @ ldfp  f2, [ip], #8   @  ecfca102
.word   0xecfca102
 
 
pos1:
        @ fstmiax       ip!, {d8-d15}
.word   0xecac8b11
 
pos2:
        @ Next FP instruction is not executed, so does not
        @ cause an interrupt
        @ stfpeq        f2, [ip], #8
.word   0x0ceca102
        add     r8, r8, #7  @ executes
        addeq   r8, r8, #3  @ doesnt execute
 
        @ fmxr  fpscr, r1
.word   0xeee11a10
 
pos3:
        @ Check that the isr has run the correction number of times
        cmp     r0, #12     @ 3 times = 12
        movne   r10, #120
        bne     testfail
 
        @ Check that the mov r8 instruction was executed
        cmp     r8, #7
        movne   r10, #130
        bne     testfail
 
        b       testpass
        b       testfail
        b       testfail
 
 
service_undefined_instruction:
        @ Check the r14 return address is correct
        ldr     r1, =Adrpos1
        @ add the interrupt number (which increments by 4 each time)
        add     r1, r1, r0
 
        @ Check the expected return address
        ldr     r2, [r1]
        ldr     r13, PCMask
        and     r13, r13, r14
        cmp     r2, r13
        movne   r10, r0
        bne     testfail
 
        @ Check the status bits
        ldr     r13, PCMask
        bic     r5, r14, r13
        cmp     r4, r5
        movne   r10, #100
        bne     testfail
 
        @ Check that Mode == SVC
        mov     r6, pc
        and     r6, r6, #0x3
        cmp     r6, #0x3
        movne   r10, #110
        bne     testfail
 
        @ increment the isr counter
        add     r0, r0, #4
 
        @ return to the next instruction from the isr
        movs    pc, r14
 
        b       testfail
        b       testfail
        b       testfail
 
@ ------------------------------------------
@ ------------------------------------------
 
 
testfail:
        ldr     r11, AdrTestStatus
        str     r10, [r11]
        b       testfail
 
testpass:
        ldr     r11, AdrTestStatus
        mov     r10, #17
        str     r10, [r11]
        b       testpass
 
 
 
/* Write 17 to this address to generate a Test Passed message */
AdrTestStatus:              .word ADR_AMBER_TEST_STATUS
Adrpos1:                    .word pos1
Adrpos2:                    .word pos2
Adrpos3:                    .word pos3
PCMask:                     .word 0x03fffffc

Line No.	Rev	Author	Line
1	2	csantifort	`/*****************************************************************`
2			`// //`
3			`// Amber 2 Core Interrupt Test //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Tests Undefined Instruction Interrupt //`
10			`// Fires a few FP instructions into the core. These //`
11			`// cause undefined instruction interrupts when executed. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`*****************************************************************/`
42
43			`#include "amber_registers.h"`
44
45			`.section .text`
46			`.globl main`
47			`main:`
48			`/* 0x00 Reset Interrupt vector address */`
49			`b start`
50
51			`/* 0x04 Undefined Instruction Interrupt vector address */`
52			`b service_undefined_instruction`
53
54			`/* 0x08 SWI Interrupt vector address */`
55			`b testfail`
56
57			`/* 0x0c Prefetch abort Interrupt vector address */`
58			`b testfail`
59
60			`/* 0x10 Data abort Interrupt vector address */`
61			`b testfail`
62
63			`/* 0x14 whats this one for? */`
64			`b testfail`
65
66			`/* 0x18 IRQ vector address */`
67			`b testfail`
68
69			`/* 0x1c FIRQ vector address */`
70			`b testfail`
71
72
73			`start:`
74			`@ count interrupts`
75			`mov r0, #0`
76			`mov r8, #0`
77
78			`@ set the flags to not equal so some undefined instructions tested below`
79			`@ won't execute (which we want)`
80			`cmp r0, #1`
81
82			`@ save status bits so can check value in isr`
83			`ldr r3, PCMask`
84			`mov r4, pc`
85			`bic r4, r4, r3`
86
87			`@ floating point instruction`
88			`@ ldfp f2, [ip], #8 @ ecfca102`
89			`.word 0xecfca102`
90
91
92			`pos1:`
93			`@ fstmiax ip!, {d8-d15}`
94			`.word 0xecac8b11`
95
96			`pos2:`
97			`@ Next FP instruction is not executed, so does not`
98			`@ cause an interrupt`
99			`@ stfpeq f2, [ip], #8`
100			`.word 0x0ceca102`
101			`add r8, r8, #7 @ executes`
102			`addeq r8, r8, #3 @ doesnt execute`
103
104			`@ fmxr fpscr, r1`
105			`.word 0xeee11a10`
106
107			`pos3:`
108			`@ Check that the isr has run the correction number of times`
109			`cmp r0, #12 @ 3 times = 12`
110			`movne r10, #120`
111			`bne testfail`
112
113			`@ Check that the mov r8 instruction was executed`
114			`cmp r8, #7`
115			`movne r10, #130`
116			`bne testfail`
117
118			`b testpass`
119			`b testfail`
120			`b testfail`
121
122
123			`service_undefined_instruction:`
124			`@ Check the r14 return address is correct`
125			`ldr r1, =Adrpos1`
126			`@ add the interrupt number (which increments by 4 each time)`
127			`add r1, r1, r0`
128
129			`@ Check the expected return address`
130			`ldr r2, [r1]`
131			`ldr r13, PCMask`
132			`and r13, r13, r14`
133			`cmp r2, r13`
134			`movne r10, r0`
135			`bne testfail`
136
137			`@ Check the status bits`
138			`ldr r13, PCMask`
139			`bic r5, r14, r13`
140			`cmp r4, r5`
141			`movne r10, #100`
142			`bne testfail`
143
144			`@ Check that Mode == SVC`
145			`mov r6, pc`
146			`and r6, r6, #0x3`
147			`cmp r6, #0x3`
148			`movne r10, #110`
149			`bne testfail`
150
151			`@ increment the isr counter`
152			`add r0, r0, #4`
153
154			`@ return to the next instruction from the isr`
155			`movs pc, r14`
156
157			`b testfail`
158			`b testfail`
159			`b testfail`
160
161			`@ ------------------------------------------`
162			`@ ------------------------------------------`
163
164
165			`testfail:`
166			`ldr r11, AdrTestStatus`
167			`str r10, [r11]`
168			`b testfail`
169
170			`testpass:`
171			`ldr r11, AdrTestStatus`
172			`mov r10, #17`
173			`str r10, [r11]`
174			`b testpass`
175
176
177
178			`/* Write 17 to this address to generate a Test Passed message */`
179			`AdrTestStatus: .word ADR_AMBER_TEST_STATUS`
180			`Adrpos1: .word pos1`
181			`Adrpos2: .word pos2`
182			`Adrpos3: .word pos3`
183			`PCMask: .word 0x03fffffc`

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[/] [amber/] [trunk/] [hw/] [tests/] [undefined_ins.S] - Blame information for rev 2