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1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  L1 Cache for Amber 2 Core                                   //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Synthesizable L1 Unified Data and Instruction Cache         //
10
//  Cache is 4-way, 256 line and 16 bytes per line for          //
11
//  a total of 16KB. The cache policy is write-through and      //
12
//  read allocate. For swap instructions (SWP and SWPB) the     //
13
//  location is evicted from the cache and read from main       //
14
//  memory.                                                     //
15
//                                                              //
16
//  Author(s):                                                  //
17
//      - Conor Santifort, csantifort.amber@gmail.com           //
18
//                                                              //
19
//////////////////////////////////////////////////////////////////
20
//                                                              //
21
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
22
//                                                              //
23
// This source file may be used and distributed without         //
24
// restriction provided that this copyright statement is not    //
25
// removed from the file and that any derivative work contains  //
26
// the original copyright notice and the associated disclaimer. //
27
//                                                              //
28
// This source file is free software; you can redistribute it   //
29
// and/or modify it under the terms of the GNU Lesser General   //
30
// Public License as published by the Free Software Foundation; //
31
// either version 2.1 of the License, or (at your option) any   //
32
// later version.                                               //
33
//                                                              //
34
// This source is distributed in the hope that it will be       //
35
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
36
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
37
// PURPOSE.  See the GNU Lesser General Public License for more //
38
// details.                                                     //
39
//                                                              //
40
// You should have received a copy of the GNU Lesser General    //
41
// Public License along with this source; if not, download it   //
42
// from http://www.opencores.org/lgpl.shtml                     //
43
//                                                              //
44
//////////////////////////////////////////////////////////////////
45 82 csantifort
`include "global_defines.vh"
46
`include "a23_config_defines.vh"
47 2 csantifort
 
48 15 csantifort
module a23_cache
49 2 csantifort
#(
50
 
51
// ---------------------------------------------------------
52
// Cache Configuration
53
 
54
// Limited to Linux 4k page sizes -> 256 lines
55
parameter CACHE_LINES          = 256,
56
 
57
// This cannot be changed without some major surgeory on
58
// this module                                       
59
parameter CACHE_WORDS_PER_LINE = 4,
60
 
61
// Changing this parameter is the recommended
62
// way to change the overall cache size; 2, 4 and 8 ways are supported.
63
//   2 ways -> 8KB  cache
64
//   4 ways -> 16KB cache
65
//   8 ways -> 32KB cache
66 15 csantifort
parameter WAYS              = `A23_CACHE_WAYS ,
67 2 csantifort
 
68
// derived configuration parameters
69
parameter CACHE_ADDR_WIDTH  = log2 ( CACHE_LINES ),                        // = 8
70
parameter WORD_SEL_WIDTH    = log2 ( CACHE_WORDS_PER_LINE ),               // = 2
71
parameter TAG_ADDR_WIDTH    = 32 - CACHE_ADDR_WIDTH - WORD_SEL_WIDTH - 2,  // = 20
72
parameter TAG_WIDTH         = TAG_ADDR_WIDTH + 1,                          // = 21, including Valid flag
73
parameter CACHE_LINE_WIDTH  = CACHE_WORDS_PER_LINE * 32,                   // = 128
74
parameter TAG_ADDR32_LSB    = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2,       // = 12
75
parameter CACHE_ADDR32_MSB  = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2 - 1,   // = 11
76
parameter CACHE_ADDR32_LSB  =                    WORD_SEL_WIDTH + 2    ,   // = 4
77
parameter WORD_SEL_MSB      = WORD_SEL_WIDTH + 2 - 1,                      // = 3
78
parameter WORD_SEL_LSB      =                  2                           // = 2
79
// ---------------------------------------------------------
80
)
81
 
82
 
83
(
84
input                               i_clk,
85
 
86
// Read / Write requests from core
87
input                               i_select,
88
input                               i_exclusive,        // exclusive access, part of swap instruction
89
input      [31:0]                   i_write_data,
90
input                               i_write_enable,     // core issued write request
91
input      [31:0]                   i_address,          // registered address from execute
92
input      [31:0]                   i_address_nxt,      // un-registered version of address from execute stage
93
input      [3:0]                    i_byte_enable,
94
input                               i_cache_enable,     // from co-processor 15 configuration register
95
input                               i_cache_flush,      // from co-processor 15 register
96
 
97
output      [31:0]                  o_read_data,
98
input                               i_core_stall,
99
output                              o_stall,
100
 
101
// WB Read Request                                                          
102
output                              o_wb_req,          // Read Request
103
input      [31:0]                   i_wb_address,      // wb bus                                 
104
input      [31:0]                   i_wb_read_data,    // wb bus                              
105
input                               i_wb_stall         // wb_stb && !wb_ack
106
);
107
 
108 82 csantifort
`include "a23_localparams.vh"
109
`include "a23_functions.vh"
110 2 csantifort
 
111
// One-hot encoded
112
localparam       C_INIT   = 0,
113
                 C_CORE   = 1,
114
                 C_FILL   = 2,
115
                 C_INVA   = 3,
116
                 C_STATES = 4;
117
 
118
localparam [3:0] CS_INIT            = 4'd0,
119
                 CS_IDLE            = 4'd1,
120
                 CS_FILL1           = 4'd2,
121
                 CS_FILL2           = 4'd3,
122
                 CS_FILL3           = 4'd4,
123
                 CS_FILL4           = 4'd5,
124
                 CS_FILL_COMPLETE   = 4'd6,
125
                 CS_TURN_AROUND     = 4'd7,
126
                 CS_WRITE_HIT1      = 4'd8,
127
                 CS_EX_DELETE       = 4'd9;
128
 
129
 
130 15 csantifort
reg  [3:0]                  c_state    = CS_IDLE;
131
reg  [C_STATES-1:0]         source_sel = 1'd1 << C_CORE;
132 2 csantifort
reg  [CACHE_ADDR_WIDTH:0]   init_count = 'd0;
133
 
134
wire [TAG_WIDTH-1:0]        tag_rdata_way [WAYS-1:0];
135
wire [CACHE_LINE_WIDTH-1:0] data_rdata_way[WAYS-1:0];
136
wire [WAYS-1:0]             data_wenable_way;
137
wire [WAYS-1:0]             data_hit_way;
138
wire [WAYS-1:0]             tag_wenable_way;
139
reg  [WAYS-1:0]             select_way = 'd0;
140
wire [WAYS-1:0]             next_way;
141
reg  [WAYS-1:0]             valid_bits_r = 'd0;
142
 
143
reg  [3:0]                  random_num = 4'hf;
144
 
145
wire [CACHE_ADDR_WIDTH-1:0] tag_address;
146
wire [TAG_WIDTH-1:0]        tag_wdata;
147
wire                        tag_wenable;
148
 
149
wire [CACHE_LINE_WIDTH-1:0] read_miss_wdata;
150
wire [CACHE_LINE_WIDTH-1:0] write_hit_wdata;
151
wire [CACHE_LINE_WIDTH-1:0] data_wdata;
152
wire [CACHE_ADDR_WIDTH-1:0] data_address;
153
wire [31:0]                 write_data_word;
154
 
155
wire                        hit;
156
wire                        read_miss;
157
wire                        write_miss;
158
wire                        write_hit;
159
 
160
reg  [31:0]                 miss_address = 'd0;
161
wire [CACHE_LINE_WIDTH-1:0] hit_rdata;
162
 
163
wire                        write_stall;
164
wire                        cache_busy_stall;
165
wire                        read_stall;
166
 
167
wire                        enable;
168
wire [CACHE_ADDR_WIDTH-1:0] address;
169
 
170
reg  [CACHE_LINE_WIDTH-1:0] wb_rdata_burst = 'd0;
171
reg                         wb_read_buf_valid = 'd0;
172
reg  [31:0]                 wb_read_buf_address = 'd0;
173
reg  [31:0]                 wb_read_buf_data = 'd0;
174
wire                        wb_read_buf_hit;
175
 
176
wire                        exclusive_access;
177
wire                        ex_read_hit;
178
reg                         ex_read_hit_r = 'd0;
179
reg  [WAYS-1:0]             ex_read_hit_way = 'd0;
180
reg  [CACHE_ADDR_WIDTH-1:0] ex_read_address;
181
wire                        ex_read_hit_clear;
182
wire                        ex_read_cache_busy;
183
 
184
genvar                      i;
185
 
186
// ======================================
187
// Address to use for cache access
188
// ======================================
189
// If currently stalled then the address for the next
190
// cycle will be the same as it is in the current cycle
191
//
192
assign address = i_core_stall ? i_address    [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
193
                                i_address_nxt[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] ;
194
 
195
// ======================================
196
// Outputs
197
// ======================================
198
assign o_read_data      = wb_read_buf_hit                              ? wb_read_buf_data   :
199
                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd0 ? hit_rdata [31:0]   :
200
                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd1 ? hit_rdata [63:32]  :
201
                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd2 ? hit_rdata [95:64]  :
202
                                                                         hit_rdata [127:96] ;
203
 
204
// Don't allow the cache to stall the wb i/f for an exclusive access
205
// The cache needs a couple of cycles to flush a potential copy of the exclusive
206
// address, but the wb can do the access in parallel. So there is no
207
// stall in the state CS_EX_DELETE, even though the cache is out of action. 
208
// This works fine as long as the wb is stalling the core
209
assign o_stall          = read_stall || write_stall || cache_busy_stall || ex_read_cache_busy;
210
 
211
assign o_wb_req        = (( read_miss || write_miss ) && c_state == CS_IDLE ) ||
212
                          c_state == CS_WRITE_HIT1;
213
 
214
 
215
// ======================================
216
// Cache State Machine
217
// ======================================
218
 
219
// Little State Machine to Flush Tag RAMS
220
always @ ( posedge i_clk )
221
    if ( i_cache_flush )
222
        begin
223 84 csantifort
        c_state     <= CS_INIT;
224 2 csantifort
        source_sel  <= 1'd1 << C_INIT;
225
        init_count  <= 'd0;
226 15 csantifort
        `ifdef A23_CACHE_DEBUG
227 2 csantifort
        `TB_DEBUG_MESSAGE
228
        $display("Cache Flush");
229
        `endif
230
        end
231
    else
232
        case ( c_state )
233
            CS_INIT :
234
                if ( init_count < CACHE_LINES [CACHE_ADDR_WIDTH:0] )
235
                    begin
236
                    init_count  <= init_count + 1'd1;
237
                    source_sel  <= 1'd1 << C_INIT;
238
                    end
239
                else
240
                    begin
241
                    source_sel  <= 1'd1 << C_CORE;
242
                    c_state     <= CS_TURN_AROUND;
243
                    end
244
 
245
             CS_IDLE :
246
                begin
247
                source_sel  <= 1'd1 << C_CORE;
248
 
249
                if ( ex_read_hit || ex_read_hit_r )
250
                    begin
251
                    select_way  <= data_hit_way | ex_read_hit_way;
252
                    c_state     <= CS_EX_DELETE;
253
                    source_sel  <= 1'd1 << C_INVA;
254
                    end
255
                else if ( read_miss )
256
                    begin
257
                    // wb read request asserted, wait for ack
258
                    if ( !i_wb_stall )
259
                        c_state <= CS_FILL1;
260
                    end
261
                else if ( write_hit )
262
                    c_state <= CS_WRITE_HIT1;
263
               end
264
 
265
 
266
             CS_FILL1 :
267
                begin
268
                // wb read request asserted, wait for ack
269
                if ( !i_wb_stall )
270
                    c_state <= CS_FILL2;
271
                end
272
 
273
 
274
             CS_FILL2 :
275
                // first read of burst of 4
276
                // wb read request asserted, wait for ack
277
                if ( !i_wb_stall )
278
                    c_state <= CS_FILL3;
279
 
280
 
281
             CS_FILL3 :
282
                // second read of burst of 4
283
                // wb read request asserted, wait for ack
284
                if ( !i_wb_stall )
285
                    c_state <= CS_FILL4;
286
 
287
 
288
             CS_FILL4 :
289
                // third read of burst of 4
290
                // wb read request asserted, wait for ack
291
                if ( !i_wb_stall )
292
                    begin
293
                    c_state     <= CS_FILL_COMPLETE;
294
                    source_sel  <= 1'd1 << C_FILL;
295
 
296
                    // Pick a way to write the cache update into
297
                    // Either pick one of the invalid caches, or if all are valid, then pick
298
                    // one randomly
299
 
300
                    select_way  <= next_way;
301
                    random_num  <= {random_num[2], random_num[1], random_num[0],
302
                                     random_num[3]^random_num[2]};
303
                    end
304
 
305
 
306
             // Write the read fetch data in this cycle
307
             CS_FILL_COMPLETE :
308
                // fourth read of burst of 4
309
                // wb read request asserted, wait for ack
310
                if ( !i_wb_stall )
311
                    begin
312
                    // Back to normal cache operations, but
313
                    // use physical address for first read as
314
                    // address moved before the stall was asserted for the read_miss
315
                    // However don't use it if its a non-cached address!
316
                    source_sel  <= 1'd1 << C_CORE;
317
                    c_state     <= CS_TURN_AROUND;
318
                    end
319
 
320
 
321
             // Ignore the tag read data in this cycle   
322
             // Wait 1 cycle to pre-read the cache and return to normal operation                 
323
             CS_TURN_AROUND :
324
                begin
325
                c_state     <= CS_IDLE;
326
                end
327
 
328
 
329
             // Flush the entry matching an exclusive access         
330
             CS_EX_DELETE:
331
                begin
332 15 csantifort
                `ifdef A23_CACHE_DEBUG
333 2 csantifort
                `TB_DEBUG_MESSAGE
334
                $display("Cache deleted Locked entry");
335
                `endif
336
                c_state    <= CS_TURN_AROUND;
337
                source_sel <= 1'd1 << C_CORE;
338
                end
339
 
340
 
341
             CS_WRITE_HIT1:
342
                begin
343
                // wait for an ack on the wb bus to complete the write
344
                if ( !i_wb_stall )
345
                    c_state     <= CS_IDLE;
346
 
347
                end
348
        endcase
349
 
350
 
351
// ======================================
352
// Capture WB Block Read - burst of 4 words
353
// ======================================
354
always @ ( posedge i_clk )
355
    if ( !i_wb_stall )
356
        wb_rdata_burst <= {i_wb_read_data, wb_rdata_burst[127:32]};
357
 
358
 
359
// ======================================
360
// WB Read Buffer
361
// ======================================
362
always @ ( posedge i_clk )
363
    begin
364
    if ( c_state == CS_FILL1 || c_state == CS_FILL2 ||
365
         c_state == CS_FILL3 || c_state == CS_FILL4 )
366
        begin
367
        if ( !i_wb_stall )
368
            begin
369
            wb_read_buf_valid   <= 1'd1;
370
            wb_read_buf_address <= i_wb_address;
371
            wb_read_buf_data    <= i_wb_read_data;
372
            end
373
        end
374
    else
375
        wb_read_buf_valid   <= 1'd0;
376
    end
377
 
378
 
379
// ======================================
380
// Miss Address
381
// ======================================
382
always @ ( posedge i_clk )
383
    if ( o_wb_req )
384
        miss_address <= i_address;
385
 
386
 
387
// ======================================
388
// Remember Read-Modify-Write Hit
389
// ======================================
390
assign ex_read_hit_clear = c_state == CS_EX_DELETE;
391
 
392
always @ ( posedge i_clk )
393
    if ( ex_read_hit_clear )
394
        begin
395
        ex_read_hit_r   <= 1'd0;
396
        ex_read_hit_way <= 'd0;
397
        end
398
    else if ( ex_read_hit )
399
        begin
400
 
401 15 csantifort
        `ifdef A23_CACHE_DEBUG
402 2 csantifort
            `TB_DEBUG_MESSAGE
403
            $display ("Exclusive access cache hit address 0x%08h", i_address);
404
        `endif
405
 
406
        ex_read_hit_r   <= 1'd1;
407
        ex_read_hit_way <= data_hit_way;
408
        end
409
    else if ( c_state == CS_FILL_COMPLETE && ex_read_hit_r )
410
        ex_read_hit_way <= select_way;
411
 
412
 
413
always @ (posedge i_clk)
414
    if ( ex_read_hit )
415
        ex_read_address <= i_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB];
416
 
417
 
418
assign tag_address      = source_sel[C_FILL] ? miss_address      [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
419
                          source_sel[C_INVA] ? ex_read_address                                       :
420
                          source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0]                      :
421
                          source_sel[C_CORE] ? address                                               :
422
                                               {CACHE_ADDR_WIDTH{1'd0}}                              ;
423
 
424
 
425
assign data_address     = write_hit          ? i_address   [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
426
                          source_sel[C_FILL] ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
427
                          source_sel[C_CORE] ? address                                         :
428
                                               {CACHE_ADDR_WIDTH{1'd0}}                        ;
429
 
430
 
431
assign tag_wdata        = source_sel[C_FILL] ? {1'd1, miss_address[31:TAG_ADDR32_LSB]} :
432
                                               {TAG_WIDTH{1'd0}}                       ;
433
 
434
 
435
    // Data comes in off the WB bus in wrap4 with the missed data word first
436
assign data_wdata       = write_hit && c_state == CS_IDLE ? write_hit_wdata : read_miss_wdata;
437
 
438
assign read_miss_wdata  = miss_address[3:2] == 2'd0 ? wb_rdata_burst                              :
439
                          miss_address[3:2] == 2'd1 ? { wb_rdata_burst[95:0], wb_rdata_burst[127:96] }:
440
                          miss_address[3:2] == 2'd2 ? { wb_rdata_burst[63:0], wb_rdata_burst[127:64] }:
441
                                                      { wb_rdata_burst[31:0], wb_rdata_burst[127:32] };
442
 
443
 
444
assign write_hit_wdata  = i_address[3:2] == 2'd0 ? {hit_rdata[127:32], write_data_word                   } :
445
                          i_address[3:2] == 2'd1 ? {hit_rdata[127:64], write_data_word, hit_rdata[31:0]  } :
446
                          i_address[3:2] == 2'd2 ? {hit_rdata[127:96], write_data_word, hit_rdata[63:0]  } :
447
                                                   {                   write_data_word, hit_rdata[95:0]  } ;
448
 
449
// Use Byte Enables
450
assign write_data_word  = i_byte_enable == 4'b0001 ? { o_read_data[31: 8], i_write_data[ 7: 0]                   } :
451
                          i_byte_enable == 4'b0010 ? { o_read_data[31:16], i_write_data[15: 8], o_read_data[ 7:0]} :
452
                          i_byte_enable == 4'b0100 ? { o_read_data[31:24], i_write_data[23:16], o_read_data[15:0]} :
453
                          i_byte_enable == 4'b1000 ? {                     i_write_data[31:24], o_read_data[23:0]} :
454
                          i_byte_enable == 4'b0011 ? { o_read_data[31:16], i_write_data[15: 0]                   } :
455
                          i_byte_enable == 4'b1100 ? {                     i_write_data[31:16], o_read_data[15:0]} :
456
                                                     i_write_data                                                  ;
457
 
458
 
459
assign tag_wenable      = source_sel[C_INVA] ? 1'd1  :
460
                          source_sel[C_FILL] ? 1'd1  :
461
                          source_sel[C_INIT] ? 1'd1  :
462
                          source_sel[C_CORE] ? 1'd0  :
463
                                               1'd0  ;
464
 
465
 
466
assign enable           = i_select && i_cache_enable;
467
 
468
assign exclusive_access = i_exclusive && i_cache_enable;
469
 
470
 
471
                          // the wb read buffer returns data directly from the wb bus to the
472
                          // core during a read miss operation
473
assign wb_read_buf_hit  = enable && wb_read_buf_address == i_address && wb_read_buf_valid;
474
 
475
assign hit              = |data_hit_way;
476
 
477
assign write_hit        = enable &&  i_write_enable && hit;
478
 
479
assign write_miss       = enable &&  i_write_enable && !hit && c_state != CS_WRITE_HIT1;
480
 
481
assign read_miss        = enable && !i_write_enable && !(hit || wb_read_buf_hit);
482
 
483
                          // Exclusive read hit
484
assign ex_read_hit      = exclusive_access && !i_write_enable && (hit || wb_read_buf_hit);
485
 
486
                          // Added to fix rare swap bug which occurs when the cache starts
487
                          // a fill just as the swap instruction starts to execute. The cache
488
                          // fails to check for a read hit on the swap read cycle.
489
                          // This signal stalls the core in that case until after the
490
                          // fill has completed.
491
assign ex_read_cache_busy = exclusive_access && !i_write_enable && c_state != CS_IDLE;
492
 
493
                          // Need to stall for a write miss to wait for the current wb 
494
                          // read miss access to complete. Also for a write hit, need 
495
                          // to stall for 1 cycle while the data cache is being written to
496
assign write_stall      = ( write_hit  && c_state != CS_WRITE_HIT1 ) ||
497
                          ( write_miss && ( c_state != CS_IDLE ) )   ||
498
                           i_wb_stall                                ;
499
 
500
assign read_stall       = read_miss;
501
 
502
                          // Core may or may not be trying to access cache memory during
503
                          // this phase of the read fetch. It could be doing e.g. a wb access
504
assign cache_busy_stall = ((c_state == CS_TURN_AROUND || c_state == CS_FILL1) && enable) ||
505
                           c_state == CS_INIT;
506
 
507
 
508
// ======================================
509
// Instantiate RAMS
510
// ======================================
511
 
512
generate
513
    for ( i=0; i<WAYS;i=i+1 ) begin : rams
514
 
515
        // Tag RAMs 
516
        `ifdef XILINX_SPARTAN6_FPGA
517
        xs6_sram_256x21_line_en
518
        `endif
519
 
520
        `ifdef XILINX_VIRTEX6_FPGA
521
        xv6_sram_256x21_line_en
522
        `endif
523
 
524
        `ifndef XILINX_FPGA
525
        generic_sram_line_en
526
        `endif
527
 
528
            #(
529 15 csantifort
            .DATA_WIDTH                 ( TAG_WIDTH             ),
530
            .INITIALIZE_TO_ZERO         ( 1                     ),
531
            .ADDRESS_WIDTH              ( CACHE_ADDR_WIDTH      ))
532 2 csantifort
        u_tag (
533
            .i_clk                      ( i_clk                 ),
534
            .i_write_data               ( tag_wdata             ),
535
            .i_write_enable             ( tag_wenable_way[i]    ),
536
            .i_address                  ( tag_address           ),
537
 
538
            .o_read_data                ( tag_rdata_way[i]      )
539
            );
540
 
541
        // Data RAMs 
542
        `ifdef XILINX_SPARTAN6_FPGA
543
        xs6_sram_256x128_byte_en
544
        `endif
545
 
546
        `ifdef XILINX_VIRTEX6_FPGA
547
        xv6_sram_256x128_byte_en
548
        `endif
549
 
550
        `ifndef XILINX_FPGA
551
        generic_sram_byte_en
552
        `endif
553
 
554
            #(
555
            .DATA_WIDTH    ( CACHE_LINE_WIDTH) ,
556
            .ADDRESS_WIDTH ( CACHE_ADDR_WIDTH) )
557
        u_data (
558
            .i_clk                      ( i_clk                         ),
559
            .i_write_data               ( data_wdata                    ),
560
            .i_write_enable             ( data_wenable_way[i]           ),
561
            .i_address                  ( data_address                  ),
562
            .i_byte_enable              ( {CACHE_LINE_WIDTH/8{1'd1}}    ),
563
            .o_read_data                ( data_rdata_way[i]             )
564
            );
565
 
566
 
567
        // Per tag-ram write-enable
568
        assign tag_wenable_way[i]  = tag_wenable && ( select_way[i] || source_sel[C_INIT] );
569
 
570
        // Per data-ram write-enable
571
        assign data_wenable_way[i] = (source_sel[C_FILL] && select_way[i]) ||
572
                                     (write_hit && data_hit_way[i] && c_state == CS_IDLE);
573
        // Per data-ram hit flag
574
        assign data_hit_way[i]     = tag_rdata_way[i][TAG_WIDTH-1] &&
575
                                     tag_rdata_way[i][TAG_ADDR_WIDTH-1:0] == i_address[31:TAG_ADDR32_LSB] &&
576
                                     c_state == CS_IDLE;
577
    end
578
endgenerate
579
 
580
 
581
// ======================================
582
// Register Valid Bits
583
// ======================================
584
generate
585
if ( WAYS == 2 ) begin : valid_bits_2ways
586
 
587
    always @ ( posedge i_clk )
588
        if ( c_state == CS_IDLE )
589
            valid_bits_r <= {tag_rdata_way[1][TAG_WIDTH-1],
590
                             tag_rdata_way[0][TAG_WIDTH-1]};
591
 
592
end
593
else if ( WAYS == 3 ) begin : valid_bits_3ways
594
 
595
    always @ ( posedge i_clk )
596
        if ( c_state == CS_IDLE )
597
            valid_bits_r <= {tag_rdata_way[2][TAG_WIDTH-1],
598
                             tag_rdata_way[1][TAG_WIDTH-1],
599
                             tag_rdata_way[0][TAG_WIDTH-1]};
600
 
601
end
602
else if ( WAYS == 4 ) begin : valid_bits_4ways
603
 
604
    always @ ( posedge i_clk )
605
        if ( c_state == CS_IDLE )
606
            valid_bits_r <= {tag_rdata_way[3][TAG_WIDTH-1],
607
                             tag_rdata_way[2][TAG_WIDTH-1],
608
                             tag_rdata_way[1][TAG_WIDTH-1],
609
                             tag_rdata_way[0][TAG_WIDTH-1]};
610
 
611
end
612
else begin : valid_bits_8ways
613
 
614
    always @ ( posedge i_clk )
615
        if ( c_state == CS_IDLE )
616
            valid_bits_r <= {tag_rdata_way[7][TAG_WIDTH-1],
617
                             tag_rdata_way[6][TAG_WIDTH-1],
618
                             tag_rdata_way[5][TAG_WIDTH-1],
619
                             tag_rdata_way[4][TAG_WIDTH-1],
620
                             tag_rdata_way[3][TAG_WIDTH-1],
621
                             tag_rdata_way[2][TAG_WIDTH-1],
622
                             tag_rdata_way[1][TAG_WIDTH-1],
623
                             tag_rdata_way[0][TAG_WIDTH-1]};
624
 
625
end
626
endgenerate
627
 
628
 
629
// ======================================
630
// Select read hit data
631
// ======================================
632
generate
633
if ( WAYS == 2 ) begin : read_data_2ways
634
 
635
    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
636
                          data_hit_way[1] ? data_rdata_way[1] :
637
                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
638
 
639
end
640
else if ( WAYS == 3 ) begin : read_data_3ways
641
 
642
    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
643
                          data_hit_way[1] ? data_rdata_way[1] :
644
                          data_hit_way[2] ? data_rdata_way[2] :
645
                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
646
 
647
end
648
else if ( WAYS == 4 ) begin : read_data_4ways
649
 
650
    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
651
                          data_hit_way[1] ? data_rdata_way[1] :
652
                          data_hit_way[2] ? data_rdata_way[2] :
653
                          data_hit_way[3] ? data_rdata_way[3] :
654
                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
655
 
656
end
657
else begin : read_data_8ways
658
 
659
    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
660
                          data_hit_way[1] ? data_rdata_way[1] :
661
                          data_hit_way[2] ? data_rdata_way[2] :
662
                          data_hit_way[3] ? data_rdata_way[3] :
663
                          data_hit_way[4] ? data_rdata_way[4] :
664
                          data_hit_way[5] ? data_rdata_way[5] :
665
                          data_hit_way[6] ? data_rdata_way[6] :
666
                          data_hit_way[7] ? data_rdata_way[7] :
667
                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
668
 
669
end
670
endgenerate
671
 
672
 
673
// ======================================
674
// Function to select the way to use
675
// for fills
676
// ======================================
677
generate
678
if ( WAYS == 2 ) begin : pick_way_2ways
679
 
680
    assign next_way = pick_way ( valid_bits_r, random_num );
681
 
682
    function [WAYS-1:0] pick_way;
683
    input [WAYS-1:0] valid_bits;
684
    input [3:0]      random_num;
685
    begin
686
        if (      valid_bits[0] == 1'd0 )
687
            // way 0 not occupied so use it
688
            pick_way     = 2'b01;
689
        else if ( valid_bits[1] == 1'd0 )
690
            // way 1 not occupied so use it
691
            pick_way     = 2'b10;
692
        else
693
            begin
694
            // All ways occupied so pick one randomly
695
            case (random_num[3:1])
696
                3'd0, 3'd3,
697
                3'd5, 3'd6: pick_way = 2'b10;
698
                default:    pick_way = 2'b01;
699
            endcase
700
            end
701
    end
702
    endfunction
703
 
704
end
705
else if ( WAYS == 3 ) begin : pick_way_3ways
706
 
707
    assign next_way = pick_way ( valid_bits_r, random_num );
708
 
709
    function [WAYS-1:0] pick_way;
710
    input [WAYS-1:0] valid_bits;
711
    input [3:0]      random_num;
712
    begin
713
        if (      valid_bits[0] == 1'd0 )
714
            // way 0 not occupied so use it
715
            pick_way     = 3'b001;
716
        else if ( valid_bits[1] == 1'd0 )
717
            // way 1 not occupied so use it
718
            pick_way     = 3'b010;
719
        else if ( valid_bits[2] == 1'd0 )
720
            // way 2 not occupied so use it
721
            pick_way     = 3'b100;
722
        else
723
            begin
724
            // All ways occupied so pick one randomly
725
            case (random_num[3:1])
726
                3'd0, 3'd1, 3'd2: pick_way = 3'b010;
727
                3'd2, 3'd3, 3'd4: pick_way = 3'b100;
728
                default:          pick_way = 3'b001;
729
            endcase
730
            end
731
    end
732
    endfunction
733
 
734
end
735
else if ( WAYS == 4 ) begin : pick_way_4ways
736
 
737
    assign next_way = pick_way ( valid_bits_r, random_num );
738
 
739
    function [WAYS-1:0] pick_way;
740
    input [WAYS-1:0] valid_bits;
741
    input [3:0]      random_num;
742
    begin
743
        if (      valid_bits[0] == 1'd0 )
744
            // way 0 not occupied so use it
745
            pick_way     = 4'b0001;
746
        else if ( valid_bits[1] == 1'd0 )
747
            // way 1 not occupied so use it
748
            pick_way     = 4'b0010;
749
        else if ( valid_bits[2] == 1'd0 )
750
            // way 2 not occupied so use it
751
            pick_way     = 4'b0100;
752
        else if ( valid_bits[3] == 1'd0 )
753
            // way 3 not occupied so use it
754
            pick_way     = 4'b1000;
755
        else
756
            begin
757
            // All ways occupied so pick one randomly
758
            case (random_num[3:1])
759
                3'd0, 3'd1: pick_way = 4'b0100;
760
                3'd2, 3'd3: pick_way = 4'b1000;
761
                3'd4, 3'd5: pick_way = 4'b0001;
762
                default:    pick_way = 4'b0010;
763
            endcase
764
            end
765
    end
766
    endfunction
767
 
768
end
769
else begin : pick_way_8ways
770
 
771
    assign next_way = pick_way ( valid_bits_r, random_num );
772
 
773
    function [WAYS-1:0] pick_way;
774
    input [WAYS-1:0] valid_bits;
775
    input [3:0]      random_num;
776
    begin
777
        if (      valid_bits[0] == 1'd0 )
778
            // way 0 not occupied so use it
779
            pick_way     = 8'b00000001;
780
        else if ( valid_bits[1] == 1'd0 )
781
            // way 1 not occupied so use it
782
            pick_way     = 8'b00000010;
783
        else if ( valid_bits[2] == 1'd0 )
784
            // way 2 not occupied so use it
785
            pick_way     = 8'b00000100;
786
        else if ( valid_bits[3] == 1'd0 )
787
            // way 3 not occupied so use it
788
            pick_way     = 8'b00001000;
789
        else if ( valid_bits[4] == 1'd0 )
790
            // way 3 not occupied so use it
791
            pick_way     = 8'b00010000;
792
        else if ( valid_bits[5] == 1'd0 )
793
            // way 3 not occupied so use it
794
            pick_way     = 8'b00100000;
795
        else if ( valid_bits[6] == 1'd0 )
796
            // way 3 not occupied so use it
797
            pick_way     = 8'b01000000;
798
        else if ( valid_bits[7] == 1'd0 )
799
            // way 3 not occupied so use it
800
            pick_way     = 8'b10000000;
801
        else
802
            begin
803
            // All ways occupied so pick one randomly
804
            case (random_num[3:1])
805
                3'd0:       pick_way = 8'b00010000;
806
                3'd1:       pick_way = 8'b00100000;
807
                3'd2:       pick_way = 8'b01000000;
808
                3'd3:       pick_way = 8'b10000000;
809
                3'd4:       pick_way = 8'b00000001;
810
                3'd5:       pick_way = 8'b00000010;
811
                3'd6:       pick_way = 8'b00000100;
812
                default:    pick_way = 8'b00001000;
813
            endcase
814
            end
815
    end
816
    endfunction
817
 
818
end
819
endgenerate
820
 
821
 
822
// ========================================================
823
// Debug WB bus - not synthesizable
824
// ========================================================
825
//synopsys translate_off
826
wire    [(6*8)-1:0]     xSOURCE_SEL;
827
wire    [(20*8)-1:0]    xC_STATE;
828
 
829
assign xSOURCE_SEL = source_sel[C_CORE]            ? "C_CORE"           :
830
                     source_sel[C_INIT]            ? "C_INIT"           :
831
                     source_sel[C_FILL]            ? "C_FILL"           :
832
                     source_sel[C_INVA]            ? "C_INVA"           :
833
                                                     "UNKNON"           ;
834
 
835
assign xC_STATE    = c_state == CS_INIT            ? "CS_INIT"          :
836
                     c_state == CS_IDLE            ? "CS_IDLE"          :
837
                     c_state == CS_FILL1           ? "CS_FILL1"         :
838
                     c_state == CS_FILL2           ? "CS_FILL2"         :
839
                     c_state == CS_FILL3           ? "CS_FILL3"         :
840
                     c_state == CS_FILL4           ? "CS_FILL4"         :
841
                     c_state == CS_FILL_COMPLETE   ? "CS_FILL_COMPLETE" :
842
                     c_state == CS_EX_DELETE       ? "CS_EX_DELETE"     :
843
                     c_state == CS_TURN_AROUND     ? "CS_TURN_AROUND"   :
844
                     c_state == CS_WRITE_HIT1      ? "CS_WRITE_HIT1"    :
845
                                                     "UNKNOWN"          ;
846
 
847
 
848
generate
849
if ( WAYS == 2 ) begin : check_hit_2ways
850
 
851
    always @( posedge i_clk )
852
        if ( (data_hit_way[0] + data_hit_way[1] ) > 4'd1 )
853
            begin
854
            `TB_ERROR_MESSAGE
855
            $display("Hit in more than one cache ways!");
856
            end
857
 
858
end
859
else if ( WAYS == 3 ) begin : check_hit_3ways
860
 
861
    always @( posedge i_clk )
862
        if ( (data_hit_way[0] + data_hit_way[1] + data_hit_way[2] ) > 4'd1 )
863
            begin
864
            `TB_ERROR_MESSAGE
865
            $display("Hit in more than one cache ways!");
866
            end
867
 
868
end
869
else if ( WAYS == 4 ) begin : check_hit_4ways
870
 
871
    always @( posedge i_clk )
872
        if ( (data_hit_way[0] + data_hit_way[1] +
873
              data_hit_way[2] + data_hit_way[3] ) > 4'd1 )
874
            begin
875
            `TB_ERROR_MESSAGE
876
            $display("Hit in more than one cache ways!");
877
            end
878
 
879
end
880
else if ( WAYS == 8 )  begin : check_hit_8ways
881
 
882
    always @( posedge i_clk )
883
        if ( (data_hit_way[0] + data_hit_way[1] +
884
              data_hit_way[2] + data_hit_way[3] +
885
              data_hit_way[4] + data_hit_way[5] +
886
              data_hit_way[6] + data_hit_way[7] ) > 4'd1 )
887
            begin
888
            `TB_ERROR_MESSAGE
889
            $display("Hit in more than one cache ways!");
890
            end
891
 
892
end
893
else begin : check_hit_nways
894
 
895
    initial
896
        begin
897
        `TB_ERROR_MESSAGE
898
        $display("Unsupported number of ways %0d", WAYS);
899 15 csantifort
        $display("Set A23_CACHE_WAYS in a23_config_defines.v to either 2,3,4 or 8");
900 2 csantifort
        end
901
 
902
end
903
endgenerate
904
 
905
//synopsys translate_on
906
 
907
endmodule
908
 

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