| 1 |
2 |
csantifort |
//////////////////////////////////////////////////////////////////
|
| 2 |
|
|
// //
|
| 3 |
|
|
// Amber 2 Core top-Level module //
|
| 4 |
|
|
// //
|
| 5 |
|
|
// This file is part of the Amber project //
|
| 6 |
|
|
// http://www.opencores.org/project,amber //
|
| 7 |
|
|
// //
|
| 8 |
|
|
// Description //
|
| 9 |
|
|
// Instantiates the core consisting of fetch, instruction //
|
| 10 |
|
|
// decode, execute, and co-processor. //
|
| 11 |
|
|
// //
|
| 12 |
|
|
// Author(s): //
|
| 13 |
|
|
// - Conor Santifort, csantifort.amber@gmail.com //
|
| 14 |
|
|
// //
|
| 15 |
|
|
//////////////////////////////////////////////////////////////////
|
| 16 |
|
|
// //
|
| 17 |
|
|
// Copyright (C) 2010 Authors and OPENCORES.ORG //
|
| 18 |
|
|
// //
|
| 19 |
|
|
// This source file may be used and distributed without //
|
| 20 |
|
|
// restriction provided that this copyright statement is not //
|
| 21 |
|
|
// removed from the file and that any derivative work contains //
|
| 22 |
|
|
// the original copyright notice and the associated disclaimer. //
|
| 23 |
|
|
// //
|
| 24 |
|
|
// This source file is free software; you can redistribute it //
|
| 25 |
|
|
// and/or modify it under the terms of the GNU Lesser General //
|
| 26 |
|
|
// Public License as published by the Free Software Foundation; //
|
| 27 |
|
|
// either version 2.1 of the License, or (at your option) any //
|
| 28 |
|
|
// later version. //
|
| 29 |
|
|
// //
|
| 30 |
|
|
// This source is distributed in the hope that it will be //
|
| 31 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
| 32 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
| 33 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
| 34 |
|
|
// details. //
|
| 35 |
|
|
// //
|
| 36 |
|
|
// You should have received a copy of the GNU Lesser General //
|
| 37 |
|
|
// Public License along with this source; if not, download it //
|
| 38 |
|
|
// from http://www.opencores.org/lgpl.shtml //
|
| 39 |
|
|
// //
|
| 40 |
|
|
//////////////////////////////////////////////////////////////////
|
| 41 |
|
|
|
| 42 |
|
|
|
| 43 |
15 |
csantifort |
module a23_core
|
| 44 |
2 |
csantifort |
(
|
| 45 |
|
|
input i_clk,
|
| 46 |
|
|
|
| 47 |
|
|
input i_irq, // Interrupt request, active high
|
| 48 |
|
|
input i_firq, // Fast Interrupt request, active high
|
| 49 |
|
|
|
| 50 |
|
|
input i_system_rdy, // Amber is stalled when this is low
|
| 51 |
|
|
|
| 52 |
|
|
// Wishbone Master I/F
|
| 53 |
|
|
output [31:0] o_wb_adr,
|
| 54 |
|
|
output [3:0] o_wb_sel,
|
| 55 |
|
|
output o_wb_we,
|
| 56 |
|
|
input [31:0] i_wb_dat,
|
| 57 |
|
|
output [31:0] o_wb_dat,
|
| 58 |
|
|
output o_wb_cyc,
|
| 59 |
|
|
output o_wb_stb,
|
| 60 |
|
|
input i_wb_ack,
|
| 61 |
|
|
input i_wb_err
|
| 62 |
|
|
|
| 63 |
|
|
);
|
| 64 |
|
|
|
| 65 |
|
|
wire [31:0] execute_address;
|
| 66 |
|
|
wire execute_address_valid;
|
| 67 |
|
|
wire [31:0] execute_address_nxt; // un-registered version of execute_address to the cache rams
|
| 68 |
|
|
wire [31:0] write_data;
|
| 69 |
|
|
wire write_enable;
|
| 70 |
|
|
wire [31:0] read_data;
|
| 71 |
|
|
wire priviledged;
|
| 72 |
|
|
wire exclusive_exec;
|
| 73 |
|
|
wire data_access_exec;
|
| 74 |
|
|
wire [3:0] byte_enable;
|
| 75 |
|
|
wire data_access; // high for data petch, low for instruction fetch
|
| 76 |
|
|
wire exclusive; // swap access
|
| 77 |
|
|
wire cache_enable; // Enabel the cache
|
| 78 |
|
|
wire cache_flush; // Flush the cache
|
| 79 |
|
|
wire [31:0] cacheable_area;
|
| 80 |
|
|
|
| 81 |
|
|
wire fetch_stall; // when this is asserted all registers in all 3 pipeline
|
| 82 |
|
|
// stages are held
|
| 83 |
|
|
// at their current values
|
| 84 |
|
|
wire [1:0] status_bits_mode;
|
| 85 |
|
|
wire status_bits_irq_mask;
|
| 86 |
|
|
wire status_bits_firq_mask;
|
| 87 |
|
|
wire status_bits_flags_wen;
|
| 88 |
|
|
wire status_bits_mode_wen;
|
| 89 |
|
|
wire status_bits_irq_mask_wen;
|
| 90 |
|
|
wire status_bits_firq_mask_wen;
|
| 91 |
|
|
wire [31:0] execute_status_bits;
|
| 92 |
|
|
|
| 93 |
|
|
wire [31:0] imm32;
|
| 94 |
|
|
wire [4:0] imm_shift_amount;
|
| 95 |
|
|
wire shift_imm_zero;
|
| 96 |
|
|
wire [3:0] condition;
|
| 97 |
|
|
wire [31:0] read_data_s2;
|
| 98 |
|
|
wire [4:0] read_data_alignment;
|
| 99 |
|
|
|
| 100 |
|
|
wire [3:0] rm_sel;
|
| 101 |
|
|
wire [3:0] rds_sel;
|
| 102 |
|
|
wire [3:0] rn_sel;
|
| 103 |
71 |
csantifort |
wire [3:0] rm_sel_nxt;
|
| 104 |
|
|
wire [3:0] rds_sel_nxt;
|
| 105 |
|
|
wire [3:0] rn_sel_nxt;
|
| 106 |
2 |
csantifort |
wire [1:0] barrel_shift_amount_sel;
|
| 107 |
|
|
wire [1:0] barrel_shift_data_sel;
|
| 108 |
|
|
wire [1:0] barrel_shift_function;
|
| 109 |
|
|
wire [8:0] alu_function;
|
| 110 |
|
|
wire [1:0] multiply_function;
|
| 111 |
|
|
wire [2:0] interrupt_vector_sel;
|
| 112 |
|
|
wire [3:0] address_sel;
|
| 113 |
|
|
wire [1:0] pc_sel;
|
| 114 |
|
|
wire [1:0] byte_enable_sel;
|
| 115 |
|
|
wire [2:0] status_bits_sel;
|
| 116 |
|
|
wire [2:0] reg_write_sel;
|
| 117 |
|
|
wire user_mode_regs_load;
|
| 118 |
|
|
wire user_mode_regs_store_nxt;
|
| 119 |
|
|
wire firq_not_user_mode;
|
| 120 |
|
|
|
| 121 |
|
|
wire write_data_wen;
|
| 122 |
|
|
wire copro_write_data_wen;
|
| 123 |
|
|
wire base_address_wen;
|
| 124 |
|
|
wire pc_wen;
|
| 125 |
|
|
wire [14:0] reg_bank_wen;
|
| 126 |
71 |
csantifort |
wire [3:0] reg_bank_wsel;
|
| 127 |
2 |
csantifort |
|
| 128 |
|
|
wire [2:0] copro_opcode1;
|
| 129 |
|
|
wire [2:0] copro_opcode2;
|
| 130 |
|
|
wire [3:0] copro_crn;
|
| 131 |
|
|
wire [3:0] copro_crm;
|
| 132 |
|
|
wire [3:0] copro_num;
|
| 133 |
|
|
wire [1:0] copro_operation;
|
| 134 |
|
|
wire [31:0] copro_read_data;
|
| 135 |
|
|
wire [31:0] copro_write_data;
|
| 136 |
|
|
wire multiply_done;
|
| 137 |
|
|
|
| 138 |
|
|
wire decode_fault;
|
| 139 |
|
|
wire iabt_trigger;
|
| 140 |
|
|
wire dabt_trigger;
|
| 141 |
|
|
|
| 142 |
|
|
wire [7:0] decode_fault_status;
|
| 143 |
|
|
wire [7:0] iabt_fault_status;
|
| 144 |
|
|
wire [7:0] dabt_fault_status;
|
| 145 |
|
|
|
| 146 |
|
|
wire [31:0] decode_fault_address;
|
| 147 |
|
|
wire [31:0] iabt_fault_address;
|
| 148 |
|
|
wire [31:0] dabt_fault_address;
|
| 149 |
|
|
|
| 150 |
|
|
wire adex;
|
| 151 |
|
|
|
| 152 |
|
|
|
| 153 |
|
|
// data abort has priority
|
| 154 |
|
|
assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status;
|
| 155 |
|
|
assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
|
| 156 |
|
|
assign decode_fault = dabt_trigger | iabt_trigger;
|
| 157 |
|
|
|
| 158 |
|
|
|
| 159 |
15 |
csantifort |
a23_fetch u_fetch (
|
| 160 |
2 |
csantifort |
.i_clk ( i_clk ),
|
| 161 |
|
|
|
| 162 |
|
|
.i_address ( {execute_address[31:2], 2'd0} ),
|
| 163 |
|
|
.i_address_valid ( execute_address_valid ),
|
| 164 |
|
|
.i_address_nxt ( execute_address_nxt ),
|
| 165 |
|
|
.i_write_data ( write_data ),
|
| 166 |
|
|
.i_write_enable ( write_enable ),
|
| 167 |
|
|
.o_read_data ( read_data ),
|
| 168 |
|
|
.i_priviledged ( priviledged ),
|
| 169 |
|
|
.i_byte_enable ( byte_enable ),
|
| 170 |
|
|
.i_data_access ( data_access ),
|
| 171 |
|
|
.i_exclusive ( exclusive ),
|
| 172 |
|
|
.i_cache_enable ( cache_enable ),
|
| 173 |
|
|
.i_cache_flush ( cache_flush ),
|
| 174 |
|
|
.i_cacheable_area ( cacheable_area ),
|
| 175 |
|
|
|
| 176 |
|
|
.i_system_rdy ( i_system_rdy ),
|
| 177 |
|
|
.o_fetch_stall ( fetch_stall ),
|
| 178 |
|
|
|
| 179 |
|
|
.o_wb_adr ( o_wb_adr ),
|
| 180 |
|
|
.o_wb_sel ( o_wb_sel ),
|
| 181 |
|
|
.o_wb_we ( o_wb_we ),
|
| 182 |
|
|
.i_wb_dat ( i_wb_dat ),
|
| 183 |
|
|
.o_wb_dat ( o_wb_dat ),
|
| 184 |
|
|
.o_wb_cyc ( o_wb_cyc ),
|
| 185 |
|
|
.o_wb_stb ( o_wb_stb ),
|
| 186 |
|
|
.i_wb_ack ( i_wb_ack ),
|
| 187 |
|
|
.i_wb_err ( i_wb_err )
|
| 188 |
|
|
);
|
| 189 |
|
|
|
| 190 |
|
|
|
| 191 |
15 |
csantifort |
a23_decode u_decode (
|
| 192 |
2 |
csantifort |
.i_clk ( i_clk ),
|
| 193 |
|
|
|
| 194 |
|
|
// Instruction fetch or data read signals
|
| 195 |
|
|
.i_read_data ( read_data ),
|
| 196 |
|
|
.i_execute_address ( execute_address ),
|
| 197 |
|
|
.i_adex ( adex ),
|
| 198 |
|
|
.i_iabt ( 1'd0 ),
|
| 199 |
|
|
.i_dabt ( 1'd0 ),
|
| 200 |
|
|
.i_abt_status ( 8'd0 ),
|
| 201 |
|
|
|
| 202 |
|
|
.o_read_data ( read_data_s2 ),
|
| 203 |
|
|
.o_read_data_alignment ( read_data_alignment ),
|
| 204 |
|
|
|
| 205 |
|
|
.i_irq ( i_irq ),
|
| 206 |
|
|
.i_firq ( i_firq ),
|
| 207 |
|
|
.i_fetch_stall ( fetch_stall ),
|
| 208 |
|
|
.i_execute_status_bits ( execute_status_bits ),
|
| 209 |
|
|
.i_multiply_done ( multiply_done ),
|
| 210 |
|
|
|
| 211 |
71 |
csantifort |
.o_status_bits_mode ( status_bits_mode ),
|
| 212 |
2 |
csantifort |
.o_status_bits_irq_mask ( status_bits_irq_mask ),
|
| 213 |
|
|
.o_status_bits_firq_mask ( status_bits_firq_mask ),
|
| 214 |
|
|
.o_imm32 ( imm32 ),
|
| 215 |
|
|
.o_imm_shift_amount ( imm_shift_amount ),
|
| 216 |
|
|
.o_shift_imm_zero ( shift_imm_zero ),
|
| 217 |
|
|
.o_condition ( condition ),
|
| 218 |
|
|
.o_exclusive_exec ( exclusive_exec ),
|
| 219 |
|
|
.o_data_access_exec ( data_access_exec ),
|
| 220 |
|
|
.o_rm_sel ( rm_sel ),
|
| 221 |
|
|
.o_rds_sel ( rds_sel ),
|
| 222 |
|
|
.o_rn_sel ( rn_sel ),
|
| 223 |
71 |
csantifort |
.o_rm_sel_nxt ( rm_sel_nxt ),
|
| 224 |
|
|
.o_rds_sel_nxt ( rds_sel_nxt ),
|
| 225 |
|
|
.o_rn_sel_nxt ( rn_sel_nxt ),
|
| 226 |
2 |
csantifort |
.o_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
|
| 227 |
|
|
.o_barrel_shift_data_sel ( barrel_shift_data_sel ),
|
| 228 |
|
|
.o_barrel_shift_function ( barrel_shift_function ),
|
| 229 |
|
|
.o_alu_function ( alu_function ),
|
| 230 |
|
|
.o_multiply_function ( multiply_function ),
|
| 231 |
|
|
.o_interrupt_vector_sel ( interrupt_vector_sel ),
|
| 232 |
|
|
.o_address_sel ( address_sel ),
|
| 233 |
|
|
.o_pc_sel ( pc_sel ),
|
| 234 |
|
|
.o_byte_enable_sel ( byte_enable_sel ),
|
| 235 |
|
|
.o_status_bits_sel ( status_bits_sel ),
|
| 236 |
|
|
.o_reg_write_sel ( reg_write_sel ),
|
| 237 |
|
|
.o_user_mode_regs_load ( user_mode_regs_load ),
|
| 238 |
|
|
.o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
|
| 239 |
|
|
.o_firq_not_user_mode ( firq_not_user_mode ),
|
| 240 |
|
|
.o_write_data_wen ( write_data_wen ),
|
| 241 |
|
|
.o_base_address_wen ( base_address_wen ),
|
| 242 |
|
|
.o_pc_wen ( pc_wen ),
|
| 243 |
|
|
.o_reg_bank_wen ( reg_bank_wen ),
|
| 244 |
71 |
csantifort |
.o_reg_bank_wsel ( reg_bank_wsel ),
|
| 245 |
2 |
csantifort |
.o_status_bits_flags_wen ( status_bits_flags_wen ),
|
| 246 |
|
|
.o_status_bits_mode_wen ( status_bits_mode_wen ),
|
| 247 |
|
|
.o_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
|
| 248 |
|
|
.o_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
|
| 249 |
|
|
|
| 250 |
|
|
.o_copro_opcode1 ( copro_opcode1 ),
|
| 251 |
|
|
.o_copro_opcode2 ( copro_opcode2 ),
|
| 252 |
|
|
.o_copro_crn ( copro_crn ),
|
| 253 |
|
|
.o_copro_crm ( copro_crm ),
|
| 254 |
|
|
.o_copro_num ( copro_num ),
|
| 255 |
|
|
.o_copro_operation ( copro_operation ),
|
| 256 |
|
|
.o_copro_write_data_wen ( copro_write_data_wen ),
|
| 257 |
|
|
|
| 258 |
|
|
.o_iabt_trigger ( iabt_trigger ),
|
| 259 |
|
|
.o_iabt_address ( iabt_fault_address ),
|
| 260 |
|
|
.o_iabt_status ( iabt_fault_status ),
|
| 261 |
|
|
.o_dabt_trigger ( dabt_trigger ),
|
| 262 |
|
|
.o_dabt_address ( dabt_fault_address ),
|
| 263 |
|
|
.o_dabt_status ( dabt_fault_status )
|
| 264 |
|
|
);
|
| 265 |
|
|
|
| 266 |
|
|
|
| 267 |
15 |
csantifort |
a23_execute u_execute (
|
| 268 |
2 |
csantifort |
.i_clk ( i_clk ),
|
| 269 |
|
|
|
| 270 |
|
|
.i_read_data ( read_data_s2 ),
|
| 271 |
|
|
.i_read_data_alignment ( read_data_alignment ),
|
| 272 |
|
|
.i_copro_read_data ( copro_read_data ),
|
| 273 |
|
|
|
| 274 |
|
|
.o_write_data ( write_data ),
|
| 275 |
|
|
.o_copro_write_data ( copro_write_data ),
|
| 276 |
|
|
.o_address ( execute_address ),
|
| 277 |
|
|
.o_address_valid ( execute_address_valid ),
|
| 278 |
|
|
.o_address_nxt ( execute_address_nxt ),
|
| 279 |
|
|
.o_adex ( adex ),
|
| 280 |
|
|
|
| 281 |
|
|
.o_byte_enable ( byte_enable ),
|
| 282 |
|
|
.o_data_access ( data_access ),
|
| 283 |
|
|
.o_write_enable ( write_enable ),
|
| 284 |
|
|
.o_exclusive ( exclusive ),
|
| 285 |
|
|
.o_priviledged ( priviledged ),
|
| 286 |
|
|
.o_status_bits ( execute_status_bits ),
|
| 287 |
|
|
.o_multiply_done ( multiply_done ),
|
| 288 |
|
|
|
| 289 |
|
|
.i_fetch_stall ( fetch_stall ),
|
| 290 |
|
|
.i_status_bits_mode ( status_bits_mode ),
|
| 291 |
|
|
.i_status_bits_irq_mask ( status_bits_irq_mask ),
|
| 292 |
|
|
.i_status_bits_firq_mask ( status_bits_firq_mask ),
|
| 293 |
|
|
.i_imm32 ( imm32 ),
|
| 294 |
|
|
.i_imm_shift_amount ( imm_shift_amount ),
|
| 295 |
|
|
.i_shift_imm_zero ( shift_imm_zero ),
|
| 296 |
|
|
.i_condition ( condition ),
|
| 297 |
|
|
.i_exclusive_exec ( exclusive_exec ),
|
| 298 |
|
|
.i_data_access_exec ( data_access_exec ),
|
| 299 |
|
|
.i_rm_sel ( rm_sel ),
|
| 300 |
|
|
.i_rds_sel ( rds_sel ),
|
| 301 |
|
|
.i_rn_sel ( rn_sel ),
|
| 302 |
71 |
csantifort |
.i_rm_sel_nxt ( rm_sel_nxt ),
|
| 303 |
|
|
.i_rds_sel_nxt ( rds_sel_nxt ),
|
| 304 |
|
|
.i_rn_sel_nxt ( rn_sel_nxt ),
|
| 305 |
2 |
csantifort |
.i_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
|
| 306 |
|
|
.i_barrel_shift_data_sel ( barrel_shift_data_sel ),
|
| 307 |
|
|
.i_barrel_shift_function ( barrel_shift_function ),
|
| 308 |
|
|
.i_alu_function ( alu_function ),
|
| 309 |
|
|
.i_multiply_function ( multiply_function ),
|
| 310 |
|
|
.i_interrupt_vector_sel ( interrupt_vector_sel ),
|
| 311 |
|
|
.i_address_sel ( address_sel ),
|
| 312 |
|
|
.i_pc_sel ( pc_sel ),
|
| 313 |
|
|
.i_byte_enable_sel ( byte_enable_sel ),
|
| 314 |
|
|
.i_status_bits_sel ( status_bits_sel ),
|
| 315 |
|
|
.i_reg_write_sel ( reg_write_sel ),
|
| 316 |
|
|
.i_user_mode_regs_load ( user_mode_regs_load ),
|
| 317 |
|
|
.i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
|
| 318 |
|
|
.i_firq_not_user_mode ( firq_not_user_mode ),
|
| 319 |
|
|
.i_write_data_wen ( write_data_wen ),
|
| 320 |
|
|
.i_base_address_wen ( base_address_wen ),
|
| 321 |
|
|
.i_pc_wen ( pc_wen ),
|
| 322 |
|
|
.i_reg_bank_wen ( reg_bank_wen ),
|
| 323 |
71 |
csantifort |
.i_reg_bank_wsel ( reg_bank_wsel ),
|
| 324 |
2 |
csantifort |
.i_status_bits_flags_wen ( status_bits_flags_wen ),
|
| 325 |
|
|
.i_status_bits_mode_wen ( status_bits_mode_wen ),
|
| 326 |
|
|
.i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
|
| 327 |
|
|
.i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
|
| 328 |
|
|
.i_copro_write_data_wen ( copro_write_data_wen )
|
| 329 |
|
|
);
|
| 330 |
|
|
|
| 331 |
|
|
|
| 332 |
15 |
csantifort |
a23_coprocessor u_coprocessor (
|
| 333 |
2 |
csantifort |
.i_clk ( i_clk ),
|
| 334 |
|
|
|
| 335 |
|
|
.i_fetch_stall ( fetch_stall ),
|
| 336 |
|
|
.i_copro_opcode1 ( copro_opcode1 ),
|
| 337 |
|
|
.i_copro_opcode2 ( copro_opcode2 ),
|
| 338 |
|
|
.i_copro_crn ( copro_crn ),
|
| 339 |
|
|
.i_copro_crm ( copro_crm ),
|
| 340 |
|
|
.i_copro_num ( copro_num ),
|
| 341 |
|
|
.i_copro_operation ( copro_operation ),
|
| 342 |
|
|
.i_copro_write_data ( copro_write_data ),
|
| 343 |
|
|
|
| 344 |
|
|
.i_fault ( decode_fault ),
|
| 345 |
|
|
.i_fault_status ( decode_fault_status ),
|
| 346 |
|
|
.i_fault_address ( decode_fault_address ),
|
| 347 |
|
|
|
| 348 |
|
|
.o_copro_read_data ( copro_read_data ),
|
| 349 |
|
|
.o_cache_enable ( cache_enable ),
|
| 350 |
|
|
.o_cache_flush ( cache_flush ),
|
| 351 |
|
|
.o_cacheable_area ( cacheable_area )
|
| 352 |
|
|
);
|
| 353 |
|
|
|
| 354 |
|
|
|
| 355 |
|
|
endmodule
|
| 356 |
|
|
|
