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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Decode stage of Amber 2 Core //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// This module is the most complex part of the Amber core //
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// It decodes and sequences all instructions and handles all //
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// interrupts //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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63 |
csantifort |
`include "global_defines.v"
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2 |
csantifort |
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44 |
15 |
csantifort |
module a23_decode
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2 |
csantifort |
(
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input i_clk,
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input [31:0] i_read_data,
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input i_fetch_stall, // stall all stages of the cpu at the same time
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input i_irq, // interrupt request
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input i_firq, // Fast interrupt request
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input i_dabt, // data abort interrupt request
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input i_iabt, // instruction pre-fetch abort flag
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input i_adex, // Address Exception
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input [31:0] i_execute_address, // Registered address output by execute stage
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// 2 LSBs of read address used for calculating
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// shift in LDRB ops
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input [7:0] i_abt_status, // Abort status
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input [31:0] i_execute_status_bits, // current status bits values in execute stage
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input i_multiply_done, // multiply unit is nearly done
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// --------------------------------------------------
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// Control signals to execute stage
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// --------------------------------------------------
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output reg [31:0] o_read_data = 1'd0,
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output reg [4:0] o_read_data_alignment = 1'd0, // 2 LSBs of read address used for calculating shift in LDRB ops
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output reg [31:0] o_imm32 = 'd0,
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output reg [4:0] o_imm_shift_amount = 'd0,
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output reg o_shift_imm_zero = 'd0,
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output reg [3:0] o_condition = 4'he, // 4'he = al
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output reg o_exclusive_exec = 'd0, // exclusive access request ( swap instruction )
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output reg o_data_access_exec = 'd0, // high means the memory access is a read
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// read or write, low for instruction
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output reg [1:0] o_status_bits_mode = 2'b11, // SVC
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output reg o_status_bits_irq_mask = 1'd1,
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output reg o_status_bits_firq_mask = 1'd1,
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output reg [3:0] o_rm_sel = 'd0,
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output reg [3:0] o_rds_sel = 'd0,
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output reg [3:0] o_rn_sel = 'd0,
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csantifort |
output [3:0] o_rm_sel_nxt,
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output [3:0] o_rds_sel_nxt,
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output [3:0] o_rn_sel_nxt,
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csantifort |
output reg [1:0] o_barrel_shift_amount_sel = 'd0,
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output reg [1:0] o_barrel_shift_data_sel = 'd0,
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output reg [1:0] o_barrel_shift_function = 'd0,
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output reg [8:0] o_alu_function = 'd0,
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output reg [1:0] o_multiply_function = 'd0,
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output reg [2:0] o_interrupt_vector_sel = 'd0,
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output reg [3:0] o_address_sel = 4'd2,
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output reg [1:0] o_pc_sel = 2'd2,
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output reg [1:0] o_byte_enable_sel = 'd0, // byte, halfword or word write
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output reg [2:0] o_status_bits_sel = 'd0,
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output reg [2:0] o_reg_write_sel,
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output reg o_user_mode_regs_load,
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output reg o_user_mode_regs_store_nxt,
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output reg o_firq_not_user_mode,
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output reg o_write_data_wen = 'd0,
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output reg o_base_address_wen = 'd0, // save LDM base address register
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// in case of data abort
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output reg o_pc_wen = 1'd1,
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output reg [14:0] o_reg_bank_wen = 'd0,
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csantifort |
output reg [3:0] o_reg_bank_wsel = 'd0,
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csantifort |
output reg o_status_bits_flags_wen = 'd0,
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output reg o_status_bits_mode_wen = 'd0,
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output reg o_status_bits_irq_mask_wen = 'd0,
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output reg o_status_bits_firq_mask_wen = 'd0,
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// --------------------------------------------------
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// Co-Processor interface
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// --------------------------------------------------
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output reg [2:0] o_copro_opcode1 = 'd0,
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output reg [2:0] o_copro_opcode2 = 'd0,
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output reg [3:0] o_copro_crn = 'd0,
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output reg [3:0] o_copro_crm = 'd0,
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output reg [3:0] o_copro_num = 'd0,
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output reg [1:0] o_copro_operation = 'd0, // 0 = no operation,
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// 1 = Move to Amber Core Register from Coprocessor
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// 2 = Move to Coprocessor from Amber Core Register
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output reg o_copro_write_data_wen = 'd0,
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output o_iabt_trigger,
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output [31:0] o_iabt_address,
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output [7:0] o_iabt_status,
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output o_dabt_trigger,
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output [31:0] o_dabt_address,
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output [7:0] o_dabt_status
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);
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csantifort |
`include "a23_localparams.v"
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`include "a23_functions.v"
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csantifort |
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localparam [4:0] RST_WAIT1 = 5'd0,
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RST_WAIT2 = 5'd1,
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INT_WAIT1 = 5'd2,
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INT_WAIT2 = 5'd3,
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EXECUTE = 5'd4,
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PRE_FETCH_EXEC = 5'd5, // Execute the Pre-Fetched Instruction
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MEM_WAIT1 = 5'd6, // conditionally decode current instruction, in case
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// previous instruction does not execute in S2
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MEM_WAIT2 = 5'd7,
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PC_STALL1 = 5'd8, // Program Counter altered
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// conditionally decude current instruction, in case
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// previous instruction does not execute in S2
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PC_STALL2 = 5'd9,
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MTRANS_EXEC1 = 5'd10,
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MTRANS_EXEC2 = 5'd11,
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MTRANS_EXEC3 = 5'd12,
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MTRANS_EXEC3B = 5'd13,
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MTRANS_EXEC4 = 5'd14,
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MTRANS5_ABORT = 5'd15,
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MULT_PROC1 = 5'd16, // first cycle, save pre fetch instruction
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MULT_PROC2 = 5'd17, // do multiplication
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MULT_STORE = 5'd19, // save RdLo
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MULT_ACCUMU = 5'd20, // Accumulate add lower 32 bits
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SWAP_WRITE = 5'd22,
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SWAP_WAIT1 = 5'd23,
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SWAP_WAIT2 = 5'd24,
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COPRO_WAIT = 5'd25;
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// ========================================================
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// Internal signals
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// ========================================================
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wire [31:0] instruction;
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wire instruction_iabt; // abort flag, follows the instruction
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wire instruction_adex; // address exception flag, follows the instruction
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wire [31:0] instruction_address; // instruction virtual address, follows
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// the instruction
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wire [7:0] instruction_iabt_status; // abort status, follows the instruction
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wire [1:0] instruction_sel;
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reg [3:0] type;
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wire [3:0] opcode;
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wire [7:0] imm8;
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wire [31:0] offset12;
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wire [31:0] offset24;
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wire [4:0] shift_imm;
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wire opcode_compare;
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wire mem_op;
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wire load_op;
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wire store_op;
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wire write_pc;
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wire immediate_shifter_operand;
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wire rds_use_rs;
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wire branch;
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wire mem_op_pre_indexed;
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wire mem_op_post_indexed;
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// Flop inputs
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wire [31:0] imm32_nxt;
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wire [4:0] imm_shift_amount_nxt;
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wire shift_imm_zero_nxt;
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wire [3:0] condition_nxt;
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reg exclusive_exec_nxt;
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reg data_access_exec_nxt;
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reg [1:0] barrel_shift_function_nxt;
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wire [8:0] alu_function_nxt;
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reg [1:0] multiply_function_nxt;
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reg [1:0] status_bits_mode_nxt;
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reg status_bits_irq_mask_nxt;
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reg status_bits_firq_mask_nxt;
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reg [1:0] barrel_shift_amount_sel_nxt;
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reg [1:0] barrel_shift_data_sel_nxt;
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reg [3:0] address_sel_nxt;
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reg [1:0] pc_sel_nxt;
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reg [1:0] byte_enable_sel_nxt;
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reg [2:0] status_bits_sel_nxt;
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reg [2:0] reg_write_sel_nxt;
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reg user_mode_regs_load_nxt;
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wire firq_not_user_mode_nxt;
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// ALU Function signals
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reg alu_swap_sel_nxt;
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reg alu_not_sel_nxt;
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reg [1:0] alu_cin_sel_nxt;
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reg alu_cout_sel_nxt;
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reg [3:0] alu_out_sel_nxt;
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reg write_data_wen_nxt;
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reg copro_write_data_wen_nxt;
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reg base_address_wen_nxt;
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reg pc_wen_nxt;
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71 |
csantifort |
reg [3:0] reg_bank_wsel_nxt;
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2 |
csantifort |
reg status_bits_flags_wen_nxt;
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reg status_bits_mode_wen_nxt;
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reg status_bits_irq_mask_wen_nxt;
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reg status_bits_firq_mask_wen_nxt;
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reg saved_current_instruction_wen; // saved load instruction
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reg pre_fetch_instruction_wen; // pre-fetch instruction
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reg [4:0] control_state = RST_WAIT1;
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reg [4:0] control_state_nxt;
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241 |
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242 |
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wire dabt;
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reg dabt_reg = 'd0;
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reg dabt_reg_d1;
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reg iabt_reg = 'd0;
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reg adex_reg = 'd0;
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reg [31:0] abt_address_reg = 'd0;
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reg [7:0] abt_status_reg = 'd0;
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reg [31:0] saved_current_instruction = 'd0;
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reg saved_current_instruction_iabt = 'd0; // access abort flag
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reg saved_current_instruction_adex = 'd0; // address exception
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reg [31:0] saved_current_instruction_address = 'd0; // virtual address of abort instruction
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reg [7:0] saved_current_instruction_iabt_status = 'd0; // status of abort instruction
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reg [31:0] pre_fetch_instruction = 'd0;
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255 |
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reg pre_fetch_instruction_iabt = 'd0; // access abort flag
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256 |
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reg pre_fetch_instruction_adex = 'd0; // address exception
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reg [31:0] pre_fetch_instruction_address = 'd0; // virtual address of abort instruction
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reg [7:0] pre_fetch_instruction_iabt_status = 'd0; // status of abort instruction
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259 |
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wire instruction_valid;
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wire instruction_execute;
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262 |
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263 |
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reg [3:0] mtrans_reg; // the current register being accessed as part of STM/LDM
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264 |
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reg [3:0] mtrans_reg_d1 = 'd0; // delayed by 1 period
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265 |
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reg [3:0] mtrans_reg_d2 = 'd0; // delayed by 2 periods
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266 |
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reg [31:0] mtrans_instruction_nxt;
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267 |
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268 |
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wire [31:0] mtrans_base_reg_change;
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269 |
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wire [4:0] mtrans_num_registers;
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270 |
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wire use_saved_current_instruction;
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271 |
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wire use_pre_fetch_instruction;
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272 |
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wire interrupt;
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273 |
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wire [1:0] interrupt_mode;
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274 |
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wire [2:0] next_interrupt;
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275 |
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reg irq = 'd0;
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276 |
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reg firq = 'd0;
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277 |
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wire firq_request;
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278 |
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wire irq_request;
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279 |
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wire swi_request;
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280 |
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wire und_request;
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281 |
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wire dabt_request;
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282 |
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reg [1:0] copro_operation_nxt;
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283 |
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reg mtrans_r15 = 'd0;
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284 |
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reg mtrans_r15_nxt;
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285 |
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reg restore_base_address = 'd0;
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286 |
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reg restore_base_address_nxt;
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287 |
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288 |
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wire regop_set_flags;
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289 |
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290 |
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291 |
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// ========================================================
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292 |
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// Instruction Abort and Data Abort outputs
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293 |
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// ========================================================
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294 |
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295 |
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assign o_iabt_trigger = instruction_iabt && o_status_bits_mode == SVC && control_state == INT_WAIT1;
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296 |
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assign o_iabt_address = instruction_address;
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297 |
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assign o_iabt_status = instruction_iabt_status;
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298 |
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299 |
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assign o_dabt_trigger = dabt_reg && !dabt_reg_d1;
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300 |
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assign o_dabt_address = abt_address_reg;
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301 |
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assign o_dabt_status = abt_status_reg;
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302 |
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303 |
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304 |
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// ========================================================
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305 |
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// Instruction Decode
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306 |
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// ========================================================
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307 |
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308 |
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// for instructions that take more than one cycle
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309 |
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// the instruction is saved in the 'saved_mem_instruction'
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310 |
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// register and then that register is used for the rest of
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311 |
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// the execution of the instruction.
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312 |
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// But if the instruction does not execute because of the
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313 |
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// condition, then need to select the next instruction to
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314 |
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// decode
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315 |
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assign use_saved_current_instruction = instruction_execute &&
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316 |
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( control_state == MEM_WAIT1 ||
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317 |
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control_state == MEM_WAIT2 ||
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318 |
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control_state == MTRANS_EXEC1 ||
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319 |
|
|
control_state == MTRANS_EXEC2 ||
|
320 |
|
|
control_state == MTRANS_EXEC3 ||
|
321 |
|
|
control_state == MTRANS_EXEC3B ||
|
322 |
|
|
control_state == MTRANS_EXEC4 ||
|
323 |
|
|
control_state == MTRANS5_ABORT ||
|
324 |
|
|
control_state == MULT_PROC1 ||
|
325 |
|
|
control_state == MULT_PROC2 ||
|
326 |
|
|
control_state == MULT_ACCUMU ||
|
327 |
|
|
control_state == MULT_STORE ||
|
328 |
|
|
control_state == INT_WAIT1 ||
|
329 |
|
|
control_state == INT_WAIT2 ||
|
330 |
|
|
control_state == SWAP_WRITE ||
|
331 |
|
|
control_state == SWAP_WAIT1 ||
|
332 |
|
|
control_state == SWAP_WAIT2 ||
|
333 |
|
|
control_state == COPRO_WAIT );
|
334 |
|
|
|
335 |
|
|
assign use_pre_fetch_instruction = control_state == PRE_FETCH_EXEC;
|
336 |
|
|
|
337 |
|
|
|
338 |
|
|
assign instruction_sel = use_saved_current_instruction ? 2'd1 : // saved_current_instruction
|
339 |
|
|
use_pre_fetch_instruction ? 2'd2 : // pre_fetch_instruction
|
340 |
|
|
2'd0 ; // o_read_data
|
341 |
|
|
|
342 |
|
|
assign instruction = instruction_sel == 2'd0 ? o_read_data :
|
343 |
|
|
instruction_sel == 2'd1 ? saved_current_instruction :
|
344 |
|
|
pre_fetch_instruction ;
|
345 |
|
|
|
346 |
|
|
// abort flag
|
347 |
|
|
assign instruction_iabt = instruction_sel == 2'd0 ? iabt_reg :
|
348 |
|
|
instruction_sel == 2'd1 ? saved_current_instruction_iabt :
|
349 |
|
|
pre_fetch_instruction_iabt ;
|
350 |
|
|
|
351 |
|
|
assign instruction_address = instruction_sel == 2'd0 ? abt_address_reg :
|
352 |
|
|
instruction_sel == 2'd1 ? saved_current_instruction_address :
|
353 |
|
|
pre_fetch_instruction_address ;
|
354 |
|
|
|
355 |
|
|
assign instruction_iabt_status = instruction_sel == 2'd0 ? abt_status_reg :
|
356 |
|
|
instruction_sel == 2'd1 ? saved_current_instruction_iabt_status :
|
357 |
|
|
pre_fetch_instruction_iabt_status ;
|
358 |
|
|
|
359 |
|
|
// instruction address exception
|
360 |
|
|
assign instruction_adex = instruction_sel == 2'd0 ? adex_reg :
|
361 |
|
|
instruction_sel == 2'd1 ? saved_current_instruction_adex :
|
362 |
|
|
pre_fetch_instruction_adex ;
|
363 |
|
|
|
364 |
|
|
// Instruction Decode - Order is important!
|
365 |
|
|
always @*
|
366 |
|
|
casez ({instruction[27:20], instruction[7:4]})
|
367 |
|
|
12'b00010?001001 : type = SWAP;
|
368 |
|
|
12'b000000??1001 : type = MULT;
|
369 |
|
|
12'b00?????????? : type = REGOP;
|
370 |
|
|
12'b01?????????? : type = TRANS;
|
371 |
|
|
12'b100????????? : type = MTRANS;
|
372 |
|
|
12'b101????????? : type = BRANCH;
|
373 |
|
|
12'b110????????? : type = CODTRANS;
|
374 |
|
|
12'b1110???????0 : type = COREGOP;
|
375 |
|
|
12'b1110???????1 : type = CORTRANS;
|
376 |
|
|
default: type = SWI;
|
377 |
|
|
endcase
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
// ========================================================
|
381 |
|
|
// Fixed fields within the instruction
|
382 |
|
|
// ========================================================
|
383 |
|
|
|
384 |
|
|
assign opcode = instruction[24:21];
|
385 |
|
|
assign condition_nxt = instruction[31:28];
|
386 |
|
|
|
387 |
71 |
csantifort |
assign o_rm_sel_nxt = instruction[3:0];
|
388 |
2 |
csantifort |
|
389 |
71 |
csantifort |
assign o_rn_sel_nxt = branch ? 4'd15 : // Use PC to calculate branch destination
|
390 |
2 |
csantifort |
instruction[19:16] ;
|
391 |
|
|
|
392 |
71 |
csantifort |
assign o_rds_sel_nxt = control_state == SWAP_WRITE ? instruction[3:0] : // Rm gets written out to memory
|
393 |
2 |
csantifort |
type == MTRANS ? mtrans_reg :
|
394 |
|
|
branch ? 4'd15 : // Update the PC
|
395 |
|
|
rds_use_rs ? instruction[11:8] :
|
396 |
|
|
instruction[15:12] ;
|
397 |
|
|
|
398 |
|
|
|
399 |
|
|
assign shift_imm = instruction[11:7];
|
400 |
|
|
assign offset12 = { 20'h0, instruction[11:0]};
|
401 |
|
|
assign offset24 = {{6{instruction[23]}}, instruction[23:0], 2'd0 }; // sign extend
|
402 |
|
|
assign imm8 = instruction[7:0];
|
403 |
|
|
|
404 |
|
|
assign immediate_shifter_operand = instruction[25];
|
405 |
|
|
assign rds_use_rs = (type == REGOP && !instruction[25] && instruction[4]) ||
|
406 |
|
|
(type == MULT &&
|
407 |
|
|
(control_state == MULT_PROC1 ||
|
408 |
|
|
control_state == MULT_PROC2 ||
|
409 |
|
|
instruction_valid && !interrupt )) ;
|
410 |
|
|
assign branch = type == BRANCH;
|
411 |
|
|
assign opcode_compare =
|
412 |
|
|
opcode == CMP ||
|
413 |
|
|
opcode == CMN ||
|
414 |
|
|
opcode == TEQ ||
|
415 |
|
|
opcode == TST ;
|
416 |
|
|
|
417 |
|
|
|
418 |
|
|
assign mem_op = type == TRANS;
|
419 |
|
|
assign load_op = mem_op && instruction[20];
|
420 |
|
|
assign store_op = mem_op && !instruction[20];
|
421 |
|
|
assign write_pc = pc_wen_nxt && pc_sel_nxt != 2'd0;
|
422 |
|
|
assign regop_set_flags = type == REGOP && instruction[20];
|
423 |
|
|
|
424 |
|
|
assign mem_op_pre_indexed = instruction[24] && instruction[21];
|
425 |
|
|
assign mem_op_post_indexed = !instruction[24];
|
426 |
|
|
|
427 |
|
|
assign imm32_nxt = // add 0 to Rm
|
428 |
|
|
type == MULT ? { 32'd0 } :
|
429 |
|
|
|
430 |
|
|
// 4 x number of registers
|
431 |
|
|
type == MTRANS ? { mtrans_base_reg_change } :
|
432 |
|
|
type == BRANCH ? { offset24 } :
|
433 |
|
|
type == TRANS ? { offset12 } :
|
434 |
|
|
instruction[11:8] == 4'h0 ? { 24'h0, imm8[7:0] } :
|
435 |
|
|
instruction[11:8] == 4'h1 ? { imm8[1:0], 24'h0, imm8[7:2] } :
|
436 |
|
|
instruction[11:8] == 4'h2 ? { imm8[3:0], 24'h0, imm8[7:4] } :
|
437 |
|
|
instruction[11:8] == 4'h3 ? { imm8[5:0], 24'h0, imm8[7:6] } :
|
438 |
|
|
instruction[11:8] == 4'h4 ? { imm8[7:0], 24'h0 } :
|
439 |
|
|
instruction[11:8] == 4'h5 ? { 2'h0, imm8[7:0], 22'h0 } :
|
440 |
|
|
instruction[11:8] == 4'h6 ? { 4'h0, imm8[7:0], 20'h0 } :
|
441 |
|
|
instruction[11:8] == 4'h7 ? { 6'h0, imm8[7:0], 18'h0 } :
|
442 |
|
|
instruction[11:8] == 4'h8 ? { 8'h0, imm8[7:0], 16'h0 } :
|
443 |
|
|
instruction[11:8] == 4'h9 ? { 10'h0, imm8[7:0], 14'h0 } :
|
444 |
|
|
instruction[11:8] == 4'ha ? { 12'h0, imm8[7:0], 12'h0 } :
|
445 |
|
|
instruction[11:8] == 4'hb ? { 14'h0, imm8[7:0], 10'h0 } :
|
446 |
|
|
instruction[11:8] == 4'hc ? { 16'h0, imm8[7:0], 8'h0 } :
|
447 |
|
|
instruction[11:8] == 4'hd ? { 18'h0, imm8[7:0], 6'h0 } :
|
448 |
|
|
instruction[11:8] == 4'he ? { 20'h0, imm8[7:0], 4'h0 } :
|
449 |
|
|
{ 22'h0, imm8[7:0], 2'h0 } ;
|
450 |
|
|
|
451 |
|
|
|
452 |
|
|
assign imm_shift_amount_nxt = shift_imm ;
|
453 |
|
|
|
454 |
|
|
// This signal is encoded in the decode stage because
|
455 |
|
|
// it is on the critical path in the execute stage
|
456 |
|
|
assign shift_imm_zero_nxt = imm_shift_amount_nxt == 5'd0 && // immediate amount = 0
|
457 |
|
|
barrel_shift_amount_sel_nxt == 2'd2; // shift immediate amount
|
458 |
|
|
|
459 |
|
|
assign alu_function_nxt = { alu_swap_sel_nxt,
|
460 |
|
|
alu_not_sel_nxt,
|
461 |
|
|
alu_cin_sel_nxt,
|
462 |
|
|
alu_cout_sel_nxt,
|
463 |
|
|
alu_out_sel_nxt };
|
464 |
|
|
|
465 |
|
|
|
466 |
|
|
// ========================================================
|
467 |
|
|
// MTRANS Operations
|
468 |
|
|
// ========================================================
|
469 |
|
|
|
470 |
|
|
// Bit 15 = r15
|
471 |
|
|
// Bit 0 = R0
|
472 |
|
|
// In LDM and STM instructions R0 is loaded or stored first
|
473 |
|
|
always @*
|
474 |
|
|
casez (instruction[15:0])
|
475 |
|
|
16'b???????????????1 : mtrans_reg = 4'h0 ;
|
476 |
|
|
16'b??????????????10 : mtrans_reg = 4'h1 ;
|
477 |
|
|
16'b?????????????100 : mtrans_reg = 4'h2 ;
|
478 |
|
|
16'b????????????1000 : mtrans_reg = 4'h3 ;
|
479 |
|
|
16'b???????????10000 : mtrans_reg = 4'h4 ;
|
480 |
|
|
16'b??????????100000 : mtrans_reg = 4'h5 ;
|
481 |
|
|
16'b?????????1000000 : mtrans_reg = 4'h6 ;
|
482 |
|
|
16'b????????10000000 : mtrans_reg = 4'h7 ;
|
483 |
|
|
16'b???????100000000 : mtrans_reg = 4'h8 ;
|
484 |
|
|
16'b??????1000000000 : mtrans_reg = 4'h9 ;
|
485 |
|
|
16'b?????10000000000 : mtrans_reg = 4'ha ;
|
486 |
|
|
16'b????100000000000 : mtrans_reg = 4'hb ;
|
487 |
|
|
16'b???1000000000000 : mtrans_reg = 4'hc ;
|
488 |
|
|
16'b??10000000000000 : mtrans_reg = 4'hd ;
|
489 |
|
|
16'b?100000000000000 : mtrans_reg = 4'he ;
|
490 |
|
|
default : mtrans_reg = 4'hf ;
|
491 |
|
|
endcase
|
492 |
|
|
|
493 |
|
|
always @*
|
494 |
|
|
casez (instruction[15:0])
|
495 |
|
|
16'b???????????????1 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 1], 1'd0};
|
496 |
|
|
16'b??????????????10 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 2], 2'd0};
|
497 |
|
|
16'b?????????????100 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 3], 3'd0};
|
498 |
|
|
16'b????????????1000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 4], 4'd0};
|
499 |
|
|
16'b???????????10000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 5], 5'd0};
|
500 |
|
|
16'b??????????100000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 6], 6'd0};
|
501 |
|
|
16'b?????????1000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 7], 7'd0};
|
502 |
|
|
16'b????????10000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 8], 8'd0};
|
503 |
|
|
16'b???????100000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 9], 9'd0};
|
504 |
|
|
16'b??????1000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:10], 10'd0};
|
505 |
|
|
16'b?????10000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:11], 11'd0};
|
506 |
|
|
16'b????100000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:12], 12'd0};
|
507 |
|
|
16'b???1000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:13], 13'd0};
|
508 |
|
|
16'b??10000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:14], 14'd0};
|
509 |
|
|
16'b?100000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15 ], 15'd0};
|
510 |
|
|
default : mtrans_instruction_nxt = {instruction[31:16], 16'd0};
|
511 |
|
|
endcase
|
512 |
|
|
|
513 |
|
|
|
514 |
|
|
// number of registers to be stored
|
515 |
|
|
assign mtrans_num_registers = {4'd0, instruction[15]} +
|
516 |
|
|
{4'd0, instruction[14]} +
|
517 |
|
|
{4'd0, instruction[13]} +
|
518 |
|
|
{4'd0, instruction[12]} +
|
519 |
|
|
{4'd0, instruction[11]} +
|
520 |
|
|
{4'd0, instruction[10]} +
|
521 |
|
|
{4'd0, instruction[ 9]} +
|
522 |
|
|
{4'd0, instruction[ 8]} +
|
523 |
|
|
{4'd0, instruction[ 7]} +
|
524 |
|
|
{4'd0, instruction[ 6]} +
|
525 |
|
|
{4'd0, instruction[ 5]} +
|
526 |
|
|
{4'd0, instruction[ 4]} +
|
527 |
|
|
{4'd0, instruction[ 3]} +
|
528 |
|
|
{4'd0, instruction[ 2]} +
|
529 |
|
|
{4'd0, instruction[ 1]} +
|
530 |
|
|
{4'd0, instruction[ 0]} ;
|
531 |
|
|
|
532 |
|
|
// 4 x number of registers to be stored
|
533 |
|
|
assign mtrans_base_reg_change = {25'd0, mtrans_num_registers, 2'd0};
|
534 |
|
|
|
535 |
|
|
// ========================================================
|
536 |
|
|
// Interrupts
|
537 |
|
|
// ========================================================
|
538 |
|
|
|
539 |
|
|
assign firq_request = firq && !i_execute_status_bits[26];
|
540 |
|
|
assign irq_request = irq && !i_execute_status_bits[27];
|
541 |
|
|
assign swi_request = type == SWI;
|
542 |
|
|
assign dabt_request = dabt_reg;
|
543 |
|
|
|
544 |
|
|
// copro15 and copro13 only supports reg trans opcodes
|
545 |
|
|
// all other opcodes involving co-processors cause an
|
546 |
|
|
// undefined instrution interrupt
|
547 |
|
|
assign und_request = type == CODTRANS ||
|
548 |
|
|
type == COREGOP ||
|
549 |
|
|
( type == CORTRANS && instruction[11:8] != 4'd15 );
|
550 |
|
|
|
551 |
|
|
|
552 |
|
|
// in order of priority !!
|
553 |
|
|
// Highest
|
554 |
|
|
// 1 Reset
|
555 |
|
|
// 2 Data Abort (including data TLB miss)
|
556 |
|
|
// 3 FIRQ
|
557 |
|
|
// 4 IRQ
|
558 |
|
|
// 5 Prefetch Abort (including prefetch TLB miss)
|
559 |
|
|
// 6 Undefined instruction, SWI
|
560 |
|
|
// Lowest
|
561 |
|
|
assign next_interrupt = dabt_request ? 3'd1 : // Data Abort
|
562 |
|
|
firq_request ? 3'd2 : // FIRQ
|
563 |
|
|
irq_request ? 3'd3 : // IRQ
|
564 |
|
|
instruction_adex ? 3'd4 : // Address Exception
|
565 |
|
|
instruction_iabt ? 3'd5 : // PreFetch Abort, only triggered
|
566 |
|
|
// if the instruction is used
|
567 |
|
|
und_request ? 3'd6 : // Undefined Instruction
|
568 |
|
|
swi_request ? 3'd7 : // SWI
|
569 |
|
|
3'd0 ; // none
|
570 |
|
|
|
571 |
|
|
// SWI and undefined instructions do not cause an interrupt in the decode
|
572 |
|
|
// stage. They only trigger interrupts if they arfe executed, so the
|
573 |
|
|
// interrupt is triggered if the execute condition is met in the execute stage
|
574 |
|
|
assign interrupt = next_interrupt != 3'd0 &&
|
575 |
|
|
next_interrupt != 3'd7 && // SWI
|
576 |
|
|
next_interrupt != 3'd6 ; // undefined interrupt
|
577 |
|
|
|
578 |
|
|
|
579 |
|
|
assign interrupt_mode = next_interrupt == 3'd2 ? FIRQ :
|
580 |
|
|
next_interrupt == 3'd3 ? IRQ :
|
581 |
|
|
next_interrupt == 3'd4 ? SVC :
|
582 |
|
|
next_interrupt == 3'd5 ? SVC :
|
583 |
|
|
next_interrupt == 3'd6 ? SVC :
|
584 |
|
|
next_interrupt == 3'd7 ? SVC :
|
585 |
|
|
next_interrupt == 3'd1 ? SVC :
|
586 |
|
|
USR ;
|
587 |
|
|
|
588 |
|
|
|
589 |
|
|
|
590 |
|
|
|
591 |
|
|
// ========================================================
|
592 |
|
|
// Generate control signals
|
593 |
|
|
// ========================================================
|
594 |
|
|
always @*
|
595 |
|
|
begin
|
596 |
|
|
// default mode
|
597 |
|
|
status_bits_mode_nxt = i_execute_status_bits[1:0]; // change to mode in execute stage get reflected
|
598 |
|
|
// back to this stage automatically
|
599 |
|
|
status_bits_irq_mask_nxt = o_status_bits_irq_mask;
|
600 |
|
|
status_bits_firq_mask_nxt = o_status_bits_firq_mask;
|
601 |
|
|
exclusive_exec_nxt = 1'd0;
|
602 |
|
|
data_access_exec_nxt = 1'd0;
|
603 |
|
|
copro_operation_nxt = 'd0;
|
604 |
|
|
|
605 |
|
|
// Save an instruction to use later
|
606 |
|
|
saved_current_instruction_wen = 1'd0;
|
607 |
|
|
pre_fetch_instruction_wen = 1'd0;
|
608 |
|
|
mtrans_r15_nxt = mtrans_r15;
|
609 |
|
|
restore_base_address_nxt = restore_base_address;
|
610 |
|
|
|
611 |
|
|
// default Mux Select values
|
612 |
|
|
barrel_shift_amount_sel_nxt = 'd0; // don't shift the input
|
613 |
|
|
barrel_shift_data_sel_nxt = 'd0; // immediate value
|
614 |
|
|
barrel_shift_function_nxt = 'd0;
|
615 |
|
|
multiply_function_nxt = 'd0;
|
616 |
|
|
address_sel_nxt = 'd0;
|
617 |
|
|
pc_sel_nxt = 'd0;
|
618 |
|
|
byte_enable_sel_nxt = 'd0;
|
619 |
|
|
status_bits_sel_nxt = 'd0;
|
620 |
|
|
reg_write_sel_nxt = 'd0;
|
621 |
71 |
csantifort |
user_mode_regs_load_nxt = 'd0;
|
622 |
2 |
csantifort |
o_user_mode_regs_store_nxt = 'd0;
|
623 |
|
|
|
624 |
|
|
// ALU Muxes
|
625 |
|
|
alu_swap_sel_nxt = 'd0;
|
626 |
|
|
alu_not_sel_nxt = 'd0;
|
627 |
|
|
alu_cin_sel_nxt = 'd0;
|
628 |
|
|
alu_cout_sel_nxt = 'd0;
|
629 |
|
|
alu_out_sel_nxt = 'd0;
|
630 |
|
|
|
631 |
|
|
// default Flop Write Enable values
|
632 |
|
|
write_data_wen_nxt = 'd0;
|
633 |
|
|
copro_write_data_wen_nxt = 'd0;
|
634 |
|
|
base_address_wen_nxt = 'd0;
|
635 |
|
|
pc_wen_nxt = 'd1;
|
636 |
71 |
csantifort |
reg_bank_wsel_nxt = 'hF; // Don't select any
|
637 |
2 |
csantifort |
status_bits_flags_wen_nxt = 'd0;
|
638 |
|
|
status_bits_mode_wen_nxt = 'd0;
|
639 |
|
|
status_bits_irq_mask_wen_nxt = 'd0;
|
640 |
|
|
status_bits_firq_mask_wen_nxt = 'd0;
|
641 |
|
|
|
642 |
|
|
if ( instruction_valid && !interrupt )
|
643 |
|
|
begin
|
644 |
|
|
if ( type == REGOP )
|
645 |
|
|
begin
|
646 |
|
|
if ( !opcode_compare )
|
647 |
|
|
begin
|
648 |
|
|
// Check is the load destination is the PC
|
649 |
|
|
if (instruction[15:12] == 4'd15)
|
650 |
|
|
begin
|
651 |
|
|
pc_sel_nxt = 2'd1; // alu_out
|
652 |
|
|
address_sel_nxt = 4'd1; // alu_out
|
653 |
|
|
end
|
654 |
|
|
else
|
655 |
71 |
csantifort |
reg_bank_wsel_nxt = instruction[15:12];
|
656 |
2 |
csantifort |
end
|
657 |
|
|
|
658 |
|
|
if ( !immediate_shifter_operand )
|
659 |
|
|
barrel_shift_function_nxt = instruction[6:5];
|
660 |
|
|
|
661 |
|
|
if ( !immediate_shifter_operand )
|
662 |
|
|
barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
|
663 |
|
|
|
664 |
|
|
if ( !immediate_shifter_operand && instruction[4] )
|
665 |
|
|
barrel_shift_amount_sel_nxt = 2'd1; // Shift amount from Rs registter
|
666 |
|
|
|
667 |
|
|
if ( !immediate_shifter_operand && !instruction[4] )
|
668 |
|
|
barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount
|
669 |
|
|
|
670 |
|
|
if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD
|
671 |
|
|
begin
|
672 |
|
|
alu_out_sel_nxt = 4'd1; // Add
|
673 |
|
|
end
|
674 |
|
|
|
675 |
|
|
if ( opcode == ADC ) // Add with Carry
|
676 |
|
|
begin
|
677 |
|
|
alu_out_sel_nxt = 4'd1; // Add
|
678 |
|
|
alu_cin_sel_nxt = 2'd2; // carry in from status_bits
|
679 |
|
|
end
|
680 |
|
|
|
681 |
|
|
if ( opcode == SUB || opcode == CMP ) // Subtract
|
682 |
|
|
begin
|
683 |
|
|
alu_out_sel_nxt = 4'd1; // Add
|
684 |
|
|
alu_cin_sel_nxt = 2'd1; // cin = 1
|
685 |
|
|
alu_not_sel_nxt = 1'd1; // invert B
|
686 |
|
|
end
|
687 |
|
|
|
688 |
|
|
// SBC (Subtract with Carry) subtracts the value of its
|
689 |
|
|
// second operand and the value of NOT(Carry flag) from
|
690 |
|
|
// the value of its first operand.
|
691 |
|
|
// Rd = Rn - shifter_operand - NOT(C Flag)
|
692 |
|
|
if ( opcode == SBC ) // Subtract with Carry
|
693 |
|
|
begin
|
694 |
|
|
alu_out_sel_nxt = 4'd1; // Add
|
695 |
|
|
alu_cin_sel_nxt = 2'd2; // carry in from status_bits
|
696 |
|
|
alu_not_sel_nxt = 1'd1; // invert B
|
697 |
|
|
end
|
698 |
|
|
|
699 |
|
|
if ( opcode == RSB ) // Reverse Subtract
|
700 |
|
|
begin
|
701 |
|
|
alu_out_sel_nxt = 4'd1; // Add
|
702 |
|
|
alu_cin_sel_nxt = 2'd1; // cin = 1
|
703 |
|
|
alu_not_sel_nxt = 1'd1; // invert B
|
704 |
|
|
alu_swap_sel_nxt = 1'd1; // swap A and B
|
705 |
|
|
end
|
706 |
|
|
|
707 |
|
|
if ( opcode == RSC ) // Reverse Subtract with carry
|
708 |
|
|
begin
|
709 |
|
|
alu_out_sel_nxt = 4'd1; // Add
|
710 |
|
|
alu_cin_sel_nxt = 2'd2; // carry in from status_bits
|
711 |
|
|
alu_not_sel_nxt = 1'd1; // invert B
|
712 |
|
|
alu_swap_sel_nxt = 1'd1; // swap A and B
|
713 |
|
|
end
|
714 |
|
|
|
715 |
|
|
if ( opcode == AND || opcode == TST ) // Logical AND, Test (using AND operator)
|
716 |
|
|
begin
|
717 |
|
|
alu_out_sel_nxt = 4'd8; // AND
|
718 |
|
|
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
|
719 |
|
|
end
|
720 |
|
|
|
721 |
|
|
if ( opcode == EOR || opcode == TEQ ) // Logical Exclusive OR, Test Equivalence (using EOR operator)
|
722 |
|
|
begin
|
723 |
|
|
alu_out_sel_nxt = 4'd6; // XOR
|
724 |
|
|
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
|
725 |
|
|
end
|
726 |
|
|
|
727 |
|
|
if ( opcode == ORR )
|
728 |
|
|
begin
|
729 |
|
|
alu_out_sel_nxt = 4'd7; // OR
|
730 |
|
|
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
|
731 |
|
|
end
|
732 |
|
|
|
733 |
|
|
if ( opcode == BIC ) // Bit Clear (using AND & NOT operators)
|
734 |
|
|
begin
|
735 |
|
|
alu_out_sel_nxt = 4'd8; // AND
|
736 |
|
|
alu_not_sel_nxt = 1'd1; // invert B
|
737 |
|
|
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
|
738 |
|
|
end
|
739 |
|
|
|
740 |
|
|
if ( opcode == MOV ) // Move
|
741 |
|
|
begin
|
742 |
|
|
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
|
743 |
|
|
end
|
744 |
|
|
|
745 |
|
|
if ( opcode == MVN ) // Move NOT
|
746 |
|
|
begin
|
747 |
|
|
alu_not_sel_nxt = 1'd1; // invert B
|
748 |
|
|
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
|
749 |
|
|
end
|
750 |
|
|
end
|
751 |
|
|
|
752 |
|
|
// Load & Store instructions
|
753 |
|
|
if ( mem_op )
|
754 |
|
|
begin
|
755 |
|
|
saved_current_instruction_wen = 1'd1; // Save the memory access instruction to refer back to later
|
756 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
757 |
|
|
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
|
758 |
|
|
// rather than an instruction fetch
|
759 |
|
|
alu_out_sel_nxt = 4'd1; // Add
|
760 |
|
|
|
761 |
|
|
if ( !instruction[23] ) // U: Subtract offset
|
762 |
|
|
begin
|
763 |
|
|
alu_cin_sel_nxt = 2'd1; // cin = 1
|
764 |
|
|
alu_not_sel_nxt = 1'd1; // invert B
|
765 |
|
|
end
|
766 |
|
|
|
767 |
|
|
if ( store_op )
|
768 |
|
|
begin
|
769 |
|
|
write_data_wen_nxt = 1'd1;
|
770 |
|
|
if ( type == TRANS && instruction[22] )
|
771 |
|
|
byte_enable_sel_nxt = 2'd1; // Save byte
|
772 |
|
|
end
|
773 |
|
|
|
774 |
|
|
// need to update the register holding the address ?
|
775 |
|
|
// This is Rn bits [19:16]
|
776 |
|
|
if ( mem_op_pre_indexed || mem_op_post_indexed )
|
777 |
|
|
begin
|
778 |
|
|
// Check is the load destination is the PC
|
779 |
71 |
csantifort |
if ( o_rn_sel_nxt == 4'd15 )
|
780 |
2 |
csantifort |
pc_sel_nxt = 2'd1;
|
781 |
|
|
else
|
782 |
71 |
csantifort |
reg_bank_wsel_nxt = o_rn_sel_nxt;
|
783 |
2 |
csantifort |
end
|
784 |
|
|
|
785 |
|
|
// if post-indexed, then use Rn rather than ALU output, as address
|
786 |
|
|
if ( mem_op_post_indexed )
|
787 |
|
|
address_sel_nxt = 4'd4; // Rn
|
788 |
|
|
else
|
789 |
|
|
address_sel_nxt = 4'd1; // alu out
|
790 |
|
|
|
791 |
|
|
if ( instruction[25] && type == TRANS )
|
792 |
|
|
barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
|
793 |
|
|
|
794 |
|
|
if ( type == TRANS && instruction[25] && shift_imm != 5'd0 )
|
795 |
|
|
begin
|
796 |
|
|
barrel_shift_function_nxt = instruction[6:5];
|
797 |
|
|
barrel_shift_amount_sel_nxt = 2'd2; // imm_shift_amount
|
798 |
|
|
end
|
799 |
|
|
end
|
800 |
|
|
|
801 |
|
|
if ( type == BRANCH )
|
802 |
|
|
begin
|
803 |
|
|
pc_sel_nxt = 2'd1; // alu_out
|
804 |
|
|
address_sel_nxt = 4'd1; // alu_out
|
805 |
|
|
alu_out_sel_nxt = 4'd1; // Add
|
806 |
|
|
|
807 |
|
|
if ( instruction[24] ) // Link
|
808 |
|
|
begin
|
809 |
71 |
csantifort |
reg_bank_wsel_nxt = 4'd14; // Save PC to LR
|
810 |
2 |
csantifort |
reg_write_sel_nxt = 3'd1; // pc - 32'd4
|
811 |
|
|
end
|
812 |
|
|
end
|
813 |
|
|
|
814 |
|
|
if ( type == MTRANS )
|
815 |
|
|
begin
|
816 |
|
|
saved_current_instruction_wen = 1'd1; // Save the memory access instruction to refer back to later
|
817 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
818 |
|
|
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
|
819 |
|
|
// rather than an instruction fetch
|
820 |
|
|
alu_out_sel_nxt = 4'd1; // Add
|
821 |
|
|
mtrans_r15_nxt = instruction[15]; // load or save r15 ?
|
822 |
|
|
base_address_wen_nxt = 1'd1; // Save the value of the register used for the base address,
|
823 |
|
|
// in case of a data abort, and need to restore the value
|
824 |
|
|
|
825 |
|
|
// The spec says -
|
826 |
|
|
// If the instruction would have overwritten the base with data
|
827 |
|
|
// (that is, it has the base in the transfer list), the overwriting is prevented.
|
828 |
|
|
// This is true even when the abort occurs after the base word gets loaded
|
829 |
|
|
restore_base_address_nxt = instruction[20] &&
|
830 |
|
|
(instruction[15:0] & (1'd1 << instruction[19:16]));
|
831 |
|
|
|
832 |
|
|
// Increment or Decrement
|
833 |
|
|
if ( instruction[23] ) // increment
|
834 |
|
|
begin
|
835 |
|
|
if ( instruction[24] ) // increment before
|
836 |
|
|
address_sel_nxt = 4'd7; // Rn + 4
|
837 |
|
|
else
|
838 |
|
|
address_sel_nxt = 4'd4; // Rn
|
839 |
|
|
end
|
840 |
|
|
else // decrement
|
841 |
|
|
begin
|
842 |
|
|
alu_cin_sel_nxt = 2'd1; // cin = 1
|
843 |
|
|
alu_not_sel_nxt = 1'd1; // invert B
|
844 |
|
|
if ( !instruction[24] ) // decrement after
|
845 |
|
|
address_sel_nxt = 4'd6; // alu out + 4
|
846 |
|
|
else
|
847 |
|
|
address_sel_nxt = 4'd1; // alu out
|
848 |
|
|
end
|
849 |
|
|
|
850 |
|
|
// Load or store ?
|
851 |
|
|
if ( !instruction[20] ) // Store
|
852 |
|
|
write_data_wen_nxt = 1'd1;
|
853 |
|
|
|
854 |
|
|
// LDM: load into user mode registers, when in priviledged mode
|
855 |
|
|
// DOnt use mtrans_r15 here because its not loaded yet
|
856 |
|
|
if ( {instruction[22:20],instruction[15]} == 4'b1010 )
|
857 |
|
|
user_mode_regs_load_nxt = 1'd1;
|
858 |
|
|
|
859 |
|
|
// SDM: store the user mode registers, when in priviledged mode
|
860 |
|
|
if ( {instruction[22:20]} == 3'b100 )
|
861 |
|
|
o_user_mode_regs_store_nxt = 1'd1;
|
862 |
|
|
|
863 |
|
|
// update the base register ?
|
864 |
|
|
if ( instruction[21] ) // the W bit
|
865 |
71 |
csantifort |
reg_bank_wsel_nxt = o_rn_sel_nxt;
|
866 |
2 |
csantifort |
end
|
867 |
|
|
|
868 |
|
|
|
869 |
|
|
if ( type == MULT )
|
870 |
|
|
begin
|
871 |
|
|
multiply_function_nxt[0] = 1'd1; // set enable
|
872 |
|
|
// some bits can be changed just below
|
873 |
|
|
saved_current_instruction_wen = 1'd1; // Save the Multiply instruction to
|
874 |
|
|
// refer back to later
|
875 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
876 |
|
|
|
877 |
|
|
if ( instruction[21] )
|
878 |
|
|
multiply_function_nxt[1] = 1'd1; // accumulate
|
879 |
|
|
end
|
880 |
|
|
|
881 |
|
|
|
882 |
|
|
// swp - do read part first
|
883 |
|
|
if ( type == SWAP )
|
884 |
|
|
begin
|
885 |
|
|
saved_current_instruction_wen = 1'd1; // Save the memory access instruction to refer back to later
|
886 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
887 |
|
|
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
|
888 |
|
|
// rather than an instruction fetch
|
889 |
|
|
barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
|
890 |
|
|
address_sel_nxt = 4'd4; // Rn
|
891 |
|
|
exclusive_exec_nxt = 1'd1; // signal an exclusive access
|
892 |
|
|
end
|
893 |
|
|
|
894 |
|
|
|
895 |
|
|
// mcr & mrc - takes two cycles
|
896 |
|
|
if ( type == CORTRANS && !und_request )
|
897 |
|
|
begin
|
898 |
|
|
saved_current_instruction_wen = 1'd1; // Save the memory access instruction to refer back to later
|
899 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
900 |
|
|
address_sel_nxt = 4'd3; // pc (not pc + 4)
|
901 |
|
|
|
902 |
|
|
if ( instruction[20] ) // MRC
|
903 |
|
|
copro_operation_nxt = 2'd1; // Register transfer from Co-Processor
|
904 |
|
|
else // MCR
|
905 |
|
|
begin
|
906 |
|
|
// Don't enable operation to Co-Processor until next period
|
907 |
|
|
// So it gets the Rd value from the execution stage at the same time
|
908 |
|
|
copro_operation_nxt = 2'd0;
|
909 |
|
|
copro_write_data_wen_nxt = 1'd1; // Rd register value to co-processor
|
910 |
|
|
end
|
911 |
|
|
end
|
912 |
|
|
|
913 |
|
|
|
914 |
|
|
if ( type == SWI || und_request )
|
915 |
|
|
begin
|
916 |
|
|
// save address of next instruction to Supervisor Mode LR
|
917 |
|
|
reg_write_sel_nxt = 3'd1; // pc -4
|
918 |
71 |
csantifort |
reg_bank_wsel_nxt = 4'd14; // LR
|
919 |
2 |
csantifort |
|
920 |
|
|
address_sel_nxt = 4'd2; // interrupt_vector
|
921 |
|
|
pc_sel_nxt = 2'd2; // interrupt_vector
|
922 |
|
|
|
923 |
|
|
status_bits_mode_nxt = interrupt_mode; // e.g. Supervisor mode
|
924 |
|
|
status_bits_mode_wen_nxt = 1'd1;
|
925 |
|
|
|
926 |
|
|
// disable normal interrupts
|
927 |
|
|
status_bits_irq_mask_nxt = 1'd1;
|
928 |
|
|
status_bits_irq_mask_wen_nxt = 1'd1;
|
929 |
|
|
end
|
930 |
|
|
|
931 |
|
|
|
932 |
|
|
if ( regop_set_flags )
|
933 |
|
|
begin
|
934 |
|
|
status_bits_flags_wen_nxt = 1'd1;
|
935 |
|
|
|
936 |
|
|
// If <Rd> is r15, the ALU output is copied to the Status Bits.
|
937 |
|
|
// Not allowed to use r15 for mul or lma instructions
|
938 |
|
|
if ( instruction[15:12] == 4'd15 )
|
939 |
|
|
begin
|
940 |
|
|
status_bits_sel_nxt = 3'd1; // alu out
|
941 |
|
|
|
942 |
|
|
// Priviledged mode? Then also update the other status bits
|
943 |
|
|
if ( i_execute_status_bits[1:0] != USR )
|
944 |
|
|
begin
|
945 |
|
|
status_bits_mode_wen_nxt = 1'd1;
|
946 |
|
|
status_bits_irq_mask_wen_nxt = 1'd1;
|
947 |
|
|
status_bits_firq_mask_wen_nxt = 1'd1;
|
948 |
|
|
end
|
949 |
|
|
end
|
950 |
|
|
end
|
951 |
|
|
|
952 |
|
|
end
|
953 |
|
|
|
954 |
|
|
// Handle asynchronous interrupts.
|
955 |
|
|
// interrupts are processed only during execution states
|
956 |
|
|
// multicycle instructions must complete before the interrupt starts
|
957 |
|
|
// SWI, Address Exception and Undefined Instruction interrupts are only executed if the
|
958 |
|
|
// instruction that causes the interrupt is conditionally executed so
|
959 |
|
|
// its not handled here
|
960 |
|
|
if ( instruction_valid && interrupt && next_interrupt != 3'd6 )
|
961 |
|
|
begin
|
962 |
|
|
// Save the interrupt causing instruction to refer back to later
|
963 |
|
|
// This also saves the instruction abort vma and status, in the case of an
|
964 |
|
|
// instruction abort interrupt
|
965 |
|
|
saved_current_instruction_wen = 1'd1;
|
966 |
|
|
|
967 |
|
|
// save address of next instruction to Supervisor Mode LR
|
968 |
|
|
// Address Exception ?
|
969 |
|
|
if ( next_interrupt == 3'd4 )
|
970 |
|
|
reg_write_sel_nxt = 3'd7; // pc
|
971 |
|
|
else
|
972 |
|
|
reg_write_sel_nxt = 3'd1; // pc -4
|
973 |
|
|
|
974 |
71 |
csantifort |
reg_bank_wsel_nxt = 4'd14; // LR
|
975 |
2 |
csantifort |
|
976 |
|
|
address_sel_nxt = 4'd2; // interrupt_vector
|
977 |
|
|
pc_sel_nxt = 2'd2; // interrupt_vector
|
978 |
|
|
|
979 |
|
|
status_bits_mode_nxt = interrupt_mode; // e.g. Supervisor mode
|
980 |
|
|
status_bits_mode_wen_nxt = 1'd1;
|
981 |
|
|
|
982 |
|
|
// disable normal interrupts
|
983 |
|
|
status_bits_irq_mask_nxt = 1'd1;
|
984 |
|
|
status_bits_irq_mask_wen_nxt = 1'd1;
|
985 |
|
|
|
986 |
|
|
// disable fast interrupts
|
987 |
|
|
if ( next_interrupt == 3'd2 ) // FIRQ
|
988 |
|
|
begin
|
989 |
|
|
status_bits_firq_mask_nxt = 1'd1;
|
990 |
|
|
status_bits_firq_mask_wen_nxt = 1'd1;
|
991 |
|
|
end
|
992 |
|
|
end
|
993 |
|
|
|
994 |
|
|
|
995 |
|
|
// previous instruction was either ldr or sdr
|
996 |
|
|
// if it is currently executing in the execute stage do the following
|
997 |
|
|
if ( control_state == MEM_WAIT1 )
|
998 |
|
|
begin
|
999 |
|
|
// Save the next instruction to execute later
|
1000 |
|
|
// Do this even if this instruction does not execute because of Condition
|
1001 |
|
|
pre_fetch_instruction_wen = 1'd1;
|
1002 |
|
|
|
1003 |
|
|
if ( instruction_execute ) // conditional execution state
|
1004 |
|
|
begin
|
1005 |
|
|
address_sel_nxt = 4'd3; // pc (not pc + 4)
|
1006 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1007 |
|
|
end
|
1008 |
|
|
end
|
1009 |
|
|
|
1010 |
|
|
|
1011 |
|
|
// completion of load operation
|
1012 |
|
|
if ( control_state == MEM_WAIT2 && load_op )
|
1013 |
|
|
begin
|
1014 |
|
|
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
|
1015 |
|
|
barrel_shift_amount_sel_nxt = 2'd3; // shift by address[1:0] x 8
|
1016 |
|
|
|
1017 |
|
|
// shift needed
|
1018 |
|
|
if ( i_execute_address[1:0] != 2'd0 )
|
1019 |
|
|
barrel_shift_function_nxt = ROR;
|
1020 |
|
|
|
1021 |
|
|
// load a byte
|
1022 |
|
|
if ( type == TRANS && instruction[22] )
|
1023 |
|
|
alu_out_sel_nxt = 4'd3; // zero_extend8
|
1024 |
|
|
|
1025 |
|
|
if ( !dabt ) // dont load data there is an abort on the data read
|
1026 |
|
|
begin
|
1027 |
|
|
// Check if the load destination is the PC
|
1028 |
|
|
if (instruction[15:12] == 4'd15)
|
1029 |
|
|
begin
|
1030 |
|
|
pc_sel_nxt = 2'd1; // alu_out
|
1031 |
|
|
address_sel_nxt = 4'd1; // alu_out
|
1032 |
|
|
end
|
1033 |
|
|
else
|
1034 |
71 |
csantifort |
reg_bank_wsel_nxt = instruction[15:12];
|
1035 |
2 |
csantifort |
end
|
1036 |
|
|
end
|
1037 |
|
|
|
1038 |
|
|
|
1039 |
|
|
// second cycle of multiple load or store
|
1040 |
|
|
if ( control_state == MTRANS_EXEC1 )
|
1041 |
|
|
begin
|
1042 |
|
|
// Save the next instruction to execute later
|
1043 |
|
|
// Do this even if this instruction does not execute because of Condition
|
1044 |
|
|
pre_fetch_instruction_wen = 1'd1;
|
1045 |
|
|
|
1046 |
|
|
if ( instruction_execute ) // conditional execution state
|
1047 |
|
|
begin
|
1048 |
|
|
address_sel_nxt = 4'd5; // o_address
|
1049 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1050 |
|
|
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
|
1051 |
|
|
// rather than an instruction fetch
|
1052 |
|
|
|
1053 |
|
|
if ( !instruction[20] ) // Store
|
1054 |
|
|
write_data_wen_nxt = 1'd1;
|
1055 |
|
|
|
1056 |
|
|
// LDM: load into user mode registers, when in priviledged mode
|
1057 |
|
|
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
|
1058 |
|
|
user_mode_regs_load_nxt = 1'd1;
|
1059 |
|
|
|
1060 |
|
|
// SDM: store the user mode registers, when in priviledged mode
|
1061 |
|
|
if ( {instruction[22:20]} == 3'b100 )
|
1062 |
|
|
o_user_mode_regs_store_nxt = 1'd1;
|
1063 |
|
|
end
|
1064 |
|
|
end
|
1065 |
|
|
|
1066 |
|
|
|
1067 |
|
|
// third cycle of multiple load or store
|
1068 |
|
|
if ( control_state == MTRANS_EXEC2 )
|
1069 |
|
|
begin
|
1070 |
|
|
address_sel_nxt = 4'd5; // o_address
|
1071 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1072 |
|
|
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
|
1073 |
|
|
// rather than an instruction fetch
|
1074 |
|
|
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
|
1075 |
|
|
|
1076 |
|
|
// Load or Store
|
1077 |
|
|
if ( instruction[20] ) // Load
|
1078 |
|
|
begin
|
1079 |
|
|
// Can never be loading the PC in this state, as the PC is always
|
1080 |
|
|
// the last register in the set to be loaded
|
1081 |
|
|
if ( !dabt )
|
1082 |
71 |
csantifort |
reg_bank_wsel_nxt = mtrans_reg_d2;
|
1083 |
2 |
csantifort |
end
|
1084 |
|
|
else // Store
|
1085 |
|
|
write_data_wen_nxt = 1'd1;
|
1086 |
|
|
|
1087 |
|
|
// LDM: load into user mode registers, when in priviledged mode
|
1088 |
|
|
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
|
1089 |
|
|
user_mode_regs_load_nxt = 1'd1;
|
1090 |
|
|
|
1091 |
|
|
// SDM: store the user mode registers, when in priviledged mode
|
1092 |
|
|
if ( {instruction[22:20]} == 3'b100 )
|
1093 |
|
|
o_user_mode_regs_store_nxt = 1'd1;
|
1094 |
|
|
end
|
1095 |
|
|
|
1096 |
|
|
|
1097 |
|
|
// second or fourth cycle of multiple load or store
|
1098 |
|
|
if ( control_state == MTRANS_EXEC3 && instruction_execute )
|
1099 |
|
|
begin
|
1100 |
|
|
address_sel_nxt = 4'd3; // pc (not pc + 4)
|
1101 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1102 |
|
|
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
|
1103 |
|
|
|
1104 |
|
|
// Can never be loading the PC in this state, as the PC is always
|
1105 |
|
|
// the last register in the set to be loaded
|
1106 |
|
|
if ( instruction[20] && !dabt ) // Load
|
1107 |
71 |
csantifort |
reg_bank_wsel_nxt = mtrans_reg_d2;
|
1108 |
2 |
csantifort |
|
1109 |
|
|
// LDM: load into user mode registers, when in priviledged mode
|
1110 |
|
|
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
|
1111 |
|
|
user_mode_regs_load_nxt = 1'd1;
|
1112 |
|
|
|
1113 |
|
|
// SDM: store the user mode registers, when in priviledged mode
|
1114 |
|
|
if ( {instruction[22:20]} == 3'b100 )
|
1115 |
|
|
o_user_mode_regs_store_nxt = 1'd1;
|
1116 |
|
|
end
|
1117 |
|
|
|
1118 |
|
|
// state is used for LMD/STM of a single register
|
1119 |
|
|
if ( control_state == MTRANS_EXEC3B && instruction_execute )
|
1120 |
|
|
begin
|
1121 |
|
|
// Save the next instruction to execute later
|
1122 |
|
|
// Do this even if this instruction does not execute because of Condition
|
1123 |
|
|
pre_fetch_instruction_wen = 1'd1;
|
1124 |
|
|
|
1125 |
|
|
address_sel_nxt = 4'd3; // pc (not pc + 4)
|
1126 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1127 |
|
|
|
1128 |
|
|
// LDM: load into user mode registers, when in priviledged mode
|
1129 |
|
|
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
|
1130 |
|
|
user_mode_regs_load_nxt = 1'd1;
|
1131 |
|
|
|
1132 |
|
|
// SDM: store the user mode registers, when in priviledged mode
|
1133 |
|
|
if ( {instruction[22:20]} == 3'b100 )
|
1134 |
|
|
o_user_mode_regs_store_nxt = 1'd1;
|
1135 |
|
|
end
|
1136 |
|
|
|
1137 |
|
|
if ( control_state == MTRANS_EXEC4 )
|
1138 |
|
|
begin
|
1139 |
|
|
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
|
1140 |
|
|
|
1141 |
|
|
if ( instruction[20] ) // Load
|
1142 |
|
|
begin
|
1143 |
|
|
if (!dabt) // dont overwrite registers or status if theres a data abort
|
1144 |
|
|
begin
|
1145 |
|
|
if ( mtrans_reg_d2 == 4'd15 ) // load new value into PC
|
1146 |
|
|
begin
|
1147 |
|
|
address_sel_nxt = 4'd1; // alu_out - read instructions using new PC value
|
1148 |
|
|
pc_sel_nxt = 2'd1; // alu_out
|
1149 |
|
|
pc_wen_nxt = 1'd1; // write PC
|
1150 |
|
|
|
1151 |
|
|
// ldm with S bit and pc: the Status bits are updated
|
1152 |
|
|
// Node this must be done only at the end
|
1153 |
|
|
// so the register set is the set in the mode before it
|
1154 |
|
|
// gets changed.
|
1155 |
|
|
if ( instruction[22] )
|
1156 |
|
|
begin
|
1157 |
|
|
status_bits_sel_nxt = 3'd1; // alu out
|
1158 |
|
|
status_bits_flags_wen_nxt = 1'd1;
|
1159 |
|
|
|
1160 |
|
|
// Can't change the mode or mask bits in User mode
|
1161 |
|
|
if ( i_execute_status_bits[1:0] != USR )
|
1162 |
|
|
begin
|
1163 |
|
|
status_bits_mode_wen_nxt = 1'd1;
|
1164 |
|
|
status_bits_irq_mask_wen_nxt = 1'd1;
|
1165 |
|
|
status_bits_firq_mask_wen_nxt = 1'd1;
|
1166 |
|
|
end
|
1167 |
|
|
end
|
1168 |
|
|
end
|
1169 |
|
|
else
|
1170 |
|
|
begin
|
1171 |
71 |
csantifort |
reg_bank_wsel_nxt = mtrans_reg_d2;
|
1172 |
2 |
csantifort |
end
|
1173 |
|
|
end
|
1174 |
|
|
end
|
1175 |
|
|
|
1176 |
|
|
// we have a data abort interrupt
|
1177 |
|
|
if ( dabt )
|
1178 |
|
|
begin
|
1179 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1180 |
|
|
end
|
1181 |
|
|
|
1182 |
|
|
// LDM: load into user mode registers, when in priviledged mode
|
1183 |
|
|
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
|
1184 |
|
|
user_mode_regs_load_nxt = 1'd1;
|
1185 |
|
|
|
1186 |
|
|
// SDM: store the user mode registers, when in priviledged mode
|
1187 |
|
|
if ( {instruction[22:20]} == 3'b100 )
|
1188 |
|
|
o_user_mode_regs_store_nxt = 1'd1;
|
1189 |
|
|
end
|
1190 |
|
|
|
1191 |
|
|
|
1192 |
|
|
// state is for when a data abort interrupt is triggered during an LDM
|
1193 |
|
|
if ( control_state == MTRANS5_ABORT )
|
1194 |
|
|
begin
|
1195 |
|
|
// Restore the Base Address, if the base register is included in the
|
1196 |
|
|
// list of registers being loaded
|
1197 |
|
|
if (restore_base_address) // LDM with base address in register list
|
1198 |
|
|
begin
|
1199 |
|
|
reg_write_sel_nxt = 3'd6; // write base_register
|
1200 |
71 |
csantifort |
reg_bank_wsel_nxt = instruction[19:16]; // to Rn
|
1201 |
2 |
csantifort |
end
|
1202 |
|
|
end
|
1203 |
|
|
|
1204 |
|
|
|
1205 |
|
|
// Multiply or Multiply-Accumulate
|
1206 |
|
|
if ( control_state == MULT_PROC1 && instruction_execute )
|
1207 |
|
|
begin
|
1208 |
|
|
// Save the next instruction to execute later
|
1209 |
|
|
// Do this even if this instruction does not execute because of Condition
|
1210 |
|
|
pre_fetch_instruction_wen = 1'd1;
|
1211 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1212 |
|
|
multiply_function_nxt = o_multiply_function;
|
1213 |
|
|
end
|
1214 |
|
|
|
1215 |
|
|
|
1216 |
|
|
// Multiply or Multiply-Accumulate
|
1217 |
|
|
// Do multiplication
|
1218 |
|
|
// Wait for done or accumulate signal
|
1219 |
|
|
if ( control_state == MULT_PROC2 )
|
1220 |
|
|
begin
|
1221 |
|
|
// Save the next instruction to execute later
|
1222 |
|
|
// Do this even if this instruction does not execute because of Condition
|
1223 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1224 |
|
|
address_sel_nxt = 4'd3; // pc (not pc + 4)
|
1225 |
|
|
multiply_function_nxt = o_multiply_function;
|
1226 |
|
|
end
|
1227 |
|
|
|
1228 |
|
|
|
1229 |
|
|
// Save RdLo
|
1230 |
|
|
// always last cycle of all multiply or multiply accumulate operations
|
1231 |
|
|
if ( control_state == MULT_STORE )
|
1232 |
|
|
begin
|
1233 |
|
|
reg_write_sel_nxt = 3'd2; // multiply_out
|
1234 |
|
|
multiply_function_nxt = o_multiply_function;
|
1235 |
|
|
|
1236 |
|
|
if ( type == MULT ) // 32-bit
|
1237 |
71 |
csantifort |
reg_bank_wsel_nxt = instruction[19:16]; // Rd
|
1238 |
2 |
csantifort |
else // 64-bit / Long
|
1239 |
71 |
csantifort |
reg_bank_wsel_nxt = instruction[15:12]; // RdLo
|
1240 |
2 |
csantifort |
|
1241 |
|
|
if ( instruction[20] ) // the 'S' bit
|
1242 |
|
|
begin
|
1243 |
|
|
status_bits_sel_nxt = 3'd4; // { multiply_flags, status_bits_flags[1:0] }
|
1244 |
|
|
status_bits_flags_wen_nxt = 1'd1;
|
1245 |
|
|
end
|
1246 |
|
|
end
|
1247 |
|
|
|
1248 |
|
|
// Add lower 32 bits to multiplication product
|
1249 |
|
|
if ( control_state == MULT_ACCUMU )
|
1250 |
|
|
begin
|
1251 |
|
|
multiply_function_nxt = o_multiply_function;
|
1252 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1253 |
|
|
address_sel_nxt = 4'd3; // pc (not pc + 4)
|
1254 |
|
|
end
|
1255 |
|
|
|
1256 |
|
|
// swp - do write request in 2nd cycle
|
1257 |
|
|
if ( control_state == SWAP_WRITE && instruction_execute )
|
1258 |
|
|
begin
|
1259 |
|
|
barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
|
1260 |
|
|
address_sel_nxt = 4'd4; // Rn
|
1261 |
|
|
write_data_wen_nxt = 1'd1;
|
1262 |
|
|
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
|
1263 |
|
|
// rather than an instruction fetch
|
1264 |
|
|
|
1265 |
|
|
if ( instruction[22] )
|
1266 |
|
|
byte_enable_sel_nxt = 2'd1; // Save byte
|
1267 |
|
|
|
1268 |
|
|
if ( instruction_execute ) // conditional execution state
|
1269 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1270 |
|
|
|
1271 |
|
|
// Save the next instruction to execute later
|
1272 |
|
|
// Do this even if this instruction does not execute because of Condition
|
1273 |
|
|
pre_fetch_instruction_wen = 1'd1;
|
1274 |
|
|
|
1275 |
|
|
end
|
1276 |
|
|
|
1277 |
|
|
|
1278 |
|
|
// swp - receive read response in 3rd cycle
|
1279 |
|
|
if ( control_state == SWAP_WAIT1 )
|
1280 |
|
|
begin
|
1281 |
|
|
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
|
1282 |
|
|
barrel_shift_amount_sel_nxt = 2'd3; // shift by address[1:0] x 8
|
1283 |
|
|
|
1284 |
|
|
// shift needed
|
1285 |
|
|
if ( i_execute_address[1:0] != 2'd0 )
|
1286 |
|
|
barrel_shift_function_nxt = ROR;
|
1287 |
|
|
|
1288 |
|
|
if ( instruction_execute ) // conditional execution state
|
1289 |
|
|
begin
|
1290 |
|
|
address_sel_nxt = 4'd3; // pc (not pc + 4)
|
1291 |
|
|
pc_wen_nxt = 1'd0; // hold current PC value
|
1292 |
|
|
end
|
1293 |
|
|
|
1294 |
|
|
// load a byte
|
1295 |
|
|
if ( instruction[22] )
|
1296 |
|
|
alu_out_sel_nxt = 4'd3; // zero_extend8
|
1297 |
|
|
|
1298 |
|
|
if ( !dabt )
|
1299 |
|
|
begin
|
1300 |
|
|
// Check is the load destination is the PC
|
1301 |
|
|
if ( instruction[15:12] == 4'd15 )
|
1302 |
|
|
begin
|
1303 |
|
|
pc_sel_nxt = 2'd1; // alu_out
|
1304 |
|
|
address_sel_nxt = 4'd1; // alu_out
|
1305 |
|
|
end
|
1306 |
|
|
else
|
1307 |
71 |
csantifort |
reg_bank_wsel_nxt = instruction[15:12];
|
1308 |
2 |
csantifort |
end
|
1309 |
|
|
end
|
1310 |
|
|
|
1311 |
|
|
// 1 cycle delay for Co-Processor Register access
|
1312 |
|
|
if ( control_state == COPRO_WAIT && instruction_execute )
|
1313 |
|
|
begin
|
1314 |
|
|
pre_fetch_instruction_wen = 1'd1;
|
1315 |
|
|
|
1316 |
|
|
if ( instruction[20] ) // mrc instruction
|
1317 |
|
|
begin
|
1318 |
|
|
// Check is the load destination is the PC
|
1319 |
|
|
if ( instruction[15:12] == 4'd15 )
|
1320 |
|
|
begin
|
1321 |
|
|
// If r15 is specified for <Rd>, the condition code flags are
|
1322 |
|
|
// updated instead of a general-purpose register.
|
1323 |
|
|
status_bits_sel_nxt = 3'd3; // i_copro_data
|
1324 |
|
|
status_bits_flags_wen_nxt = 1'd1;
|
1325 |
|
|
|
1326 |
|
|
// Can't change these in USR mode
|
1327 |
|
|
if ( i_execute_status_bits[1:0] != USR )
|
1328 |
|
|
begin
|
1329 |
|
|
status_bits_mode_wen_nxt = 1'd1;
|
1330 |
|
|
status_bits_irq_mask_wen_nxt = 1'd1;
|
1331 |
|
|
status_bits_firq_mask_wen_nxt = 1'd1;
|
1332 |
|
|
end
|
1333 |
|
|
end
|
1334 |
|
|
else
|
1335 |
71 |
csantifort |
reg_bank_wsel_nxt = instruction[15:12];
|
1336 |
2 |
csantifort |
|
1337 |
|
|
reg_write_sel_nxt = 3'd5; // i_copro_data
|
1338 |
|
|
end
|
1339 |
|
|
else // mcr instruction
|
1340 |
|
|
begin
|
1341 |
|
|
copro_operation_nxt = 2'd2; // Register transfer to Co-Processor
|
1342 |
|
|
end
|
1343 |
|
|
end
|
1344 |
|
|
|
1345 |
|
|
|
1346 |
|
|
// Have just changed the status_bits mode but this
|
1347 |
|
|
// creates a 1 cycle gap with the old mode
|
1348 |
|
|
// coming back from execute into instruction_decode
|
1349 |
|
|
// So squash that old mode value during this
|
1350 |
|
|
// cycle of the interrupt transition
|
1351 |
|
|
if ( control_state == INT_WAIT1 )
|
1352 |
|
|
status_bits_mode_nxt = o_status_bits_mode; // Supervisor mode
|
1353 |
|
|
|
1354 |
|
|
end
|
1355 |
|
|
|
1356 |
|
|
|
1357 |
|
|
// Speed up the long path from u_decode/o_read_data to u_register_bank/r8_firq
|
1358 |
|
|
// This pre-encodes the firq_s3 signal thats used in u_register_bank
|
1359 |
|
|
assign firq_not_user_mode_nxt = !user_mode_regs_load_nxt && status_bits_mode_nxt == FIRQ;
|
1360 |
|
|
|
1361 |
|
|
|
1362 |
|
|
// ========================================================
|
1363 |
|
|
// Next State Logic
|
1364 |
|
|
// ========================================================
|
1365 |
|
|
|
1366 |
|
|
// this replicates the current value of the execute signal in the execute stage
|
1367 |
|
|
assign instruction_execute = conditional_execute ( o_condition, i_execute_status_bits[31:28] );
|
1368 |
|
|
|
1369 |
|
|
assign instruction_valid = (control_state == EXECUTE || control_state == PRE_FETCH_EXEC) ||
|
1370 |
|
|
// when last instruction was multi-cycle instruction but did not execute
|
1371 |
|
|
// because condition was false then act like you're in the execute state
|
1372 |
|
|
(!instruction_execute && (control_state == PC_STALL1 ||
|
1373 |
|
|
control_state == MEM_WAIT1 ||
|
1374 |
|
|
control_state == COPRO_WAIT ||
|
1375 |
|
|
control_state == SWAP_WRITE ||
|
1376 |
|
|
control_state == MULT_PROC1 ||
|
1377 |
|
|
control_state == MTRANS_EXEC1 ||
|
1378 |
|
|
control_state == MTRANS_EXEC3 ||
|
1379 |
|
|
control_state == MTRANS_EXEC3B ) );
|
1380 |
|
|
|
1381 |
|
|
|
1382 |
|
|
always @*
|
1383 |
|
|
begin
|
1384 |
|
|
// default is to hold the current state
|
1385 |
|
|
control_state_nxt = control_state;
|
1386 |
|
|
|
1387 |
|
|
// Note: The order is important here
|
1388 |
|
|
if ( control_state == RST_WAIT1 ) control_state_nxt = RST_WAIT2;
|
1389 |
|
|
if ( control_state == RST_WAIT2 ) control_state_nxt = EXECUTE;
|
1390 |
|
|
if ( control_state == INT_WAIT1 ) control_state_nxt = INT_WAIT2;
|
1391 |
|
|
if ( control_state == INT_WAIT2 ) control_state_nxt = EXECUTE;
|
1392 |
|
|
if ( control_state == COPRO_WAIT ) control_state_nxt = PRE_FETCH_EXEC;
|
1393 |
|
|
if ( control_state == PC_STALL1 ) control_state_nxt = PC_STALL2;
|
1394 |
|
|
if ( control_state == PC_STALL2 ) control_state_nxt = EXECUTE;
|
1395 |
|
|
if ( control_state == SWAP_WRITE ) control_state_nxt = SWAP_WAIT1;
|
1396 |
|
|
if ( control_state == SWAP_WAIT1 ) control_state_nxt = SWAP_WAIT2;
|
1397 |
|
|
if ( control_state == MULT_STORE ) control_state_nxt = PRE_FETCH_EXEC;
|
1398 |
|
|
if ( control_state == MTRANS5_ABORT ) control_state_nxt = PRE_FETCH_EXEC;
|
1399 |
|
|
|
1400 |
|
|
if ( control_state == MEM_WAIT1 )
|
1401 |
|
|
control_state_nxt = MEM_WAIT2;
|
1402 |
|
|
|
1403 |
|
|
if ( control_state == MEM_WAIT2 ||
|
1404 |
|
|
control_state == SWAP_WAIT2 )
|
1405 |
|
|
begin
|
1406 |
|
|
if ( write_pc ) // writing to the PC!!
|
1407 |
|
|
control_state_nxt = PC_STALL1;
|
1408 |
|
|
else
|
1409 |
|
|
control_state_nxt = PRE_FETCH_EXEC;
|
1410 |
|
|
end
|
1411 |
|
|
|
1412 |
|
|
if ( control_state == MTRANS_EXEC1 )
|
1413 |
|
|
begin
|
1414 |
|
|
if (mtrans_instruction_nxt[15:0] != 16'd0)
|
1415 |
|
|
control_state_nxt = MTRANS_EXEC2;
|
1416 |
|
|
else // if the register list holds a single register
|
1417 |
|
|
control_state_nxt = MTRANS_EXEC3;
|
1418 |
|
|
end
|
1419 |
|
|
|
1420 |
|
|
// Stay in State MTRANS_EXEC2 until the full list of registers to
|
1421 |
|
|
// load or store has been processed
|
1422 |
|
|
if ( control_state == MTRANS_EXEC2 && mtrans_num_registers == 5'd1 )
|
1423 |
|
|
control_state_nxt = MTRANS_EXEC3;
|
1424 |
|
|
|
1425 |
|
|
if ( control_state == MTRANS_EXEC3 ) control_state_nxt = MTRANS_EXEC4;
|
1426 |
|
|
|
1427 |
|
|
if ( control_state == MTRANS_EXEC3B ) control_state_nxt = MTRANS_EXEC4;
|
1428 |
|
|
|
1429 |
|
|
if ( control_state == MTRANS_EXEC4 )
|
1430 |
|
|
begin
|
1431 |
|
|
if ( dabt ) // data abort
|
1432 |
|
|
control_state_nxt = MTRANS5_ABORT;
|
1433 |
|
|
else if (write_pc) // writing to the PC!!
|
1434 |
|
|
control_state_nxt = PC_STALL1;
|
1435 |
|
|
else
|
1436 |
|
|
control_state_nxt = PRE_FETCH_EXEC;
|
1437 |
|
|
end
|
1438 |
|
|
|
1439 |
|
|
if ( control_state == MULT_PROC1 )
|
1440 |
|
|
begin
|
1441 |
|
|
if (!instruction_execute)
|
1442 |
|
|
control_state_nxt = PRE_FETCH_EXEC;
|
1443 |
|
|
else
|
1444 |
|
|
control_state_nxt = MULT_PROC2;
|
1445 |
|
|
end
|
1446 |
|
|
|
1447 |
|
|
if ( control_state == MULT_PROC2 )
|
1448 |
|
|
begin
|
1449 |
|
|
if ( i_multiply_done )
|
1450 |
|
|
if ( o_multiply_function[1] ) // Accumulate ?
|
1451 |
|
|
control_state_nxt = MULT_ACCUMU;
|
1452 |
|
|
else
|
1453 |
|
|
control_state_nxt = MULT_STORE;
|
1454 |
|
|
end
|
1455 |
|
|
|
1456 |
|
|
|
1457 |
|
|
if ( control_state == MULT_ACCUMU )
|
1458 |
|
|
begin
|
1459 |
|
|
control_state_nxt = MULT_STORE;
|
1460 |
|
|
end
|
1461 |
|
|
|
1462 |
|
|
|
1463 |
|
|
// This should come at the end, so that conditional execution works
|
1464 |
|
|
// correctly
|
1465 |
|
|
if ( instruction_valid )
|
1466 |
|
|
begin
|
1467 |
|
|
// default is to stay in execute state, or to move into this
|
1468 |
|
|
// state from a conditional execute state
|
1469 |
|
|
control_state_nxt = EXECUTE;
|
1470 |
|
|
|
1471 |
|
|
if ( mem_op ) // load or store word or byte
|
1472 |
|
|
control_state_nxt = MEM_WAIT1;
|
1473 |
|
|
if ( write_pc )
|
1474 |
|
|
control_state_nxt = PC_STALL1;
|
1475 |
|
|
if ( type == MTRANS )
|
1476 |
|
|
begin
|
1477 |
|
|
if ( mtrans_num_registers != 5'd0 )
|
1478 |
|
|
begin
|
1479 |
|
|
// check for LDM/STM of a single register
|
1480 |
|
|
if ( mtrans_num_registers == 5'd1 )
|
1481 |
|
|
control_state_nxt = MTRANS_EXEC3B;
|
1482 |
|
|
else
|
1483 |
|
|
control_state_nxt = MTRANS_EXEC1;
|
1484 |
|
|
end
|
1485 |
|
|
else
|
1486 |
|
|
control_state_nxt = MTRANS_EXEC3;
|
1487 |
|
|
end
|
1488 |
|
|
|
1489 |
|
|
if ( type == MULT )
|
1490 |
|
|
control_state_nxt = MULT_PROC1;
|
1491 |
|
|
|
1492 |
|
|
if ( type == SWAP )
|
1493 |
|
|
control_state_nxt = SWAP_WRITE;
|
1494 |
|
|
|
1495 |
|
|
if ( type == CORTRANS && !und_request )
|
1496 |
|
|
control_state_nxt = COPRO_WAIT;
|
1497 |
|
|
|
1498 |
|
|
// interrupt overrides everything else so its last
|
1499 |
|
|
if ( interrupt )
|
1500 |
|
|
control_state_nxt = INT_WAIT1;
|
1501 |
|
|
end
|
1502 |
|
|
end
|
1503 |
|
|
|
1504 |
|
|
|
1505 |
|
|
// ========================================================
|
1506 |
|
|
// Register Update
|
1507 |
|
|
// ========================================================
|
1508 |
|
|
always @ ( posedge i_clk )
|
1509 |
|
|
if (!i_fetch_stall)
|
1510 |
|
|
begin
|
1511 |
|
|
o_read_data <= i_read_data;
|
1512 |
|
|
o_read_data_alignment <= {i_execute_address[1:0], 3'd0};
|
1513 |
|
|
abt_address_reg <= i_execute_address;
|
1514 |
|
|
iabt_reg <= i_iabt;
|
1515 |
|
|
adex_reg <= i_adex;
|
1516 |
|
|
abt_status_reg <= i_abt_status;
|
1517 |
|
|
o_status_bits_mode <= status_bits_mode_nxt;
|
1518 |
|
|
o_status_bits_irq_mask <= status_bits_irq_mask_nxt;
|
1519 |
|
|
o_status_bits_firq_mask <= status_bits_firq_mask_nxt;
|
1520 |
|
|
o_imm32 <= imm32_nxt;
|
1521 |
|
|
o_imm_shift_amount <= imm_shift_amount_nxt;
|
1522 |
|
|
o_shift_imm_zero <= shift_imm_zero_nxt;
|
1523 |
|
|
|
1524 |
|
|
// when have an interrupt, execute the interrupt operation
|
1525 |
|
|
// unconditionally in the execute stage
|
1526 |
|
|
// ensures that status_bits register gets updated correctly
|
1527 |
|
|
// Likewise when in middle of multi-cycle instructions
|
1528 |
|
|
// execute them unconditionally
|
1529 |
|
|
o_condition <= instruction_valid && !interrupt ? condition_nxt : AL;
|
1530 |
|
|
o_exclusive_exec <= exclusive_exec_nxt;
|
1531 |
|
|
o_data_access_exec <= data_access_exec_nxt;
|
1532 |
|
|
|
1533 |
71 |
csantifort |
o_rm_sel <= o_rm_sel_nxt;
|
1534 |
|
|
o_rds_sel <= o_rds_sel_nxt;
|
1535 |
|
|
o_rn_sel <= o_rn_sel_nxt;
|
1536 |
2 |
csantifort |
o_barrel_shift_amount_sel <= barrel_shift_amount_sel_nxt;
|
1537 |
|
|
o_barrel_shift_data_sel <= barrel_shift_data_sel_nxt;
|
1538 |
|
|
o_barrel_shift_function <= barrel_shift_function_nxt;
|
1539 |
|
|
o_alu_function <= alu_function_nxt;
|
1540 |
|
|
o_multiply_function <= multiply_function_nxt;
|
1541 |
|
|
o_interrupt_vector_sel <= next_interrupt;
|
1542 |
|
|
o_address_sel <= address_sel_nxt;
|
1543 |
|
|
o_pc_sel <= pc_sel_nxt;
|
1544 |
|
|
o_byte_enable_sel <= byte_enable_sel_nxt;
|
1545 |
|
|
o_status_bits_sel <= status_bits_sel_nxt;
|
1546 |
|
|
o_reg_write_sel <= reg_write_sel_nxt;
|
1547 |
|
|
o_user_mode_regs_load <= user_mode_regs_load_nxt;
|
1548 |
|
|
o_firq_not_user_mode <= firq_not_user_mode_nxt;
|
1549 |
|
|
o_write_data_wen <= write_data_wen_nxt;
|
1550 |
|
|
o_base_address_wen <= base_address_wen_nxt;
|
1551 |
|
|
o_pc_wen <= pc_wen_nxt;
|
1552 |
71 |
csantifort |
o_reg_bank_wsel <= reg_bank_wsel_nxt;
|
1553 |
|
|
o_reg_bank_wen <= decode ( reg_bank_wsel_nxt );
|
1554 |
2 |
csantifort |
o_status_bits_flags_wen <= status_bits_flags_wen_nxt;
|
1555 |
|
|
o_status_bits_mode_wen <= status_bits_mode_wen_nxt;
|
1556 |
|
|
o_status_bits_irq_mask_wen <= status_bits_irq_mask_wen_nxt;
|
1557 |
|
|
o_status_bits_firq_mask_wen <= status_bits_firq_mask_wen_nxt;
|
1558 |
|
|
|
1559 |
|
|
o_copro_opcode1 <= instruction[23:21];
|
1560 |
|
|
o_copro_opcode2 <= instruction[7:5];
|
1561 |
|
|
o_copro_crn <= instruction[19:16];
|
1562 |
|
|
o_copro_crm <= instruction[3:0];
|
1563 |
|
|
o_copro_num <= instruction[11:8];
|
1564 |
|
|
o_copro_operation <= copro_operation_nxt;
|
1565 |
|
|
o_copro_write_data_wen <= copro_write_data_wen_nxt;
|
1566 |
|
|
mtrans_r15 <= mtrans_r15_nxt;
|
1567 |
|
|
restore_base_address <= restore_base_address_nxt;
|
1568 |
|
|
control_state <= control_state_nxt;
|
1569 |
|
|
mtrans_reg_d1 <= mtrans_reg;
|
1570 |
|
|
mtrans_reg_d2 <= mtrans_reg_d1;
|
1571 |
|
|
end
|
1572 |
|
|
|
1573 |
|
|
|
1574 |
|
|
|
1575 |
|
|
always @ ( posedge i_clk )
|
1576 |
|
|
if ( !i_fetch_stall )
|
1577 |
|
|
begin
|
1578 |
|
|
// sometimes this is a pre-fetch instruction
|
1579 |
|
|
// e.g. two ldr instructions in a row. The second ldr will be saved
|
1580 |
|
|
// to the pre-fetch instruction register
|
1581 |
|
|
// then when its decoded, a copy is saved to the saved_current_instruction
|
1582 |
|
|
// register
|
1583 |
|
|
if (type == MTRANS)
|
1584 |
|
|
begin
|
1585 |
|
|
saved_current_instruction <= mtrans_instruction_nxt;
|
1586 |
|
|
saved_current_instruction_iabt <= instruction_iabt;
|
1587 |
|
|
saved_current_instruction_adex <= instruction_adex;
|
1588 |
|
|
saved_current_instruction_address <= instruction_address;
|
1589 |
|
|
saved_current_instruction_iabt_status <= instruction_iabt_status;
|
1590 |
|
|
end
|
1591 |
|
|
else if (saved_current_instruction_wen)
|
1592 |
|
|
begin
|
1593 |
|
|
saved_current_instruction <= instruction;
|
1594 |
|
|
saved_current_instruction_iabt <= instruction_iabt;
|
1595 |
|
|
saved_current_instruction_adex <= instruction_adex;
|
1596 |
|
|
saved_current_instruction_address <= instruction_address;
|
1597 |
|
|
saved_current_instruction_iabt_status <= instruction_iabt_status;
|
1598 |
|
|
end
|
1599 |
|
|
|
1600 |
|
|
if (pre_fetch_instruction_wen)
|
1601 |
|
|
begin
|
1602 |
|
|
pre_fetch_instruction <= o_read_data;
|
1603 |
|
|
pre_fetch_instruction_iabt <= iabt_reg;
|
1604 |
|
|
pre_fetch_instruction_adex <= adex_reg;
|
1605 |
|
|
pre_fetch_instruction_address <= abt_address_reg;
|
1606 |
|
|
pre_fetch_instruction_iabt_status <= abt_status_reg;
|
1607 |
|
|
end
|
1608 |
|
|
end
|
1609 |
|
|
|
1610 |
|
|
|
1611 |
|
|
|
1612 |
|
|
always @ ( posedge i_clk )
|
1613 |
|
|
if ( !i_fetch_stall )
|
1614 |
|
|
begin
|
1615 |
|
|
irq <= i_irq;
|
1616 |
|
|
firq <= i_firq;
|
1617 |
|
|
|
1618 |
|
|
if ( control_state == INT_WAIT1 && o_status_bits_mode == SVC )
|
1619 |
|
|
begin
|
1620 |
|
|
dabt_reg <= 1'd0;
|
1621 |
|
|
end
|
1622 |
|
|
else
|
1623 |
|
|
begin
|
1624 |
|
|
dabt_reg <= dabt_reg || i_dabt;
|
1625 |
|
|
end
|
1626 |
|
|
|
1627 |
|
|
dabt_reg_d1 <= dabt_reg;
|
1628 |
|
|
end
|
1629 |
|
|
|
1630 |
|
|
assign dabt = dabt_reg || i_dabt;
|
1631 |
|
|
|
1632 |
|
|
|
1633 |
|
|
// ========================================================
|
1634 |
|
|
// Decompiler for debugging core - not synthesizable
|
1635 |
|
|
// ========================================================
|
1636 |
|
|
//synopsys translate_off
|
1637 |
|
|
|
1638 |
|
|
`include "debug_functions.v"
|
1639 |
|
|
|
1640 |
15 |
csantifort |
a23_decompile u_decompile (
|
1641 |
2 |
csantifort |
.i_clk ( i_clk ),
|
1642 |
|
|
.i_fetch_stall ( i_fetch_stall ),
|
1643 |
|
|
.i_instruction ( instruction ),
|
1644 |
|
|
.i_instruction_valid ( instruction_valid ),
|
1645 |
|
|
.i_instruction_execute ( instruction_execute ),
|
1646 |
|
|
.i_instruction_address ( instruction_address ),
|
1647 |
|
|
.i_interrupt ( {3{interrupt}} & next_interrupt ),
|
1648 |
|
|
.i_interrupt_state ( control_state == INT_WAIT2 ),
|
1649 |
|
|
.i_instruction_undefined ( und_request ),
|
1650 |
|
|
.i_pc_sel ( o_pc_sel ),
|
1651 |
|
|
.i_pc_wen ( o_pc_wen )
|
1652 |
|
|
);
|
1653 |
|
|
|
1654 |
|
|
|
1655 |
|
|
wire [(15*8)-1:0] xCONTROL_STATE;
|
1656 |
|
|
wire [(15*8)-1:0] xMODE;
|
1657 |
|
|
|
1658 |
|
|
assign xCONTROL_STATE =
|
1659 |
|
|
control_state == RST_WAIT1 ? "RST_WAIT1" :
|
1660 |
|
|
control_state == RST_WAIT2 ? "RST_WAIT2" :
|
1661 |
|
|
|
1662 |
|
|
|
1663 |
|
|
control_state == INT_WAIT1 ? "INT_WAIT1" :
|
1664 |
|
|
control_state == INT_WAIT2 ? "INT_WAIT2" :
|
1665 |
|
|
control_state == EXECUTE ? "EXECUTE" :
|
1666 |
|
|
control_state == PRE_FETCH_EXEC ? "PRE_FETCH_EXEC" :
|
1667 |
|
|
control_state == MEM_WAIT1 ? "MEM_WAIT1" :
|
1668 |
|
|
control_state == MEM_WAIT2 ? "MEM_WAIT2" :
|
1669 |
|
|
control_state == PC_STALL1 ? "PC_STALL1" :
|
1670 |
|
|
control_state == PC_STALL2 ? "PC_STALL2" :
|
1671 |
|
|
control_state == MTRANS_EXEC1 ? "MTRANS_EXEC1" :
|
1672 |
|
|
control_state == MTRANS_EXEC2 ? "MTRANS_EXEC2" :
|
1673 |
|
|
control_state == MTRANS_EXEC3 ? "MTRANS_EXEC3" :
|
1674 |
|
|
control_state == MTRANS_EXEC3B ? "MTRANS_EXEC3B" :
|
1675 |
|
|
control_state == MTRANS_EXEC4 ? "MTRANS_EXEC4" :
|
1676 |
|
|
control_state == MTRANS5_ABORT ? "MTRANS5_ABORT" :
|
1677 |
|
|
control_state == MULT_PROC1 ? "MULT_PROC1" :
|
1678 |
|
|
control_state == MULT_PROC2 ? "MULT_PROC2" :
|
1679 |
|
|
control_state == MULT_STORE ? "MULT_STORE" :
|
1680 |
|
|
control_state == MULT_ACCUMU ? "MULT_ACCUMU" :
|
1681 |
|
|
control_state == SWAP_WRITE ? "SWAP_WRITE" :
|
1682 |
|
|
control_state == SWAP_WAIT1 ? "SWAP_WAIT1" :
|
1683 |
|
|
control_state == SWAP_WAIT2 ? "SWAP_WAIT2" :
|
1684 |
|
|
control_state == COPRO_WAIT ? "COPRO_WAIT" :
|
1685 |
|
|
"UNKNOWN " ;
|
1686 |
|
|
|
1687 |
|
|
assign xMODE = mode_name ( o_status_bits_mode );
|
1688 |
|
|
|
1689 |
|
|
always @( posedge i_clk )
|
1690 |
|
|
if (control_state == EXECUTE && ((instruction[0] === 1'bx) || (instruction[31] === 1'bx)))
|
1691 |
|
|
begin
|
1692 |
|
|
`TB_ERROR_MESSAGE
|
1693 |
|
|
$display("Instruction with x's =%08h", instruction);
|
1694 |
|
|
end
|
1695 |
|
|
//synopsys translate_on
|
1696 |
|
|
|
1697 |
|
|
endmodule
|
1698 |
|
|
|
1699 |
|
|
|