OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_execute.v] - Blame information for rev 87

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Execute stage of Amber 2 Core                               //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Executes instructions. Instantiates the register file, ALU  //
10
//  multiplication unit and barrel shifter. This stage is       //
11
//  relitively simple. All the complex stuff is done in the     //
12
//  decode stage.                                               //
13
//                                                              //
14
//  Author(s):                                                  //
15
//      - Conor Santifort, csantifort.amber@gmail.com           //
16
//                                                              //
17
//////////////////////////////////////////////////////////////////
18
//                                                              //
19
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
20
//                                                              //
21
// This source file may be used and distributed without         //
22
// restriction provided that this copyright statement is not    //
23
// removed from the file and that any derivative work contains  //
24
// the original copyright notice and the associated disclaimer. //
25
//                                                              //
26
// This source file is free software; you can redistribute it   //
27
// and/or modify it under the terms of the GNU Lesser General   //
28
// Public License as published by the Free Software Foundation; //
29
// either version 2.1 of the License, or (at your option) any   //
30
// later version.                                               //
31
//                                                              //
32
// This source is distributed in the hope that it will be       //
33
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
34
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
35
// PURPOSE.  See the GNU Lesser General Public License for more //
36
// details.                                                     //
37
//                                                              //
38
// You should have received a copy of the GNU Lesser General    //
39
// Public License along with this source; if not, download it   //
40
// from http://www.opencores.org/lgpl.shtml                     //
41
//                                                              //
42
//////////////////////////////////////////////////////////////////
43
 
44 82 csantifort
`include "a23_config_defines.vh"
45 2 csantifort
 
46 15 csantifort
module a23_execute (
47 2 csantifort
 
48
input                       i_clk,
49
input       [31:0]          i_read_data,
50
input       [4:0]           i_read_data_alignment,  // 2 LSBs of address in [4:3], appended 
51
                                                    // with 3 zeros
52
input       [31:0]          i_copro_read_data,      // From Co-Processor, to either Register 
53
                                                    // or Memory
54
input                       i_data_access_exec,     // from Instruction Decode stage
55
                                                    // high means the memory access is a read 
56
                                                    // read or write, low for instruction
57
 
58
output reg  [31:0]          o_copro_write_data = 'd0,
59
output reg  [31:0]          o_write_data = 'd0,
60
output reg  [31:0]          o_address = 32'hdead_dead,
61
output reg                  o_adex = 'd0,           // Address Exception
62
output reg                  o_address_valid = 'd0,  // Prevents the reset address value being a 
63
                                                    // wishbone access
64
output      [31:0]          o_address_nxt,          // un-registered version of address to the 
65
                                                    // cache rams address ports
66
output reg                  o_priviledged = 'd0,    // Priviledged access
67
output reg                  o_exclusive = 'd0,      // swap access
68
output reg                  o_write_enable = 'd0,
69
output reg  [3:0]           o_byte_enable = 'd0,
70
output reg                  o_data_access = 'd0,    // To Fetch stage. high = data fetch, 
71
                                                    // low = instruction fetch
72
output      [31:0]          o_status_bits,          // Full PC will all status bits, but PC part zero'ed out
73
output                      o_multiply_done,
74
 
75
 
76
// --------------------------------------------------
77
// Control signals from Instruction Decode stage
78
// --------------------------------------------------
79
input                       i_fetch_stall,          // stall all stages of the cpu at the same time
80
input      [1:0]            i_status_bits_mode,
81
input                       i_status_bits_irq_mask,
82
input                       i_status_bits_firq_mask,
83
input      [31:0]           i_imm32,
84
input      [4:0]            i_imm_shift_amount,
85
input                       i_shift_imm_zero,
86
input      [3:0]            i_condition,
87
input                       i_exclusive_exec,       // swap access
88 83 csantifort
input                       i_use_carry_in,         // e.g. add with carry instruction
89 2 csantifort
 
90
input      [3:0]            i_rm_sel,
91
input      [3:0]            i_rds_sel,
92
input      [3:0]            i_rn_sel,
93 71 csantifort
input      [3:0]            i_rm_sel_nxt,
94
input      [3:0]            i_rds_sel_nxt,
95
input      [3:0]            i_rn_sel_nxt,
96 2 csantifort
input      [1:0]            i_barrel_shift_amount_sel,
97
input      [1:0]            i_barrel_shift_data_sel,
98
input      [1:0]            i_barrel_shift_function,
99
input      [8:0]            i_alu_function,
100
input      [1:0]            i_multiply_function,
101
input      [2:0]            i_interrupt_vector_sel,
102
input      [3:0]            i_address_sel,
103
input      [1:0]            i_pc_sel,
104
input      [1:0]            i_byte_enable_sel,
105
input      [2:0]            i_status_bits_sel,
106
input      [2:0]            i_reg_write_sel,
107
input                       i_user_mode_regs_load,
108
input                       i_user_mode_regs_store_nxt,
109
input                       i_firq_not_user_mode,
110
 
111
input                       i_write_data_wen,
112
input                       i_base_address_wen,     // save LDM base address register, 
113
                                                    // in case of data abort
114
input                       i_pc_wen,
115
input      [14:0]           i_reg_bank_wen,
116 71 csantifort
input      [3:0]            i_reg_bank_wsel,
117 2 csantifort
input                       i_status_bits_flags_wen,
118
input                       i_status_bits_mode_wen,
119
input                       i_status_bits_irq_mask_wen,
120
input                       i_status_bits_firq_mask_wen,
121
input                       i_copro_write_data_wen
122
 
123
);
124
 
125 82 csantifort
`include "a23_localparams.vh"
126
`include "a23_functions.vh"
127 2 csantifort
 
128
// ========================================================
129
// Internal signals
130
// ========================================================
131
wire [31:0]         write_data_nxt;
132
wire [3:0]          byte_enable_nxt;
133
wire [31:0]         pc_plus4;
134
wire [31:0]         pc_minus4;
135
wire [31:0]         address_plus4;
136
wire [31:0]         alu_plus4;
137
wire [31:0]         rn_plus4;
138
wire [31:0]         alu_out;
139
wire [3:0]          alu_flags;
140
wire [31:0]         rm;
141
wire [31:0]         rs;
142
wire [31:0]         rd;
143
wire [31:0]         rn;
144
wire [31:0]         pc;
145
wire [31:0]         pc_nxt;
146
wire                write_enable_nxt;
147
wire [31:0]         interrupt_vector;
148
wire [7:0]          shift_amount;
149
wire [31:0]         barrel_shift_in;
150
wire [31:0]         barrel_shift_out;
151
wire                barrel_shift_carry;
152
 
153
wire [3:0]          status_bits_flags_nxt;
154
reg  [3:0]          status_bits_flags = 'd0;
155
wire [1:0]          status_bits_mode_nxt;
156 71 csantifort
wire [1:0]          status_bits_mode_nr;
157 2 csantifort
reg  [1:0]          status_bits_mode = SVC;
158 71 csantifort
                    // raw rs select
159
wire [1:0]          status_bits_mode_rds_nxt;
160
wire [1:0]          status_bits_mode_rds_nr;
161
reg  [1:0]          status_bits_mode_rds;
162 2 csantifort
                    // one-hot encoded rs select
163
wire [3:0]          status_bits_mode_rds_oh_nxt;
164
reg  [3:0]          status_bits_mode_rds_oh = 1'd1 << OH_SVC;
165
wire                status_bits_mode_rds_oh_update;
166
wire                status_bits_irq_mask_nxt;
167
reg                 status_bits_irq_mask = 1'd1;
168
wire                status_bits_firq_mask_nxt;
169
reg                 status_bits_firq_mask = 1'd1;
170
 
171
wire                execute;           // high when condition execution is true
172
wire [31:0]         reg_write_nxt;
173
wire                pc_wen;
174
wire [14:0]         reg_bank_wen;
175 71 csantifort
wire [3:0]          reg_bank_wsel;
176 2 csantifort
wire [31:0]         multiply_out;
177
wire [1:0]          multiply_flags;
178
reg  [31:0]         base_address = 'd0;    // Saves base address during LDM instruction in 
179
                                           // case of data abort
180
 
181
wire                priviledged_nxt;
182
wire                priviledged_update;
183
wire                address_update;
184
wire                base_address_update;
185
wire                write_data_update;
186
wire                copro_write_data_update;
187
wire                byte_enable_update;
188
wire                data_access_update;
189
wire                write_enable_update;
190
wire                exclusive_update;
191
wire                status_bits_flags_update;
192
wire                status_bits_mode_update;
193
wire                status_bits_irq_mask_update;
194
wire                status_bits_firq_mask_update;
195 82 csantifort
wire [1:0]          status_bits_out;
196 2 csantifort
 
197
wire [31:0]         alu_out_pc_filtered;
198
wire                adex_nxt;
199
 
200 83 csantifort
wire                carry_in;
201
 
202
 
203 2 csantifort
// ========================================================
204
// Status Bits in PC register
205
// ========================================================
206 82 csantifort
assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && execute) ?
207 54 csantifort
                            alu_out[1:0] : status_bits_mode ;
208
 
209
 
210 2 csantifort
assign o_status_bits = {   status_bits_flags,           // 31:28
211
                           status_bits_irq_mask,        // 7
212
                           status_bits_firq_mask,       // 6
213
                           24'd0,
214 54 csantifort
                           status_bits_out};          // 1:0 = mode
215 2 csantifort
 
216
// ========================================================
217
// Status Bits Select
218
// ========================================================
219
assign status_bits_flags_nxt     = i_status_bits_sel == 3'd0 ? alu_flags                           :
220
                                   i_status_bits_sel == 3'd1 ? alu_out          [31:28]            :
221
                                   i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28]            :
222 82 csantifort
                                   //  update flags after a multiply operation
223
                                   i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } :
224
                                   // regops that do not change the overflow flag
225
                                   i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } :
226
                                                               4'b1111 ;
227 2 csantifort
 
228
assign status_bits_mode_nxt      = i_status_bits_sel == 3'd0 ? i_status_bits_mode       :
229 82 csantifort
                                   i_status_bits_sel == 3'd5 ? i_status_bits_mode       :
230 2 csantifort
                                   i_status_bits_sel == 3'd1 ? alu_out            [1:0] :
231
                                                               i_copro_read_data  [1:0] ;
232
 
233
 
234
// Used for the Rds output of register_bank - this special version of
235
// status_bits_mode speeds up the critical path from status_bits_mode through the
236
// register_bank, barrel_shifter and alu. It moves a mux needed for the
237
// i_user_mode_regs_store_nxt signal back into the previous stage -
238
// so its really part of the decode stage even though the logic is right here
239
// In addition the signal is one-hot encoded to further speed up the logic
240 71 csantifort
// Raw version is also kept for ram-based register bank implementation.
241 2 csantifort
 
242 72 csantifort
assign status_bits_mode_rds_nxt  = i_user_mode_regs_store_nxt ? USR                  :
243 71 csantifort
                                   status_bits_mode_update    ? status_bits_mode_nxt :
244
                                                                status_bits_mode     ;
245 2 csantifort
 
246 71 csantifort
assign status_bits_mode_rds_oh_nxt    = oh_status_bits_mode(status_bits_mode_rds_nxt);
247
 
248
 
249 2 csantifort
assign status_bits_irq_mask_nxt  = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask      :
250 82 csantifort
                                   i_status_bits_sel == 3'd5 ? i_status_bits_irq_mask      :
251 2 csantifort
                                   i_status_bits_sel == 3'd1 ? alu_out                [27] :
252
                                                               i_copro_read_data      [27] ;
253
 
254
assign status_bits_firq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask     :
255 82 csantifort
                                   i_status_bits_sel == 3'd5 ? i_status_bits_firq_mask     :
256 2 csantifort
                                   i_status_bits_sel == 3'd1 ? alu_out                [26] :
257
                                                               i_copro_read_data      [26] ;
258
 
259
 
260
 
261
// ========================================================
262
// Adders
263
// ========================================================
264
assign pc_plus4      = pc        + 32'd4;
265
assign pc_minus4     = pc        - 32'd4;
266
assign address_plus4 = o_address + 32'd4;
267
assign alu_plus4     = alu_out   + 32'd4;
268
assign rn_plus4      = rn        + 32'd4;
269
 
270
// ========================================================
271
// Barrel Shift Amount Select
272
// ========================================================
273
// An immediate shift value of 0 is translated into 32
274
assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0                           :
275 82 csantifort
                      i_barrel_shift_amount_sel == 2'd1 ? rs[7:0]                        :
276 2 csantifort
                      i_barrel_shift_amount_sel == 2'd2 ? {3'd0, i_imm_shift_amount    } :
277
                                                          {3'd0, i_read_data_alignment } ;
278
 
279
// ========================================================
280
// Barrel Shift Data Select
281
// ========================================================
282
assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32       :
283
                         i_barrel_shift_data_sel == 2'd1 ? i_read_data   :
284
                                                           rm            ;
285
 
286
// ========================================================
287
// Interrupt vector Select
288
// ========================================================
289
 
290
assign interrupt_vector = // Reset vector
291
                          (i_interrupt_vector_sel == 3'd0) ? 32'h00000000 :
292
                          // Data abort interrupt vector                 
293
                          (i_interrupt_vector_sel == 3'd1) ? 32'h00000010 :
294
                          // Fast interrupt vector  
295
                          (i_interrupt_vector_sel == 3'd2) ? 32'h0000001c :
296
                          // Regular interrupt vector
297
                          (i_interrupt_vector_sel == 3'd3) ? 32'h00000018 :
298
                          // Prefetch abort interrupt vector
299
                          (i_interrupt_vector_sel == 3'd5) ? 32'h0000000c :
300
                          // Undefined instruction interrupt vector
301
                          (i_interrupt_vector_sel == 3'd6) ? 32'h00000004 :
302
                          // Software (SWI) interrupt vector
303
                          (i_interrupt_vector_sel == 3'd7) ? 32'h00000008 :
304
                          // Default is the address exception interrupt
305
                                                             32'h00000014 ;
306
 
307
 
308
// ========================================================
309
// Address Select
310
// ========================================================
311
 
312
// If rd is the pc, then seperate the address bits from the status bits for
313
// generating the next address to fetch
314
assign alu_out_pc_filtered = pc_wen && i_pc_sel == 2'd1 ? pcf(alu_out) : alu_out;
315
 
316
// if current instruction does not execute because it does not meet the condition
317
// then address advances to next instruction
318
assign o_address_nxt = (!execute)              ? pc_plus4              :
319
                       (i_address_sel == 4'd0) ? pc_plus4              :
320
                       (i_address_sel == 4'd1) ? alu_out_pc_filtered   :
321
                       (i_address_sel == 4'd2) ? interrupt_vector      :
322
                       (i_address_sel == 4'd3) ? pc                    :
323
                       (i_address_sel == 4'd4) ? rn                    :
324
                       (i_address_sel == 4'd5) ? address_plus4         :  // MTRANS address incrementer
325
                       (i_address_sel == 4'd6) ? alu_plus4             :  // MTRANS decrement after
326
                                                 rn_plus4              ;  // MTRANS increment before
327
 
328
// Data accesses use 32-bit address space, but instruction
329
// accesses are restricted to 26 bit space
330
assign adex_nxt      = |o_address_nxt[31:26] && !i_data_access_exec;
331
 
332
// ========================================================
333
// Program Counter Select
334
// ========================================================
335
// If current instruction does not execute because it does not meet the condition
336
// then PC advances to next instruction
337
assign pc_nxt = (!execute)       ? pc_plus4              :
338
                i_pc_sel == 2'd0 ? pc_plus4              :
339
                i_pc_sel == 2'd1 ? alu_out               :
340
                                   interrupt_vector      ;
341
 
342
 
343
// ========================================================
344
// Register Write Select
345
// ========================================================
346
wire [31:0] save_int_pc;
347
wire [31:0] save_int_pc_m4;
348
 
349
assign save_int_pc    = { status_bits_flags,
350
                          status_bits_irq_mask,
351
                          status_bits_firq_mask,
352
                          pc[25:2],
353
                          status_bits_mode      };
354
 
355
 
356
assign save_int_pc_m4 = { status_bits_flags,
357
                          status_bits_irq_mask,
358
                          status_bits_firq_mask,
359
                          pc_minus4[25:2],
360
                          status_bits_mode      };
361
 
362
 
363
assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out               :
364
                       // save pc to lr on an interrupt                    
365
                       i_reg_write_sel == 3'd1 ? save_int_pc_m4        :
366
                       // to update Rd at the end of Multiplication
367
                       i_reg_write_sel == 3'd2 ? multiply_out          :
368
                       i_reg_write_sel == 3'd3 ? o_status_bits         :
369
                       i_reg_write_sel == 3'd5 ? i_copro_read_data     :  // mrc
370
                       i_reg_write_sel == 3'd6 ? base_address          :
371
                                                 save_int_pc           ;
372
 
373
 
374
// ========================================================
375
// Byte Enable Select
376
// ========================================================
377
assign byte_enable_nxt = i_byte_enable_sel == 2'd0  ? 4'b1111 :  // word write
378
                         i_byte_enable_sel == 2'd2  ?            // halfword write
379
                         ( o_address_nxt[1] == 1'd0 ? 4'b0011 :
380
                                                      4'b1100  ) :
381
 
382
                         o_address_nxt[1:0] == 2'd0 ? 4'b0001 :  // byte write
383
                         o_address_nxt[1:0] == 2'd1 ? 4'b0010 :
384
                         o_address_nxt[1:0] == 2'd2 ? 4'b0100 :
385
                                                      4'b1000 ;
386
 
387
 
388
// ========================================================
389
// Write Data Select
390
// ========================================================
391
assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd            :
392
                                                    {4{rd[ 7:0]}} ;
393
 
394
 
395
// ========================================================
396
// Conditional Execution
397
// ========================================================
398
assign execute = conditional_execute ( i_condition, status_bits_flags );
399
 
400
// allow the PC to increment to the next instruction when current
401
// instruction does not execute
402
assign pc_wen       = i_pc_wen || !execute;
403
 
404
// only update register bank if current instruction executes
405
assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
406
 
407 71 csantifort
assign reg_bank_wsel = {{4{~execute}} | i_reg_bank_wsel};
408 2 csantifort
 
409 71 csantifort
 
410 2 csantifort
// ========================================================
411
// Priviledged output flag
412
// ========================================================
413
// Need to look at status_bits_mode_nxt so switch to priviledged mode
414
// at the same time as assert interrupt vector address
415
assign priviledged_nxt  = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ;
416
 
417
 
418
// ========================================================
419
// Write Enable
420
// ========================================================
421
// This must be de-asserted when execute is fault
422
assign write_enable_nxt = execute && i_write_data_wen;
423
 
424
 
425
// ========================================================
426
// Register Update
427
// ========================================================
428
 
429
assign priviledged_update              = !i_fetch_stall;
430
assign data_access_update              = !i_fetch_stall && execute;
431
assign write_enable_update             = !i_fetch_stall;
432
assign write_data_update               = !i_fetch_stall && execute && i_write_data_wen;
433
assign exclusive_update                = !i_fetch_stall && execute;
434
assign address_update                  = !i_fetch_stall;
435
assign byte_enable_update              = !i_fetch_stall && execute && i_write_data_wen;
436
assign copro_write_data_update         = !i_fetch_stall && execute && i_copro_write_data_wen;
437
 
438
assign base_address_update             = !i_fetch_stall && execute && i_base_address_wen;
439
assign status_bits_flags_update        = !i_fetch_stall && execute && i_status_bits_flags_wen;
440
assign status_bits_mode_update         = !i_fetch_stall && execute && i_status_bits_mode_wen;
441
assign status_bits_mode_rds_oh_update  = !i_fetch_stall;
442
assign status_bits_irq_mask_update     = !i_fetch_stall && execute && i_status_bits_irq_mask_wen;
443
assign status_bits_firq_mask_update    = !i_fetch_stall && execute && i_status_bits_firq_mask_wen;
444
 
445 71 csantifort
assign status_bits_mode_rds_nr         =  status_bits_mode_rds_oh_update ? status_bits_mode_rds_nxt :
446
                                                                           status_bits_mode_rds     ;
447 2 csantifort
 
448 71 csantifort
assign status_bits_mode_nr             =  status_bits_mode_update        ? status_bits_mode_nxt     :
449
                                                                           status_bits_mode         ;
450
 
451 2 csantifort
always @( posedge i_clk )
452
    begin
453
    o_priviledged           <= priviledged_update             ? priviledged_nxt              : o_priviledged;
454
    o_exclusive             <= exclusive_update               ? i_exclusive_exec             : o_exclusive;
455
    o_data_access           <= data_access_update             ? i_data_access_exec           : o_data_access;
456
    o_write_enable          <= write_enable_update            ? write_enable_nxt             : o_write_enable;
457
    o_write_data            <= write_data_update              ? write_data_nxt               : o_write_data;
458
    o_address               <= address_update                 ? o_address_nxt                : o_address;
459
    o_adex                  <= address_update                 ? adex_nxt                     : o_adex;
460
    o_address_valid         <= address_update                 ? 1'd1                         : o_address_valid;
461
    o_byte_enable           <= byte_enable_update             ? byte_enable_nxt              : o_byte_enable;
462
    o_copro_write_data      <= copro_write_data_update        ? write_data_nxt               : o_copro_write_data;
463
 
464
    base_address            <= base_address_update            ? rn                           : base_address;
465
 
466
    status_bits_flags       <= status_bits_flags_update       ? status_bits_flags_nxt        : status_bits_flags;
467 71 csantifort
    status_bits_mode        <=  status_bits_mode_nr;
468 2 csantifort
    status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt  : status_bits_mode_rds_oh;
469 71 csantifort
    status_bits_mode_rds    <= status_bits_mode_rds_nr;
470 2 csantifort
    status_bits_irq_mask    <= status_bits_irq_mask_update    ? status_bits_irq_mask_nxt     : status_bits_irq_mask;
471
    status_bits_firq_mask   <= status_bits_firq_mask_update   ? status_bits_firq_mask_nxt    : status_bits_firq_mask;
472
    end
473
 
474
 
475
// ========================================================
476
// Instantiate Barrel Shift
477
// ========================================================
478 83 csantifort
 
479
assign carry_in = i_use_carry_in ? status_bits_flags[1] : 1'd0;
480
 
481 74 csantifort
`ifndef ALTERA_FPGA
482 15 csantifort
a23_barrel_shift u_barrel_shift  (
483 74 csantifort
`else
484
a23_barrel_shift_fpga u_barrel_shift  (
485
`endif
486 2 csantifort
    .i_in             ( barrel_shift_in           ),
487 83 csantifort
    .i_carry_in       ( carry_in                  ),
488 2 csantifort
    .i_shift_amount   ( shift_amount              ),
489
    .i_shift_imm_zero ( i_shift_imm_zero          ),
490
    .i_function       ( i_barrel_shift_function   ),
491
 
492
    .o_out            ( barrel_shift_out          ),
493
    .o_carry_out      ( barrel_shift_carry        )
494
);
495
 
496
 
497 87 csantifort
wire barrel_shift_carry_real;
498
assign barrel_shift_carry_real =  i_barrel_shift_data_sel == 2'd0 ?
499
                                      (i_imm_shift_amount[4:1] == 0 ? status_bits_flags[1] : i_imm32[31]) :
500
                                      barrel_shift_carry;
501
 
502 2 csantifort
// ========================================================
503
// Instantiate ALU
504
// ========================================================
505 15 csantifort
a23_alu u_alu (
506 2 csantifort
    .i_a_in                 ( rn                    ),
507
    .i_b_in                 ( barrel_shift_out      ),
508 87 csantifort
    //.i_barrel_shift_carry   ( barrel_shift_carry    ),
509
    .i_barrel_shift_carry   ( barrel_shift_carry_real    ),
510 2 csantifort
    .i_status_bits_carry    ( status_bits_flags[1]  ),
511
    .i_function             ( i_alu_function        ),
512
 
513
    .o_out                  ( alu_out               ),
514
    .o_flags                ( alu_flags             )
515
);
516
 
517
 
518
// ========================================================
519
// Instantiate Booth 64-bit Multiplier-Accumulator
520
// ========================================================
521 15 csantifort
a23_multiply u_multiply (
522 2 csantifort
    .i_clk          ( i_clk                 ),
523
    .i_fetch_stall  ( i_fetch_stall         ),
524
    .i_a_in         ( rs                    ),
525
    .i_b_in         ( rm                    ),
526
    .i_function     ( i_multiply_function   ),
527
    .i_execute      ( execute               ),
528
    .o_out          ( multiply_out          ),
529
    .o_flags        ( multiply_flags        ),  // [1] = N, [0] = Z
530
    .o_done         ( o_multiply_done       )
531
);
532
 
533
 
534
// ========================================================
535
// Instantiate Register Bank
536
// ========================================================
537 73 csantifort
`ifndef A23_RAM_REGISTER_BANK
538 15 csantifort
a23_register_bank u_register_bank(
539 2 csantifort
    .i_clk                   ( i_clk                     ),
540
    .i_fetch_stall           ( i_fetch_stall             ),
541
    .i_rm_sel                ( i_rm_sel                  ),
542
    .i_rds_sel               ( i_rds_sel                 ),
543
    .i_rn_sel                ( i_rn_sel                  ),
544
    .i_pc_wen                ( pc_wen                    ),
545
    .i_reg_bank_wen          ( reg_bank_wen              ),
546
    .i_pc                    ( pc_nxt[25:2]              ),
547
    .i_reg                   ( reg_write_nxt             ),
548
    .i_mode_idec             ( i_status_bits_mode        ),
549
    .i_mode_exec             ( status_bits_mode          ),
550
 
551
    .i_status_bits_flags     ( status_bits_flags         ),
552
    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
553
    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
554
 
555
    // pre-encoded in decode stage to speed up long path
556
    .i_firq_not_user_mode    ( i_firq_not_user_mode      ),
557
 
558
    // use one-hot version for speed, combine with i_user_mode_regs_store
559
    .i_mode_rds_exec         ( status_bits_mode_rds_oh   ),
560
 
561
    .i_user_mode_regs_load   ( i_user_mode_regs_load     ),
562
    .o_rm                    ( rm                        ),
563
    .o_rs                    ( rs                        ),
564
    .o_rd                    ( rd                        ),
565
    .o_rn                    ( rn                        ),
566
    .o_pc                    ( pc                        )
567
);
568 73 csantifort
`else
569
a23_ram_register_bank u_register_bank(
570
    .i_clk                   ( i_clk                     ),
571
    .i_fetch_stall           ( i_fetch_stall             ),
572
    .i_rm_sel                ( i_rm_sel_nxt              ),
573
    .i_rds_sel               ( i_rds_sel_nxt             ),
574
    .i_rn_sel                ( i_rn_sel_nxt              ),
575
    .i_pc_wen                ( pc_wen                    ),
576
    .i_reg_bank_wsel         ( reg_bank_wsel             ),
577
    .i_pc                    ( pc_nxt[25:2]              ),
578
    .i_reg                   ( reg_write_nxt             ),
579 2 csantifort
 
580 73 csantifort
    .i_mode_exec_nxt         ( status_bits_mode_nr       ),
581
    .i_mode_exec             ( status_bits_mode          ),
582
    .i_mode_rds_exec         ( status_bits_mode_rds_nr   ),
583
    .i_user_mode_regs_load   ( i_user_mode_regs_load     ),
584 2 csantifort
 
585 73 csantifort
    .i_status_bits_flags     ( status_bits_flags         ),
586
    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
587
    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
588
 
589
    .o_rm                    ( rm                        ),
590
    .o_rs                    ( rs                        ),
591
    .o_rd                    ( rd                        ),
592
    .o_rn                    ( rn                        ),
593
    .o_pc                    ( pc                        )
594
);
595
`endif
596
 
597 2 csantifort
// ========================================================
598
// Debug - non-synthesizable code
599
// ========================================================
600
//synopsys translate_off
601
 
602
wire    [(2*8)-1:0]    xCONDITION;
603
wire    [(4*8)-1:0]    xMODE;
604
 
605
assign  xCONDITION           = i_condition == EQ ? "EQ"  :
606
                               i_condition == NE ? "NE"  :
607
                               i_condition == CS ? "CS"  :
608
                               i_condition == CC ? "CC"  :
609
                               i_condition == MI ? "MI"  :
610
                               i_condition == PL ? "PL"  :
611
                               i_condition == VS ? "VS"  :
612
                               i_condition == VC ? "VC"  :
613
                               i_condition == HI ? "HI"  :
614
                               i_condition == LS ? "LS"  :
615
                               i_condition == GE ? "GE"  :
616
                               i_condition == LT ? "LT"  :
617
                               i_condition == GT ? "GT"  :
618
                               i_condition == LE ? "LE"  :
619
                               i_condition == AL ? "AL"  :
620
                                                   "NV " ;
621
 
622
assign  xMODE  =  status_bits_mode == SVC  ? "SVC"  :
623
                  status_bits_mode == IRQ  ? "IRQ"  :
624
                  status_bits_mode == FIRQ ? "FIRQ" :
625
                  status_bits_mode == USR  ? "USR"  :
626
                                             "XXX"  ;
627
 
628
 
629
//synopsys translate_on
630
 
631
endmodule
632
 
633
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.