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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_execute.v] - Blame information for rev 88

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1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Execute stage of Amber 2 Core                               //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Executes instructions. Instantiates the register file, ALU  //
10
//  multiplication unit and barrel shifter. This stage is       //
11
//  relitively simple. All the complex stuff is done in the     //
12
//  decode stage.                                               //
13
//                                                              //
14
//  Author(s):                                                  //
15
//      - Conor Santifort, csantifort.amber@gmail.com           //
16
//                                                              //
17
//////////////////////////////////////////////////////////////////
18
//                                                              //
19
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
20
//                                                              //
21
// This source file may be used and distributed without         //
22
// restriction provided that this copyright statement is not    //
23
// removed from the file and that any derivative work contains  //
24
// the original copyright notice and the associated disclaimer. //
25
//                                                              //
26
// This source file is free software; you can redistribute it   //
27
// and/or modify it under the terms of the GNU Lesser General   //
28
// Public License as published by the Free Software Foundation; //
29
// either version 2.1 of the License, or (at your option) any   //
30
// later version.                                               //
31
//                                                              //
32
// This source is distributed in the hope that it will be       //
33
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
34
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
35
// PURPOSE.  See the GNU Lesser General Public License for more //
36
// details.                                                     //
37
//                                                              //
38
// You should have received a copy of the GNU Lesser General    //
39
// Public License along with this source; if not, download it   //
40
// from http://www.opencores.org/lgpl.shtml                     //
41
//                                                              //
42
//////////////////////////////////////////////////////////////////
43
 
44 82 csantifort
`include "a23_config_defines.vh"
45 2 csantifort
 
46 15 csantifort
module a23_execute (
47 2 csantifort
 
48
input                       i_clk,
49
input       [31:0]          i_read_data,
50
input       [4:0]           i_read_data_alignment,  // 2 LSBs of address in [4:3], appended 
51
                                                    // with 3 zeros
52
input       [31:0]          i_copro_read_data,      // From Co-Processor, to either Register 
53
                                                    // or Memory
54
input                       i_data_access_exec,     // from Instruction Decode stage
55
                                                    // high means the memory access is a read 
56
                                                    // read or write, low for instruction
57
 
58
output reg  [31:0]          o_copro_write_data = 'd0,
59
output reg  [31:0]          o_write_data = 'd0,
60
output reg  [31:0]          o_address = 32'hdead_dead,
61
output reg                  o_adex = 'd0,           // Address Exception
62
output reg                  o_address_valid = 'd0,  // Prevents the reset address value being a 
63
                                                    // wishbone access
64
output      [31:0]          o_address_nxt,          // un-registered version of address to the 
65
                                                    // cache rams address ports
66
output reg                  o_priviledged = 'd0,    // Priviledged access
67
output reg                  o_exclusive = 'd0,      // swap access
68
output reg                  o_write_enable = 'd0,
69
output reg  [3:0]           o_byte_enable = 'd0,
70
output reg                  o_data_access = 'd0,    // To Fetch stage. high = data fetch, 
71
                                                    // low = instruction fetch
72
output      [31:0]          o_status_bits,          // Full PC will all status bits, but PC part zero'ed out
73
output                      o_multiply_done,
74
 
75
 
76
// --------------------------------------------------
77
// Control signals from Instruction Decode stage
78
// --------------------------------------------------
79
input                       i_fetch_stall,          // stall all stages of the cpu at the same time
80
input      [1:0]            i_status_bits_mode,
81
input                       i_status_bits_irq_mask,
82
input                       i_status_bits_firq_mask,
83
input      [31:0]           i_imm32,
84
input      [4:0]            i_imm_shift_amount,
85
input                       i_shift_imm_zero,
86
input      [3:0]            i_condition,
87
input                       i_exclusive_exec,       // swap access
88 83 csantifort
input                       i_use_carry_in,         // e.g. add with carry instruction
89 2 csantifort
 
90
input      [3:0]            i_rm_sel,
91
input      [3:0]            i_rds_sel,
92
input      [3:0]            i_rn_sel,
93 71 csantifort
input      [3:0]            i_rm_sel_nxt,
94
input      [3:0]            i_rds_sel_nxt,
95
input      [3:0]            i_rn_sel_nxt,
96 2 csantifort
input      [1:0]            i_barrel_shift_amount_sel,
97
input      [1:0]            i_barrel_shift_data_sel,
98
input      [1:0]            i_barrel_shift_function,
99
input      [8:0]            i_alu_function,
100
input      [1:0]            i_multiply_function,
101
input      [2:0]            i_interrupt_vector_sel,
102
input      [3:0]            i_address_sel,
103
input      [1:0]            i_pc_sel,
104
input      [1:0]            i_byte_enable_sel,
105
input      [2:0]            i_status_bits_sel,
106
input      [2:0]            i_reg_write_sel,
107
input                       i_user_mode_regs_load,
108
input                       i_user_mode_regs_store_nxt,
109
input                       i_firq_not_user_mode,
110
 
111
input                       i_write_data_wen,
112
input                       i_base_address_wen,     // save LDM base address register, 
113
                                                    // in case of data abort
114
input                       i_pc_wen,
115
input      [14:0]           i_reg_bank_wen,
116 71 csantifort
input      [3:0]            i_reg_bank_wsel,
117 2 csantifort
input                       i_status_bits_flags_wen,
118
input                       i_status_bits_mode_wen,
119
input                       i_status_bits_irq_mask_wen,
120
input                       i_status_bits_firq_mask_wen,
121
input                       i_copro_write_data_wen
122
 
123
);
124
 
125 82 csantifort
`include "a23_localparams.vh"
126
`include "a23_functions.vh"
127 2 csantifort
 
128
// ========================================================
129
// Internal signals
130
// ========================================================
131
wire [31:0]         write_data_nxt;
132
wire [3:0]          byte_enable_nxt;
133
wire [31:0]         pc_plus4;
134
wire [31:0]         pc_minus4;
135
wire [31:0]         address_plus4;
136
wire [31:0]         alu_plus4;
137
wire [31:0]         rn_plus4;
138
wire [31:0]         alu_out;
139
wire [3:0]          alu_flags;
140
wire [31:0]         rm;
141
wire [31:0]         rs;
142
wire [31:0]         rd;
143
wire [31:0]         rn;
144
wire [31:0]         pc;
145
wire [31:0]         pc_nxt;
146
wire                write_enable_nxt;
147
wire [31:0]         interrupt_vector;
148
wire [7:0]          shift_amount;
149
wire [31:0]         barrel_shift_in;
150
wire [31:0]         barrel_shift_out;
151
wire                barrel_shift_carry;
152 88 csantifort
wire                barrel_shift_carry_alu;
153 2 csantifort
 
154
wire [3:0]          status_bits_flags_nxt;
155
reg  [3:0]          status_bits_flags = 'd0;
156
wire [1:0]          status_bits_mode_nxt;
157 71 csantifort
wire [1:0]          status_bits_mode_nr;
158 2 csantifort
reg  [1:0]          status_bits_mode = SVC;
159 71 csantifort
                    // raw rs select
160
wire [1:0]          status_bits_mode_rds_nxt;
161
wire [1:0]          status_bits_mode_rds_nr;
162
reg  [1:0]          status_bits_mode_rds;
163 2 csantifort
                    // one-hot encoded rs select
164
wire [3:0]          status_bits_mode_rds_oh_nxt;
165
reg  [3:0]          status_bits_mode_rds_oh = 1'd1 << OH_SVC;
166
wire                status_bits_mode_rds_oh_update;
167
wire                status_bits_irq_mask_nxt;
168
reg                 status_bits_irq_mask = 1'd1;
169
wire                status_bits_firq_mask_nxt;
170
reg                 status_bits_firq_mask = 1'd1;
171
 
172
wire                execute;           // high when condition execution is true
173
wire [31:0]         reg_write_nxt;
174
wire                pc_wen;
175
wire [14:0]         reg_bank_wen;
176 71 csantifort
wire [3:0]          reg_bank_wsel;
177 2 csantifort
wire [31:0]         multiply_out;
178
wire [1:0]          multiply_flags;
179
reg  [31:0]         base_address = 'd0;    // Saves base address during LDM instruction in 
180
                                           // case of data abort
181
 
182
wire                priviledged_nxt;
183
wire                priviledged_update;
184
wire                address_update;
185
wire                base_address_update;
186
wire                write_data_update;
187
wire                copro_write_data_update;
188
wire                byte_enable_update;
189
wire                data_access_update;
190
wire                write_enable_update;
191
wire                exclusive_update;
192
wire                status_bits_flags_update;
193
wire                status_bits_mode_update;
194
wire                status_bits_irq_mask_update;
195
wire                status_bits_firq_mask_update;
196 82 csantifort
wire [1:0]          status_bits_out;
197 2 csantifort
 
198
wire [31:0]         alu_out_pc_filtered;
199
wire                adex_nxt;
200
 
201 83 csantifort
wire                carry_in;
202
 
203
 
204 2 csantifort
// ========================================================
205
// Status Bits in PC register
206
// ========================================================
207 82 csantifort
assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && execute) ?
208 54 csantifort
                            alu_out[1:0] : status_bits_mode ;
209
 
210
 
211 2 csantifort
assign o_status_bits = {   status_bits_flags,           // 31:28
212
                           status_bits_irq_mask,        // 7
213
                           status_bits_firq_mask,       // 6
214
                           24'd0,
215 54 csantifort
                           status_bits_out};          // 1:0 = mode
216 2 csantifort
 
217
// ========================================================
218
// Status Bits Select
219
// ========================================================
220
assign status_bits_flags_nxt     = i_status_bits_sel == 3'd0 ? alu_flags                           :
221
                                   i_status_bits_sel == 3'd1 ? alu_out          [31:28]            :
222
                                   i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28]            :
223 82 csantifort
                                   //  update flags after a multiply operation
224
                                   i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } :
225
                                   // regops that do not change the overflow flag
226
                                   i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } :
227
                                                               4'b1111 ;
228 2 csantifort
 
229
assign status_bits_mode_nxt      = i_status_bits_sel == 3'd0 ? i_status_bits_mode       :
230 82 csantifort
                                   i_status_bits_sel == 3'd5 ? i_status_bits_mode       :
231 2 csantifort
                                   i_status_bits_sel == 3'd1 ? alu_out            [1:0] :
232
                                                               i_copro_read_data  [1:0] ;
233
 
234
 
235
// Used for the Rds output of register_bank - this special version of
236
// status_bits_mode speeds up the critical path from status_bits_mode through the
237
// register_bank, barrel_shifter and alu. It moves a mux needed for the
238
// i_user_mode_regs_store_nxt signal back into the previous stage -
239
// so its really part of the decode stage even though the logic is right here
240
// In addition the signal is one-hot encoded to further speed up the logic
241 71 csantifort
// Raw version is also kept for ram-based register bank implementation.
242 2 csantifort
 
243 72 csantifort
assign status_bits_mode_rds_nxt  = i_user_mode_regs_store_nxt ? USR                  :
244 71 csantifort
                                   status_bits_mode_update    ? status_bits_mode_nxt :
245
                                                                status_bits_mode     ;
246 2 csantifort
 
247 71 csantifort
assign status_bits_mode_rds_oh_nxt    = oh_status_bits_mode(status_bits_mode_rds_nxt);
248
 
249
 
250 2 csantifort
assign status_bits_irq_mask_nxt  = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask      :
251 82 csantifort
                                   i_status_bits_sel == 3'd5 ? i_status_bits_irq_mask      :
252 2 csantifort
                                   i_status_bits_sel == 3'd1 ? alu_out                [27] :
253
                                                               i_copro_read_data      [27] ;
254
 
255
assign status_bits_firq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask     :
256 82 csantifort
                                   i_status_bits_sel == 3'd5 ? i_status_bits_firq_mask     :
257 2 csantifort
                                   i_status_bits_sel == 3'd1 ? alu_out                [26] :
258
                                                               i_copro_read_data      [26] ;
259
 
260
 
261
 
262
// ========================================================
263
// Adders
264
// ========================================================
265
assign pc_plus4      = pc        + 32'd4;
266
assign pc_minus4     = pc        - 32'd4;
267
assign address_plus4 = o_address + 32'd4;
268
assign alu_plus4     = alu_out   + 32'd4;
269
assign rn_plus4      = rn        + 32'd4;
270
 
271
// ========================================================
272
// Barrel Shift Amount Select
273
// ========================================================
274
// An immediate shift value of 0 is translated into 32
275
assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0                           :
276 82 csantifort
                      i_barrel_shift_amount_sel == 2'd1 ? rs[7:0]                        :
277 2 csantifort
                      i_barrel_shift_amount_sel == 2'd2 ? {3'd0, i_imm_shift_amount    } :
278
                                                          {3'd0, i_read_data_alignment } ;
279
 
280
// ========================================================
281
// Barrel Shift Data Select
282
// ========================================================
283
assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32       :
284
                         i_barrel_shift_data_sel == 2'd1 ? i_read_data   :
285
                                                           rm            ;
286
 
287
// ========================================================
288
// Interrupt vector Select
289
// ========================================================
290
 
291
assign interrupt_vector = // Reset vector
292
                          (i_interrupt_vector_sel == 3'd0) ? 32'h00000000 :
293
                          // Data abort interrupt vector                 
294
                          (i_interrupt_vector_sel == 3'd1) ? 32'h00000010 :
295
                          // Fast interrupt vector  
296
                          (i_interrupt_vector_sel == 3'd2) ? 32'h0000001c :
297
                          // Regular interrupt vector
298
                          (i_interrupt_vector_sel == 3'd3) ? 32'h00000018 :
299
                          // Prefetch abort interrupt vector
300
                          (i_interrupt_vector_sel == 3'd5) ? 32'h0000000c :
301
                          // Undefined instruction interrupt vector
302
                          (i_interrupt_vector_sel == 3'd6) ? 32'h00000004 :
303
                          // Software (SWI) interrupt vector
304
                          (i_interrupt_vector_sel == 3'd7) ? 32'h00000008 :
305
                          // Default is the address exception interrupt
306
                                                             32'h00000014 ;
307
 
308
 
309
// ========================================================
310
// Address Select
311
// ========================================================
312
 
313
// If rd is the pc, then seperate the address bits from the status bits for
314
// generating the next address to fetch
315
assign alu_out_pc_filtered = pc_wen && i_pc_sel == 2'd1 ? pcf(alu_out) : alu_out;
316
 
317
// if current instruction does not execute because it does not meet the condition
318
// then address advances to next instruction
319
assign o_address_nxt = (!execute)              ? pc_plus4              :
320
                       (i_address_sel == 4'd0) ? pc_plus4              :
321
                       (i_address_sel == 4'd1) ? alu_out_pc_filtered   :
322
                       (i_address_sel == 4'd2) ? interrupt_vector      :
323
                       (i_address_sel == 4'd3) ? pc                    :
324
                       (i_address_sel == 4'd4) ? rn                    :
325
                       (i_address_sel == 4'd5) ? address_plus4         :  // MTRANS address incrementer
326
                       (i_address_sel == 4'd6) ? alu_plus4             :  // MTRANS decrement after
327
                                                 rn_plus4              ;  // MTRANS increment before
328
 
329
// Data accesses use 32-bit address space, but instruction
330
// accesses are restricted to 26 bit space
331
assign adex_nxt      = |o_address_nxt[31:26] && !i_data_access_exec;
332
 
333
// ========================================================
334
// Program Counter Select
335
// ========================================================
336
// If current instruction does not execute because it does not meet the condition
337
// then PC advances to next instruction
338
assign pc_nxt = (!execute)       ? pc_plus4              :
339
                i_pc_sel == 2'd0 ? pc_plus4              :
340
                i_pc_sel == 2'd1 ? alu_out               :
341
                                   interrupt_vector      ;
342
 
343
 
344
// ========================================================
345
// Register Write Select
346
// ========================================================
347
wire [31:0] save_int_pc;
348
wire [31:0] save_int_pc_m4;
349
 
350
assign save_int_pc    = { status_bits_flags,
351
                          status_bits_irq_mask,
352
                          status_bits_firq_mask,
353
                          pc[25:2],
354
                          status_bits_mode      };
355
 
356
 
357
assign save_int_pc_m4 = { status_bits_flags,
358
                          status_bits_irq_mask,
359
                          status_bits_firq_mask,
360
                          pc_minus4[25:2],
361
                          status_bits_mode      };
362
 
363
 
364
assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out               :
365
                       // save pc to lr on an interrupt                    
366
                       i_reg_write_sel == 3'd1 ? save_int_pc_m4        :
367
                       // to update Rd at the end of Multiplication
368
                       i_reg_write_sel == 3'd2 ? multiply_out          :
369
                       i_reg_write_sel == 3'd3 ? o_status_bits         :
370
                       i_reg_write_sel == 3'd5 ? i_copro_read_data     :  // mrc
371
                       i_reg_write_sel == 3'd6 ? base_address          :
372
                                                 save_int_pc           ;
373
 
374
 
375
// ========================================================
376
// Byte Enable Select
377
// ========================================================
378
assign byte_enable_nxt = i_byte_enable_sel == 2'd0  ? 4'b1111 :  // word write
379
                         i_byte_enable_sel == 2'd2  ?            // halfword write
380
                         ( o_address_nxt[1] == 1'd0 ? 4'b0011 :
381
                                                      4'b1100  ) :
382
 
383
                         o_address_nxt[1:0] == 2'd0 ? 4'b0001 :  // byte write
384
                         o_address_nxt[1:0] == 2'd1 ? 4'b0010 :
385
                         o_address_nxt[1:0] == 2'd2 ? 4'b0100 :
386
                                                      4'b1000 ;
387
 
388
 
389
// ========================================================
390
// Write Data Select
391
// ========================================================
392
assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd            :
393
                                                    {4{rd[ 7:0]}} ;
394
 
395
 
396
// ========================================================
397
// Conditional Execution
398
// ========================================================
399
assign execute = conditional_execute ( i_condition, status_bits_flags );
400
 
401
// allow the PC to increment to the next instruction when current
402
// instruction does not execute
403
assign pc_wen       = i_pc_wen || !execute;
404
 
405
// only update register bank if current instruction executes
406
assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
407
 
408 71 csantifort
assign reg_bank_wsel = {{4{~execute}} | i_reg_bank_wsel};
409 2 csantifort
 
410 71 csantifort
 
411 2 csantifort
// ========================================================
412
// Priviledged output flag
413
// ========================================================
414
// Need to look at status_bits_mode_nxt so switch to priviledged mode
415
// at the same time as assert interrupt vector address
416
assign priviledged_nxt  = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ;
417
 
418
 
419
// ========================================================
420
// Write Enable
421
// ========================================================
422
// This must be de-asserted when execute is fault
423
assign write_enable_nxt = execute && i_write_data_wen;
424
 
425
 
426
// ========================================================
427
// Register Update
428
// ========================================================
429
 
430
assign priviledged_update              = !i_fetch_stall;
431
assign data_access_update              = !i_fetch_stall && execute;
432
assign write_enable_update             = !i_fetch_stall;
433
assign write_data_update               = !i_fetch_stall && execute && i_write_data_wen;
434
assign exclusive_update                = !i_fetch_stall && execute;
435
assign address_update                  = !i_fetch_stall;
436
assign byte_enable_update              = !i_fetch_stall && execute && i_write_data_wen;
437
assign copro_write_data_update         = !i_fetch_stall && execute && i_copro_write_data_wen;
438
 
439
assign base_address_update             = !i_fetch_stall && execute && i_base_address_wen;
440
assign status_bits_flags_update        = !i_fetch_stall && execute && i_status_bits_flags_wen;
441
assign status_bits_mode_update         = !i_fetch_stall && execute && i_status_bits_mode_wen;
442
assign status_bits_mode_rds_oh_update  = !i_fetch_stall;
443
assign status_bits_irq_mask_update     = !i_fetch_stall && execute && i_status_bits_irq_mask_wen;
444
assign status_bits_firq_mask_update    = !i_fetch_stall && execute && i_status_bits_firq_mask_wen;
445
 
446 71 csantifort
assign status_bits_mode_rds_nr         =  status_bits_mode_rds_oh_update ? status_bits_mode_rds_nxt :
447
                                                                           status_bits_mode_rds     ;
448 2 csantifort
 
449 71 csantifort
assign status_bits_mode_nr             =  status_bits_mode_update        ? status_bits_mode_nxt     :
450
                                                                           status_bits_mode         ;
451
 
452 2 csantifort
always @( posedge i_clk )
453
    begin
454
    o_priviledged           <= priviledged_update             ? priviledged_nxt              : o_priviledged;
455
    o_exclusive             <= exclusive_update               ? i_exclusive_exec             : o_exclusive;
456
    o_data_access           <= data_access_update             ? i_data_access_exec           : o_data_access;
457
    o_write_enable          <= write_enable_update            ? write_enable_nxt             : o_write_enable;
458
    o_write_data            <= write_data_update              ? write_data_nxt               : o_write_data;
459
    o_address               <= address_update                 ? o_address_nxt                : o_address;
460
    o_adex                  <= address_update                 ? adex_nxt                     : o_adex;
461
    o_address_valid         <= address_update                 ? 1'd1                         : o_address_valid;
462
    o_byte_enable           <= byte_enable_update             ? byte_enable_nxt              : o_byte_enable;
463
    o_copro_write_data      <= copro_write_data_update        ? write_data_nxt               : o_copro_write_data;
464
 
465
    base_address            <= base_address_update            ? rn                           : base_address;
466
 
467
    status_bits_flags       <= status_bits_flags_update       ? status_bits_flags_nxt        : status_bits_flags;
468 71 csantifort
    status_bits_mode        <=  status_bits_mode_nr;
469 2 csantifort
    status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt  : status_bits_mode_rds_oh;
470 71 csantifort
    status_bits_mode_rds    <= status_bits_mode_rds_nr;
471 2 csantifort
    status_bits_irq_mask    <= status_bits_irq_mask_update    ? status_bits_irq_mask_nxt     : status_bits_irq_mask;
472
    status_bits_firq_mask   <= status_bits_firq_mask_update   ? status_bits_firq_mask_nxt    : status_bits_firq_mask;
473
    end
474
 
475
 
476
// ========================================================
477
// Instantiate Barrel Shift
478
// ========================================================
479 83 csantifort
 
480
assign carry_in = i_use_carry_in ? status_bits_flags[1] : 1'd0;
481
 
482 74 csantifort
`ifndef ALTERA_FPGA
483 15 csantifort
a23_barrel_shift u_barrel_shift  (
484 74 csantifort
`else
485
a23_barrel_shift_fpga u_barrel_shift  (
486
`endif
487 2 csantifort
    .i_in             ( barrel_shift_in           ),
488 83 csantifort
    .i_carry_in       ( carry_in                  ),
489 2 csantifort
    .i_shift_amount   ( shift_amount              ),
490
    .i_shift_imm_zero ( i_shift_imm_zero          ),
491
    .i_function       ( i_barrel_shift_function   ),
492
 
493
    .o_out            ( barrel_shift_out          ),
494 88 csantifort
    .o_carry_out      ( barrel_shift_carry        ));
495 2 csantifort
 
496
 
497 87 csantifort
 
498 2 csantifort
// ========================================================
499
// Instantiate ALU
500
// ========================================================
501 88 csantifort
assign barrel_shift_carry_alu =  i_barrel_shift_data_sel == 2'd0 ?
502
                                  (i_imm_shift_amount[4:1] == 0 ? status_bits_flags[1] : i_imm32[31]) :
503
                                   barrel_shift_carry;
504
 
505 15 csantifort
a23_alu u_alu (
506 88 csantifort
    .i_a_in                 ( rn                      ),
507
    .i_b_in                 ( barrel_shift_out        ),
508
    .i_barrel_shift_carry   ( barrel_shift_carry_alu  ),
509
    .i_status_bits_carry    ( status_bits_flags[1]    ),
510
    .i_function             ( i_alu_function          ),
511
 
512
    .o_out                  ( alu_out                 ),
513
    .o_flags                ( alu_flags               ));
514 2 csantifort
 
515
 
516
 
517
// ========================================================
518
// Instantiate Booth 64-bit Multiplier-Accumulator
519
// ========================================================
520 15 csantifort
a23_multiply u_multiply (
521 2 csantifort
    .i_clk          ( i_clk                 ),
522
    .i_fetch_stall  ( i_fetch_stall         ),
523
    .i_a_in         ( rs                    ),
524
    .i_b_in         ( rm                    ),
525
    .i_function     ( i_multiply_function   ),
526
    .i_execute      ( execute               ),
527
    .o_out          ( multiply_out          ),
528
    .o_flags        ( multiply_flags        ),  // [1] = N, [0] = Z
529
    .o_done         ( o_multiply_done       )
530
);
531
 
532
 
533
// ========================================================
534
// Instantiate Register Bank
535
// ========================================================
536 73 csantifort
`ifndef A23_RAM_REGISTER_BANK
537 15 csantifort
a23_register_bank u_register_bank(
538 2 csantifort
    .i_clk                   ( i_clk                     ),
539
    .i_fetch_stall           ( i_fetch_stall             ),
540
    .i_rm_sel                ( i_rm_sel                  ),
541
    .i_rds_sel               ( i_rds_sel                 ),
542
    .i_rn_sel                ( i_rn_sel                  ),
543
    .i_pc_wen                ( pc_wen                    ),
544
    .i_reg_bank_wen          ( reg_bank_wen              ),
545
    .i_pc                    ( pc_nxt[25:2]              ),
546
    .i_reg                   ( reg_write_nxt             ),
547
    .i_mode_idec             ( i_status_bits_mode        ),
548
    .i_mode_exec             ( status_bits_mode          ),
549
 
550
    .i_status_bits_flags     ( status_bits_flags         ),
551
    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
552
    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
553
 
554
    // pre-encoded in decode stage to speed up long path
555
    .i_firq_not_user_mode    ( i_firq_not_user_mode      ),
556
 
557
    // use one-hot version for speed, combine with i_user_mode_regs_store
558
    .i_mode_rds_exec         ( status_bits_mode_rds_oh   ),
559
 
560
    .i_user_mode_regs_load   ( i_user_mode_regs_load     ),
561
    .o_rm                    ( rm                        ),
562
    .o_rs                    ( rs                        ),
563
    .o_rd                    ( rd                        ),
564
    .o_rn                    ( rn                        ),
565
    .o_pc                    ( pc                        )
566
);
567 73 csantifort
`else
568
a23_ram_register_bank u_register_bank(
569
    .i_clk                   ( i_clk                     ),
570
    .i_fetch_stall           ( i_fetch_stall             ),
571
    .i_rm_sel                ( i_rm_sel_nxt              ),
572
    .i_rds_sel               ( i_rds_sel_nxt             ),
573
    .i_rn_sel                ( i_rn_sel_nxt              ),
574
    .i_pc_wen                ( pc_wen                    ),
575
    .i_reg_bank_wsel         ( reg_bank_wsel             ),
576
    .i_pc                    ( pc_nxt[25:2]              ),
577
    .i_reg                   ( reg_write_nxt             ),
578 2 csantifort
 
579 73 csantifort
    .i_mode_exec_nxt         ( status_bits_mode_nr       ),
580
    .i_mode_exec             ( status_bits_mode          ),
581
    .i_mode_rds_exec         ( status_bits_mode_rds_nr   ),
582
    .i_user_mode_regs_load   ( i_user_mode_regs_load     ),
583 2 csantifort
 
584 73 csantifort
    .i_status_bits_flags     ( status_bits_flags         ),
585
    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
586
    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
587
 
588
    .o_rm                    ( rm                        ),
589
    .o_rs                    ( rs                        ),
590
    .o_rd                    ( rd                        ),
591
    .o_rn                    ( rn                        ),
592
    .o_pc                    ( pc                        )
593
);
594
`endif
595
 
596 2 csantifort
// ========================================================
597
// Debug - non-synthesizable code
598
// ========================================================
599
//synopsys translate_off
600
 
601
wire    [(2*8)-1:0]    xCONDITION;
602
wire    [(4*8)-1:0]    xMODE;
603
 
604
assign  xCONDITION           = i_condition == EQ ? "EQ"  :
605
                               i_condition == NE ? "NE"  :
606
                               i_condition == CS ? "CS"  :
607
                               i_condition == CC ? "CC"  :
608
                               i_condition == MI ? "MI"  :
609
                               i_condition == PL ? "PL"  :
610
                               i_condition == VS ? "VS"  :
611
                               i_condition == VC ? "VC"  :
612
                               i_condition == HI ? "HI"  :
613
                               i_condition == LS ? "LS"  :
614
                               i_condition == GE ? "GE"  :
615
                               i_condition == LT ? "LT"  :
616
                               i_condition == GT ? "GT"  :
617
                               i_condition == LE ? "LE"  :
618
                               i_condition == AL ? "AL"  :
619
                                                   "NV " ;
620
 
621
assign  xMODE  =  status_bits_mode == SVC  ? "SVC"  :
622
                  status_bits_mode == IRQ  ? "IRQ"  :
623
                  status_bits_mode == FIRQ ? "FIRQ" :
624
                  status_bits_mode == USR  ? "USR"  :
625
                                             "XXX"  ;
626
 
627
 
628
//synopsys translate_on
629
 
630
endmodule
631
 
632
 

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