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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_register_bank.v] - Blame information for rev 15

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1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Register Bank for Amber Core                                //
4
//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Contains 37 32-bit registers, 16 of which are visible       //
10
//  ina any one operating mode. Registers use real flipflops,   //
11
//  rather than SRAM. This makes sense for an FPGA              //
12
//  implementation, where flipflops are plentiful.              //
13
//                                                              //
14
//  Author(s):                                                  //
15
//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
17
//////////////////////////////////////////////////////////////////
18
//                                                              //
19
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
24
// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
43
 
44 15 csantifort
module a23_register_bank (
45 2 csantifort
 
46
input                       i_clk,
47
input                       i_fetch_stall,
48
 
49
input       [1:0]           i_mode_idec,            // user, supervisor, irq_idec, firq_idec etc.
50
                                                    // Used for register writes
51
input       [1:0]           i_mode_exec,            // 1 periods delayed from i_mode_idec
52
                                                    // Used for register reads
53
input       [3:0]           i_mode_rds_exec,        // Use one-hot version specifically for rds, 
54
                                                    // includes i_user_mode_regs_store
55
input                       i_user_mode_regs_load,
56
input                       i_firq_not_user_mode,
57
input       [3:0]           i_rm_sel,
58
input       [3:0]           i_rds_sel,
59
input       [3:0]           i_rn_sel,
60
 
61
input                       i_pc_wen,
62
input       [14:0]          i_reg_bank_wen,
63
 
64
input       [23:0]          i_pc,                   // program counter [25:2]
65
input       [31:0]          i_reg,
66
 
67
input       [3:0]           i_status_bits_flags,
68
input                       i_status_bits_irq_mask,
69
input                       i_status_bits_firq_mask,
70
 
71
output      [31:0]          o_rm,
72
output reg  [31:0]          o_rs,
73
output reg  [31:0]          o_rd,
74
output      [31:0]          o_rn,
75
output      [31:0]          o_pc
76
 
77
);
78
 
79 15 csantifort
`include "a23_localparams.v"
80
`include "a23_functions.v"
81 2 csantifort
 
82
 
83
// User Mode Registers
84
reg  [31:0] r0  = 32'hdead_beef;
85
reg  [31:0] r1  = 32'hdead_beef;
86
reg  [31:0] r2  = 32'hdead_beef;
87
reg  [31:0] r3  = 32'hdead_beef;
88
reg  [31:0] r4  = 32'hdead_beef;
89
reg  [31:0] r5  = 32'hdead_beef;
90
reg  [31:0] r6  = 32'hdead_beef;
91
reg  [31:0] r7  = 32'hdead_beef;
92
reg  [31:0] r8  = 32'hdead_beef;
93
reg  [31:0] r9  = 32'hdead_beef;
94
reg  [31:0] r10 = 32'hdead_beef;
95
reg  [31:0] r11 = 32'hdead_beef;
96
reg  [31:0] r12 = 32'hdead_beef;
97
reg  [31:0] r13 = 32'hdead_beef;
98
reg  [31:0] r14 = 32'hdead_beef;
99
reg  [23:0] r15 = 24'hc0_ffee;
100
 
101
wire  [31:0] r0_out;
102
wire  [31:0] r1_out;
103
wire  [31:0] r2_out;
104
wire  [31:0] r3_out;
105
wire  [31:0] r4_out;
106
wire  [31:0] r5_out;
107
wire  [31:0] r6_out;
108
wire  [31:0] r7_out;
109
wire  [31:0] r8_out;
110
wire  [31:0] r9_out;
111
wire  [31:0] r10_out;
112
wire  [31:0] r11_out;
113
wire  [31:0] r12_out;
114
wire  [31:0] r13_out;
115
wire  [31:0] r14_out;
116
wire  [31:0] r15_out_rm;
117
wire  [31:0] r15_out_rm_nxt;
118
wire  [31:0] r15_out_rn;
119
 
120
wire  [31:0] r8_rds;
121
wire  [31:0] r9_rds;
122
wire  [31:0] r10_rds;
123
wire  [31:0] r11_rds;
124
wire  [31:0] r12_rds;
125
wire  [31:0] r13_rds;
126
wire  [31:0] r14_rds;
127
 
128
// Supervisor Mode Registers
129
reg  [31:0] r13_svc = 32'hdead_beef;
130
reg  [31:0] r14_svc = 32'hdead_beef;
131
 
132
// Interrupt Mode Registers
133
reg  [31:0] r13_irq = 32'hdead_beef;
134
reg  [31:0] r14_irq = 32'hdead_beef;
135
 
136
// Fast Interrupt Mode Registers
137
reg  [31:0] r8_firq  = 32'hdead_beef;
138
reg  [31:0] r9_firq  = 32'hdead_beef;
139
reg  [31:0] r10_firq = 32'hdead_beef;
140
reg  [31:0] r11_firq = 32'hdead_beef;
141
reg  [31:0] r12_firq = 32'hdead_beef;
142
reg  [31:0] r13_firq = 32'hdead_beef;
143
reg  [31:0] r14_firq = 32'hdead_beef;
144
 
145
wire        usr_exec;
146
wire        svc_exec;
147
wire        irq_exec;
148
wire        firq_exec;
149
 
150
wire        usr_idec;
151
wire        svc_idec;
152
wire        irq_idec;
153
wire        firq_idec;
154
 
155
    // Write Enables from execute stage
156
assign usr_idec  =  i_user_mode_regs_load || i_mode_idec == USR;
157
assign svc_idec  = !i_user_mode_regs_load && i_mode_idec == SVC;
158
assign irq_idec  = !i_user_mode_regs_load && i_mode_idec == IRQ;
159
 
160
// pre-encoded in decode stage to speed up long path
161
assign firq_idec = i_firq_not_user_mode;
162
 
163
    // Read Enables from stage 1 (fetch)
164
assign usr_exec  = i_mode_exec == USR;
165
assign svc_exec  = i_mode_exec == SVC;
166
assign irq_exec  = i_mode_exec == IRQ;
167
assign firq_exec = i_mode_exec == FIRQ;
168
 
169
 
170
// ========================================================
171
// Register Update
172
// ========================================================
173
always @ ( posedge i_clk )
174
    if (!i_fetch_stall)
175
        begin
176
        r0       <=  i_reg_bank_wen[0 ]              ? i_reg : r0;
177
        r1       <=  i_reg_bank_wen[1 ]              ? i_reg : r1;
178
        r2       <=  i_reg_bank_wen[2 ]              ? i_reg : r2;
179
        r3       <=  i_reg_bank_wen[3 ]              ? i_reg : r3;
180
        r4       <=  i_reg_bank_wen[4 ]              ? i_reg : r4;
181
        r5       <=  i_reg_bank_wen[5 ]              ? i_reg : r5;
182
        r6       <=  i_reg_bank_wen[6 ]              ? i_reg : r6;
183
        r7       <=  i_reg_bank_wen[7 ]              ? i_reg : r7;
184
 
185
        r8       <= (i_reg_bank_wen[8 ] && !firq_idec) ? i_reg : r8;
186
        r9       <= (i_reg_bank_wen[9 ] && !firq_idec) ? i_reg : r9;
187
        r10      <= (i_reg_bank_wen[10] && !firq_idec) ? i_reg : r10;
188
        r11      <= (i_reg_bank_wen[11] && !firq_idec) ? i_reg : r11;
189
        r12      <= (i_reg_bank_wen[12] && !firq_idec) ? i_reg : r12;
190
 
191
        r8_firq  <= (i_reg_bank_wen[8 ] &&  firq_idec) ? i_reg : r8_firq;
192
        r9_firq  <= (i_reg_bank_wen[9 ] &&  firq_idec) ? i_reg : r9_firq;
193
        r10_firq <= (i_reg_bank_wen[10] &&  firq_idec) ? i_reg : r10_firq;
194
        r11_firq <= (i_reg_bank_wen[11] &&  firq_idec) ? i_reg : r11_firq;
195
        r12_firq <= (i_reg_bank_wen[12] &&  firq_idec) ? i_reg : r12_firq;
196
 
197
        r13      <= (i_reg_bank_wen[13] &&  usr_idec)  ? i_reg : r13;
198
        r14      <= (i_reg_bank_wen[14] &&  usr_idec)  ? i_reg : r14;
199
 
200
        r13_svc  <= (i_reg_bank_wen[13] &&  svc_idec)  ? i_reg : r13_svc;
201
        r14_svc  <= (i_reg_bank_wen[14] &&  svc_idec)  ? i_reg : r14_svc;
202
 
203
        r13_irq  <= (i_reg_bank_wen[13] &&  irq_idec)  ? i_reg : r13_irq;
204
        r14_irq  <= (i_reg_bank_wen[14] &&  irq_idec)  ? i_reg : r14_irq;
205
 
206
        r13_firq <= (i_reg_bank_wen[13] &&  firq_idec) ? i_reg : r13_firq;
207
        r14_firq <= (i_reg_bank_wen[14] &&  firq_idec) ? i_reg : r14_firq;
208
 
209
        r15      <=  i_pc_wen                          ?  i_pc : r15;
210
        end
211
 
212
 
213
// ========================================================
214
// Register Read based on Mode
215
// ========================================================
216
assign r0_out = r0;
217
assign r1_out = r1;
218
assign r2_out = r2;
219
assign r3_out = r3;
220
assign r4_out = r4;
221
assign r5_out = r5;
222
assign r6_out = r6;
223
assign r7_out = r7;
224
 
225
assign r8_out  = firq_exec ? r8_firq  : r8;
226
assign r9_out  = firq_exec ? r9_firq  : r9;
227
assign r10_out = firq_exec ? r10_firq : r10;
228
assign r11_out = firq_exec ? r11_firq : r11;
229
assign r12_out = firq_exec ? r12_firq : r12;
230
 
231
assign r13_out = usr_exec ? r13      :
232
                 svc_exec ? r13_svc  :
233
                 irq_exec ? r13_irq  :
234
                          r13_firq ;
235
 
236
assign r14_out = usr_exec ? r14      :
237
                 svc_exec ? r14_svc  :
238
                 irq_exec ? r14_irq  :
239
                          r14_firq ;
240
 
241
 
242
assign r15_out_rm     = { i_status_bits_flags,
243
                          i_status_bits_irq_mask,
244
                          i_status_bits_firq_mask,
245
                          r15,
246
                          i_mode_exec};
247
 
248
assign r15_out_rm_nxt = { i_status_bits_flags,
249
                          i_status_bits_irq_mask,
250
                          i_status_bits_firq_mask,
251
                          i_pc,
252
                          i_mode_exec};
253
 
254
assign r15_out_rn     = {6'd0, r15, 2'd0};
255
 
256
 
257
// rds outputs
258
assign r8_rds  = i_mode_rds_exec[OH_FIRQ] ? r8_firq  : r8;
259
assign r9_rds  = i_mode_rds_exec[OH_FIRQ] ? r9_firq  : r9;
260
assign r10_rds = i_mode_rds_exec[OH_FIRQ] ? r10_firq : r10;
261
assign r11_rds = i_mode_rds_exec[OH_FIRQ] ? r11_firq : r11;
262
assign r12_rds = i_mode_rds_exec[OH_FIRQ] ? r12_firq : r12;
263
 
264
assign r13_rds = i_mode_rds_exec[OH_USR]  ? r13      :
265
                 i_mode_rds_exec[OH_SVC]  ? r13_svc  :
266
                 i_mode_rds_exec[OH_IRQ]  ? r13_irq  :
267
                                            r13_firq ;
268
 
269
assign r14_rds = i_mode_rds_exec[OH_USR]  ? r14      :
270
                 i_mode_rds_exec[OH_SVC]  ? r14_svc  :
271
                 i_mode_rds_exec[OH_IRQ]  ? r14_irq  :
272
                                            r14_firq ;
273
 
274
// ========================================================
275
// Program Counter out
276
// ========================================================
277
assign o_pc = r15_out_rn;
278
 
279
// ========================================================
280
// Rm Selector
281
// ========================================================
282
assign o_rm = i_rm_sel == 4'd0  ? r0_out  :
283
              i_rm_sel == 4'd1  ? r1_out  :
284
              i_rm_sel == 4'd2  ? r2_out  :
285
              i_rm_sel == 4'd3  ? r3_out  :
286
              i_rm_sel == 4'd4  ? r4_out  :
287
              i_rm_sel == 4'd5  ? r5_out  :
288
              i_rm_sel == 4'd6  ? r6_out  :
289
              i_rm_sel == 4'd7  ? r7_out  :
290
              i_rm_sel == 4'd8  ? r8_out  :
291
              i_rm_sel == 4'd9  ? r9_out  :
292
              i_rm_sel == 4'd10 ? r10_out :
293
              i_rm_sel == 4'd11 ? r11_out :
294
              i_rm_sel == 4'd12 ? r12_out :
295
              i_rm_sel == 4'd13 ? r13_out :
296
              i_rm_sel == 4'd14 ? r14_out :
297
                                  r15_out_rm ;
298
 
299
 
300
 
301
 
302
// ========================================================
303
// Rds Selector
304
// ========================================================
305
always @*
306
    case (i_rds_sel)
307
       4'd0  :  o_rs = r0_out  ;
308
       4'd1  :  o_rs = r1_out  ;
309
       4'd2  :  o_rs = r2_out  ;
310
       4'd3  :  o_rs = r3_out  ;
311
       4'd4  :  o_rs = r4_out  ;
312
       4'd5  :  o_rs = r5_out  ;
313
       4'd6  :  o_rs = r6_out  ;
314
       4'd7  :  o_rs = r7_out  ;
315
       4'd8  :  o_rs = r8_rds  ;
316
       4'd9  :  o_rs = r9_rds  ;
317
       4'd10 :  o_rs = r10_rds ;
318
       4'd11 :  o_rs = r11_rds ;
319
       4'd12 :  o_rs = r12_rds ;
320
       4'd13 :  o_rs = r13_rds ;
321
       4'd14 :  o_rs = r14_rds ;
322
       4'd15 :  o_rs = r15_out_rn ;
323
       default: o_rs = r15_out_rn ;
324
    endcase
325
 
326
 
327
 
328
// ========================================================
329
// Rd Selector
330
// ========================================================
331
always @*
332
    case (i_rds_sel)
333
       4'd0  :  o_rd = r0_out  ;
334
       4'd1  :  o_rd = r1_out  ;
335
       4'd2  :  o_rd = r2_out  ;
336
       4'd3  :  o_rd = r3_out  ;
337
       4'd4  :  o_rd = r4_out  ;
338
       4'd5  :  o_rd = r5_out  ;
339
       4'd6  :  o_rd = r6_out  ;
340
       4'd7  :  o_rd = r7_out  ;
341
       4'd8  :  o_rd = r8_rds  ;
342
       4'd9  :  o_rd = r9_rds  ;
343
       4'd10 :  o_rd = r10_rds ;
344
       4'd11 :  o_rd = r11_rds ;
345
       4'd12 :  o_rd = r12_rds ;
346
       4'd13 :  o_rd = r13_rds ;
347
       4'd14 :  o_rd = r14_rds ;
348
       4'd15 :  o_rd = r15_out_rm_nxt ;
349
       default: o_rd = r15_out_rm_nxt ;
350
    endcase
351
 
352
 
353
// ========================================================
354
// Rn Selector
355
// ========================================================
356
assign o_rn = i_rn_sel == 4'd0  ? r0_out  :
357
              i_rn_sel == 4'd1  ? r1_out  :
358
              i_rn_sel == 4'd2  ? r2_out  :
359
              i_rn_sel == 4'd3  ? r3_out  :
360
              i_rn_sel == 4'd4  ? r4_out  :
361
              i_rn_sel == 4'd5  ? r5_out  :
362
              i_rn_sel == 4'd6  ? r6_out  :
363
              i_rn_sel == 4'd7  ? r7_out  :
364
              i_rn_sel == 4'd8  ? r8_out  :
365
              i_rn_sel == 4'd9  ? r9_out  :
366
              i_rn_sel == 4'd10 ? r10_out :
367
              i_rn_sel == 4'd11 ? r11_out :
368
              i_rn_sel == 4'd12 ? r12_out :
369
              i_rn_sel == 4'd13 ? r13_out :
370
              i_rn_sel == 4'd14 ? r14_out :
371
                                  r15_out_rn ;
372
 
373
 
374
endmodule
375
 
376
 

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