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//////////////////////////////////////////////////////////////////
//                                                              //
//  Wishbone master interface for the Amber core                //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Turns memory access requests from the execute stage and     //
//  cache into wishbone bus cycles. For 4-word read requests    //
//  from the cache and swap accesses ( read followed by write   //
//  to the same address) from the execute stage,                //
//  a block transfer is done. All other requests result in      //
//  single word transfers.                                      //
//                                                              //
//  Write accesses can be done in a single clock cycle on       //
//  the wishbone bus, is the destination allows it. The         //
//  next transfer will begin immediately on the                 //
//  next cycle on the bus. This looks like a block transfer     //
//  and does hold ownership of the wishbone bus, preventing     //
//  the other master ( the ethernet MAC) from gaining           //
//  ownership between those two cycles. But otherwise it would  //
//  be necessary to insert a wait cycle after every write,      //
//  slowing down the performance of the core by around 5 to     //
//  10%.                                                        //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
 
module a23_wishbone
(
input                       i_clk,
 
// Core Accesses to Wishbone bus
input                       i_select,
input       [31:0]          i_write_data,
input                       i_write_enable,
input       [3:0]           i_byte_enable,    // valid for writes only
input                       i_data_access,
input                       i_exclusive,      // high for read part of swap access
input       [31:0]          i_address,
output                      o_stall,
 
// Cache Accesses to Wishbone bus
input                       i_cache_req,
 
// Wishbone Bus
output reg  [31:0]          o_wb_adr = 'd0,
output reg  [3:0]           o_wb_sel = 'd0,
output reg                  o_wb_we  = 'd0,
input       [31:0]          i_wb_dat,
output reg  [31:0]          o_wb_dat = 'd0,
output reg                  o_wb_cyc = 'd0,
output reg                  o_wb_stb = 'd0,
input                       i_wb_ack,
input                       i_wb_err
 
);
 
 
localparam [3:0] WB_IDLE            = 3'd0,
                 WB_BURST1          = 3'd1,
                 WB_BURST2          = 3'd2,
                 WB_BURST3          = 3'd3,
                 WB_WAIT_ACK        = 3'd4;
 
reg     [2:0]               wishbone_st = WB_IDLE;
 
wire                        core_read_request;
wire                        core_write_request;
wire                        cache_read_request;
wire                        cache_write_request;
wire                        start_access;
reg                         servicing_cache = 'd0;
wire    [3:0]               byte_enable;
reg                         exclusive_access = 'd0;
wire                        read_ack;
wire                        wait_write_ack;
wire                        wb_wait;
 
// Write buffer
reg     [31:0]              wbuf_data_r = 'd0;
reg     [31:0]              wbuf_addr_r = 'd0;
reg     [3:0]               wbuf_sel_r  = 'd0;
reg                         wbuf_busy_r = 'd0;
 
 
assign read_ack             = !o_wb_we && i_wb_ack;
assign o_stall              = ( core_read_request  && !read_ack )       ||
                              ( core_read_request  && servicing_cache ) ||
                              ( core_write_request && servicing_cache ) ||
                              ( core_write_request && wishbone_st == WB_WAIT_ACK) ||
                              ( cache_write_request && wishbone_st == WB_WAIT_ACK) ||
                              wbuf_busy_r;
 
                              // Don't stall on writes
                              // Wishbone is doing burst read so make core wait to execute the write
                              // ( core_write_request && !i_wb_ack )  ;
 
assign core_read_request    = i_select && !i_write_enable;
assign core_write_request   = i_select &&  i_write_enable;
 
assign cache_read_request   = i_cache_req && !i_write_enable;
assign cache_write_request  = i_cache_req &&  i_write_enable;
 
assign wb_wait              = o_wb_stb && !i_wb_ack;
assign start_access         = (core_read_request || core_write_request || i_cache_req) && !wb_wait ;
 
// For writes the byte enable is always 4'hf
assign byte_enable          = wbuf_busy_r                                   ? wbuf_sel_r    :
                              ( core_write_request || cache_write_request ) ? i_byte_enable :
                                                                              4'hf          ;
 
 
 
// ======================================
// Write buffer
// ======================================
 
 
always @( posedge i_clk )
    if ( wb_wait && !wbuf_busy_r && (core_write_request || cache_write_request) )
        begin
        wbuf_data_r <= i_write_data;
        wbuf_addr_r <= i_address;
        wbuf_sel_r  <= i_byte_enable;
        wbuf_busy_r <= 1'd1;
        end
    else if (!o_wb_stb)
        wbuf_busy_r <= 1'd0;
 
// ======================================
// Register Accesses
// ======================================
always @( posedge i_clk )
    if ( start_access )
        o_wb_dat <= i_write_data;
 
 
assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
 
 
always @( posedge i_clk )
    case ( wishbone_st )
        WB_IDLE :
            begin
 
            if ( start_access )
                begin
                o_wb_stb            <= 1'd1;
                o_wb_cyc            <= 1'd1;
                o_wb_sel            <= byte_enable;
                end
            else if ( !wait_write_ack )
                begin
                o_wb_stb            <= 1'd0;
 
                // Hold cyc high after an exclusive access
                // to hold ownership of the wishbone bus
                o_wb_cyc            <= exclusive_access;
                end
 
            // cache has priority over the core                     
            servicing_cache <= cache_read_request && !wait_write_ack;
 
            if ( wait_write_ack )
                begin
                // still waiting for last (write) access to complete
                wishbone_st      <= WB_WAIT_ACK;
                end
            // do a burst of 4 read to fill a cache line                   
            else if ( cache_read_request )
                begin
                wishbone_st         <= WB_BURST1;
                exclusive_access    <= 1'd0;
                end
            else if ( core_read_request )
                begin
                wishbone_st         <= WB_WAIT_ACK;
                exclusive_access    <= i_exclusive;
                end
           // The core does not currently issue exclusive write requests
           // but there's no reason why this might not be added some
           // time in the future so allow for it here
            else if ( core_write_request )
                exclusive_access <= i_exclusive;
 
 
            if ( start_access )
                begin
                if (wbuf_busy_r)
                    begin
                    o_wb_we              <= 1'd1;
                    o_wb_adr[31:2]       <= wbuf_addr_r[31:2];
                    end
                else
                    begin
                    o_wb_we              <= core_write_request || cache_write_request;
                    // only update these on new wb access to make debug easier
                    o_wb_adr[31:2]       <= i_address[31:2];
                    end
 
                o_wb_adr[1:0]        <= byte_enable == 4'b0001 ? 2'd0 :
                                        byte_enable == 4'b0010 ? 2'd1 :
                                        byte_enable == 4'b0100 ? 2'd2 :
                                        byte_enable == 4'b1000 ? 2'd3 :
 
                                        byte_enable == 4'b0011 ? 2'd0 :
                                        byte_enable == 4'b1100 ? 2'd2 :
 
                                                                 2'd0 ;
                end
            end
 
 
        // Read burst, wait for first ack
        WB_BURST1:
            if ( i_wb_ack )
                begin
                // burst of 4 that wraps
                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1'd1;
                wishbone_st     <= WB_BURST2;
                end
 
 
        // Read burst, wait for second ack
        WB_BURST2:
            if ( i_wb_ack )
                begin
                // burst of 4 that wraps
                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1'd1;
                wishbone_st     <= WB_BURST3;
                end
 
 
        // Read burst, wait for third ack
        WB_BURST3:
            if ( i_wb_ack )
                begin
                // burst of 4 that wraps
                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1'd1;
                wishbone_st     <= WB_WAIT_ACK;
                end
 
 
        // Wait for the wishbone ack to be asserted
        WB_WAIT_ACK:
            if ( i_wb_ack )
                begin
                wishbone_st         <= WB_IDLE;
                o_wb_stb            <= 1'd0;
                o_wb_cyc            <= exclusive_access;
                o_wb_we             <= 1'd0;
                servicing_cache     <= 1'd0;
                end
 
    endcase
 
 
 
// ========================================================
// Debug Wishbone bus - not synthesizable
// ========================================================
//synopsys translate_off
wire    [(14*8)-1:0]   xAS_STATE;
 
 
assign xAS_STATE  = wishbone_st == WB_IDLE       ? "WB_IDLE"       :
                    wishbone_st == WB_BURST1     ? "WB_BURST1"     :
                    wishbone_st == WB_BURST2     ? "WB_BURST2"     :
                    wishbone_st == WB_BURST3     ? "WB_BURST3"     :
                    wishbone_st == WB_WAIT_ACK   ? "WB_WAIT_ACK"   :
                                                      "UNKNOWN"       ;
 
//synopsys translate_on
 
endmodule
 

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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_wishbone.v] - Blame information for rev 47

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Wishbone master interface for the Amber core //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Turns memory access requests from the execute stage and //`
10			`// cache into wishbone bus cycles. For 4-word read requests //`
11			`// from the cache and swap accesses ( read followed by write //`
12			`// to the same address) from the execute stage, //`
13			`// a block transfer is done. All other requests result in //`
14			`// single word transfers. //`
15			`// //`
16			`// Write accesses can be done in a single clock cycle on //`
17			`// the wishbone bus, is the destination allows it. The //`
18			`// next transfer will begin immediately on the //`
19			`// next cycle on the bus. This looks like a block transfer //`
20			`// and does hold ownership of the wishbone bus, preventing //`
21			`// the other master ( the ethernet MAC) from gaining //`
22			`// ownership between those two cycles. But otherwise it would //`
23			`// be necessary to insert a wait cycle after every write, //`
24			`// slowing down the performance of the core by around 5 to //`
25			`// 10%. //`
26			`// //`
27			`// Author(s): //`
28			`// - Conor Santifort, csantifort.amber@gmail.com //`
29			`// //`
30			`//////////////////////////////////////////////////////////////////`
31			`// //`
32			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
33			`// //`
34			`// This source file may be used and distributed without //`
35			`// restriction provided that this copyright statement is not //`
36			`// removed from the file and that any derivative work contains //`
37			`// the original copyright notice and the associated disclaimer. //`
38			`// //`
39			`// This source file is free software; you can redistribute it //`
40			`// and/or modify it under the terms of the GNU Lesser General //`
41			`// Public License as published by the Free Software Foundation; //`
42			`// either version 2.1 of the License, or (at your option) any //`
43			`// later version. //`
44			`// //`
45			`// This source is distributed in the hope that it will be //`
46			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
47			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
48			`// PURPOSE. See the GNU Lesser General Public License for more //`
49			`// details. //`
50			`// //`
51			`// You should have received a copy of the GNU Lesser General //`
52			`// Public License along with this source; if not, download it //`
53			`// from http://www.opencores.org/lgpl.shtml //`
54			`// //`
55			`//////////////////////////////////////////////////////////////////`
56
57
58	15	csantifort	`module a23_wishbone`
59	2	csantifort	`(`
60			`input i_clk,`
61
62			`// Core Accesses to Wishbone bus`
63			`input i_select,`
64			`input [31:0] i_write_data,`
65			`input i_write_enable,`
66			`input [3:0] i_byte_enable, // valid for writes only`
67			`input i_data_access,`
68			`input i_exclusive, // high for read part of swap access`
69			`input [31:0] i_address,`
70			`output o_stall,`
71
72			`// Cache Accesses to Wishbone bus`
73			`input i_cache_req,`
74
75			`// Wishbone Bus`
76			`output reg [31:0] o_wb_adr = 'd0,`
77			`output reg [3:0] o_wb_sel = 'd0,`
78			`output reg o_wb_we = 'd0,`
79			`input [31:0] i_wb_dat,`
80			`output reg [31:0] o_wb_dat = 'd0,`
81			`output reg o_wb_cyc = 'd0,`
82			`output reg o_wb_stb = 'd0,`
83			`input i_wb_ack,`
84			`input i_wb_err`
85
86			`);`
87
88
89			`localparam [3:0] WB_IDLE = 3'd0,`
90			`WB_BURST1 = 3'd1,`
91			`WB_BURST2 = 3'd2,`
92			`WB_BURST3 = 3'd3,`
93			`WB_WAIT_ACK = 3'd4;`
94
95			`reg [2:0] wishbone_st = WB_IDLE;`
96
97			`wire core_read_request;`
98			`wire core_write_request;`
99			`wire cache_read_request;`
100			`wire cache_write_request;`
101			`wire start_access;`
102			`reg servicing_cache = 'd0;`
103			`wire [3:0] byte_enable;`
104			`reg exclusive_access = 'd0;`
105			`wire read_ack;`
106			`wire wait_write_ack;`
107	42	csantifort	`wire wb_wait;`
108	2	csantifort
109	42	csantifort	`// Write buffer`
110			`reg [31:0] wbuf_data_r = 'd0;`
111			`reg [31:0] wbuf_addr_r = 'd0;`
112			`reg [3:0] wbuf_sel_r = 'd0;`
113			`reg wbuf_busy_r = 'd0;`
114	2	csantifort
115
116			`assign read_ack = !o_wb_we && i_wb_ack;`
117			`assign o_stall = ( core_read_request && !read_ack ) \|\|`
118			`( core_read_request && servicing_cache ) \|\|`
119	42	csantifort	`( core_write_request && servicing_cache ) \|\|`
120			`( core_write_request && wishbone_st == WB_WAIT_ACK) \|\|`
121			`( cache_write_request && wishbone_st == WB_WAIT_ACK) \|\|`
122			`wbuf_busy_r;`
123	2	csantifort
124			`// Don't stall on writes`
125			`// Wishbone is doing burst read so make core wait to execute the write`
126			`// ( core_write_request && !i_wb_ack ) ;`
127
128			`assign core_read_request = i_select && !i_write_enable;`
129			`assign core_write_request = i_select && i_write_enable;`
130
131			`assign cache_read_request = i_cache_req && !i_write_enable;`
132			`assign cache_write_request = i_cache_req && i_write_enable;`
133
134	42	csantifort	`assign wb_wait = o_wb_stb && !i_wb_ack;`
135			`assign start_access = (core_read_request \|\| core_write_request \|\| i_cache_req) && !wb_wait ;`
136	2	csantifort
137			`// For writes the byte enable is always 4'hf`
138	42	csantifort	`assign byte_enable = wbuf_busy_r ? wbuf_sel_r :`
139			`( core_write_request \|\| cache_write_request ) ? i_byte_enable :`
140			`4'hf ;`
141	2	csantifort
142
143	42	csantifort
144	2	csantifort	`// ======================================`
145	42	csantifort	`// Write buffer`
146			`// ======================================`
147
148
149			`always @( posedge i_clk )`
150			`if ( wb_wait && !wbuf_busy_r && (core_write_request \|\| cache_write_request) )`
151			`begin`
152			`wbuf_data_r <= i_write_data;`
153			`wbuf_addr_r <= i_address;`
154			`wbuf_sel_r <= i_byte_enable;`
155			`wbuf_busy_r <= 1'd1;`
156			`end`
157			`else if (!o_wb_stb)`
158			`wbuf_busy_r <= 1'd0;`
159
160			`// ======================================`
161	2	csantifort	`// Register Accesses`
162			`// ======================================`
163			`always @( posedge i_clk )`
164			`if ( start_access )`
165			`o_wb_dat <= i_write_data;`
166
167
168			`assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;`
169
170
171			`always @( posedge i_clk )`
172			`case ( wishbone_st )`
173			`WB_IDLE :`
174			`begin`
175
176			`if ( start_access )`
177			`begin`
178			`o_wb_stb <= 1'd1;`
179			`o_wb_cyc <= 1'd1;`
180			`o_wb_sel <= byte_enable;`
181			`end`
182			`else if ( !wait_write_ack )`
183			`begin`
184			`o_wb_stb <= 1'd0;`
185
186			`// Hold cyc high after an exclusive access`
187			`// to hold ownership of the wishbone bus`
188			`o_wb_cyc <= exclusive_access;`
189			`end`
190
191			`// cache has priority over the core`
192			`servicing_cache <= cache_read_request && !wait_write_ack;`
193
194			`if ( wait_write_ack )`
195			`begin`
196			`// still waiting for last (write) access to complete`
197			`wishbone_st <= WB_WAIT_ACK;`
198			`end`
199			`// do a burst of 4 read to fill a cache line`
200			`else if ( cache_read_request )`
201			`begin`
202	42	csantifort	`wishbone_st <= WB_BURST1;`
203	2	csantifort	`exclusive_access <= 1'd0;`
204			`end`
205			`else if ( core_read_request )`
206			`begin`
207	42	csantifort	`wishbone_st <= WB_WAIT_ACK;`
208	2	csantifort	`exclusive_access <= i_exclusive;`
209			`end`
210			`// The core does not currently issue exclusive write requests`
211			`// but there's no reason why this might not be added some`
212			`// time in the future so allow for it here`
213			`else if ( core_write_request )`
214			`exclusive_access <= i_exclusive;`
215
216
217			`if ( start_access )`
218			`begin`
219	42	csantifort	`if (wbuf_busy_r)`
220			`begin`
221			`o_wb_we <= 1'd1;`
222			`o_wb_adr[31:2] <= wbuf_addr_r[31:2];`
223			`end`
224			`else`
225			`begin`
226			`o_wb_we <= core_write_request \|\| cache_write_request;`
227			`// only update these on new wb access to make debug easier`
228			`o_wb_adr[31:2] <= i_address[31:2];`
229			`end`
230
231	2	csantifort	`o_wb_adr[1:0] <= byte_enable == 4'b0001 ? 2'd0 :`
232			`byte_enable == 4'b0010 ? 2'd1 :`
233			`byte_enable == 4'b0100 ? 2'd2 :`
234			`byte_enable == 4'b1000 ? 2'd3 :`
235
236			`byte_enable == 4'b0011 ? 2'd0 :`
237			`byte_enable == 4'b1100 ? 2'd2 :`
238
239			`2'd0 ;`
240			`end`
241			`end`
242
243
244			`// Read burst, wait for first ack`
245			`WB_BURST1:`
246			`if ( i_wb_ack )`
247			`begin`
248			`// burst of 4 that wraps`
249			`o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;`
250			`wishbone_st <= WB_BURST2;`
251			`end`
252
253
254			`// Read burst, wait for second ack`
255			`WB_BURST2:`
256			`if ( i_wb_ack )`
257			`begin`
258			`// burst of 4 that wraps`
259			`o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;`
260			`wishbone_st <= WB_BURST3;`
261			`end`
262
263
264			`// Read burst, wait for third ack`
265			`WB_BURST3:`
266			`if ( i_wb_ack )`
267			`begin`
268			`// burst of 4 that wraps`
269			`o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;`
270			`wishbone_st <= WB_WAIT_ACK;`
271			`end`
272
273
274			`// Wait for the wishbone ack to be asserted`
275			`WB_WAIT_ACK:`
276			`if ( i_wb_ack )`
277			`begin`
278			`wishbone_st <= WB_IDLE;`
279			`o_wb_stb <= 1'd0;`
280			`o_wb_cyc <= exclusive_access;`
281			`o_wb_we <= 1'd0;`
282			`servicing_cache <= 1'd0;`
283			`end`
284
285			`endcase`
286
287
288
289			`// ========================================================`
290			`// Debug Wishbone bus - not synthesizable`
291			`// ========================================================`
292			`//synopsys translate_off`
293			`wire [(14*8)-1:0] xAS_STATE;`
294
295
296			`assign xAS_STATE = wishbone_st == WB_IDLE ? "WB_IDLE" :`
297			`wishbone_st == WB_BURST1 ? "WB_BURST1" :`
298			`wishbone_st == WB_BURST2 ? "WB_BURST2" :`
299			`wishbone_st == WB_BURST3 ? "WB_BURST3" :`
300			`wishbone_st == WB_WAIT_ACK ? "WB_WAIT_ACK" :`
301			`"UNKNOWN" ;`
302
303			`//synopsys translate_on`
304
305			`endmodule`
306