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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Wishbone master interface for the Amber core //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Turns memory access requests from the execute stage and //
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// cache into wishbone bus cycles. For 4-word read requests //
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// from the cache and swap accesses ( read followed by write //
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// to the same address) from the execute stage, //
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// a block transfer is done. All other requests result in //
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// single word transfers. //
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// //
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// Write accesses can be done in a single clock cycle on //
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// the wishbone bus, is the destination allows it. The //
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// next transfer will begin immediately on the //
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// next cycle on the bus. This looks like a block transfer //
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// and does hold ownership of the wishbone bus, preventing //
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// the other master ( the ethernet MAC) from gaining //
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// ownership between those two cycles. But otherwise it would //
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// be necessary to insert a wait cycle after every write, //
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// slowing down the performance of the core by around 5 to //
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// 10%. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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15 |
csantifort |
module a23_wishbone
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2 |
csantifort |
(
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input i_clk,
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// Core Accesses to Wishbone bus
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input i_select,
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input [31:0] i_write_data,
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input i_write_enable,
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input [3:0] i_byte_enable, // valid for writes only
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input i_data_access,
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input i_exclusive, // high for read part of swap access
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input [31:0] i_address,
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output o_stall,
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// Cache Accesses to Wishbone bus
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input i_cache_req,
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// Wishbone Bus
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output reg [31:0] o_wb_adr = 'd0,
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output reg [3:0] o_wb_sel = 'd0,
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output reg o_wb_we = 'd0,
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input [31:0] i_wb_dat,
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output reg [31:0] o_wb_dat = 'd0,
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output reg o_wb_cyc = 'd0,
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output reg o_wb_stb = 'd0,
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input i_wb_ack,
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input i_wb_err
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);
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localparam [3:0] WB_IDLE = 3'd0,
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WB_BURST1 = 3'd1,
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WB_BURST2 = 3'd2,
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WB_BURST3 = 3'd3,
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WB_WAIT_ACK = 3'd4;
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reg [2:0] wishbone_st = WB_IDLE;
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wire core_read_request;
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wire core_write_request;
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wire cache_read_request;
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wire cache_write_request;
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wire start_access;
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reg servicing_cache = 'd0;
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wire [3:0] byte_enable;
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reg exclusive_access = 'd0;
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wire read_ack;
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wire wait_write_ack;
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42 |
csantifort |
wire wb_wait;
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2 |
csantifort |
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42 |
csantifort |
// Write buffer
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reg [31:0] wbuf_addr_r = 'd0;
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reg [3:0] wbuf_sel_r = 'd0;
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reg wbuf_busy_r = 'd0;
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2 |
csantifort |
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assign read_ack = !o_wb_we && i_wb_ack;
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assign o_stall = ( core_read_request && !read_ack ) ||
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( core_read_request && servicing_cache ) ||
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42 |
csantifort |
( core_write_request && servicing_cache ) ||
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( core_write_request && wishbone_st == WB_WAIT_ACK) ||
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( cache_write_request && wishbone_st == WB_WAIT_ACK) ||
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wbuf_busy_r;
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2 |
csantifort |
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// Don't stall on writes
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// Wishbone is doing burst read so make core wait to execute the write
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// ( core_write_request && !i_wb_ack ) ;
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assign core_read_request = i_select && !i_write_enable;
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assign core_write_request = i_select && i_write_enable;
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assign cache_read_request = i_cache_req && !i_write_enable;
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assign cache_write_request = i_cache_req && i_write_enable;
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42 |
csantifort |
assign wb_wait = o_wb_stb && !i_wb_ack;
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assign start_access = (core_read_request || core_write_request || i_cache_req) && !wb_wait ;
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2 |
csantifort |
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// For writes the byte enable is always 4'hf
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42 |
csantifort |
assign byte_enable = wbuf_busy_r ? wbuf_sel_r :
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( core_write_request || cache_write_request ) ? i_byte_enable :
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4'hf ;
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2 |
csantifort |
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42 |
csantifort |
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2 |
csantifort |
// ======================================
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42 |
csantifort |
// Write buffer
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// ======================================
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always @( posedge i_clk )
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if ( wb_wait && !wbuf_busy_r && (core_write_request || cache_write_request) )
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begin
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wbuf_addr_r <= i_address;
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wbuf_sel_r <= i_byte_enable;
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wbuf_busy_r <= 1'd1;
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end
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else if (!o_wb_stb)
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wbuf_busy_r <= 1'd0;
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// ======================================
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2 |
csantifort |
// Register Accesses
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// ======================================
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always @( posedge i_clk )
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if ( start_access )
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o_wb_dat <= i_write_data;
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assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
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always @( posedge i_clk )
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case ( wishbone_st )
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WB_IDLE :
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begin
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if ( start_access )
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begin
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o_wb_stb <= 1'd1;
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o_wb_cyc <= 1'd1;
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o_wb_sel <= byte_enable;
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end
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else if ( !wait_write_ack )
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begin
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o_wb_stb <= 1'd0;
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// Hold cyc high after an exclusive access
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// to hold ownership of the wishbone bus
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o_wb_cyc <= exclusive_access;
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end
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// cache has priority over the core
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servicing_cache <= cache_read_request && !wait_write_ack;
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if ( wait_write_ack )
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begin
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// still waiting for last (write) access to complete
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wishbone_st <= WB_WAIT_ACK;
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end
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// do a burst of 4 read to fill a cache line
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else if ( cache_read_request )
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begin
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42 |
csantifort |
wishbone_st <= WB_BURST1;
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2 |
csantifort |
exclusive_access <= 1'd0;
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end
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else if ( core_read_request )
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begin
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42 |
csantifort |
wishbone_st <= WB_WAIT_ACK;
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2 |
csantifort |
exclusive_access <= i_exclusive;
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end
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// The core does not currently issue exclusive write requests
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// but there's no reason why this might not be added some
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// time in the future so allow for it here
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else if ( core_write_request )
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exclusive_access <= i_exclusive;
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if ( start_access )
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begin
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42 |
csantifort |
if (wbuf_busy_r)
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begin
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o_wb_we <= 1'd1;
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o_wb_adr[31:2] <= wbuf_addr_r[31:2];
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end
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else
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begin
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o_wb_we <= core_write_request || cache_write_request;
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// only update these on new wb access to make debug easier
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o_wb_adr[31:2] <= i_address[31:2];
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end
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2 |
csantifort |
o_wb_adr[1:0] <= byte_enable == 4'b0001 ? 2'd0 :
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byte_enable == 4'b0010 ? 2'd1 :
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byte_enable == 4'b0100 ? 2'd2 :
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byte_enable == 4'b1000 ? 2'd3 :
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byte_enable == 4'b0011 ? 2'd0 :
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byte_enable == 4'b1100 ? 2'd2 :
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2'd0 ;
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end
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end
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// Read burst, wait for first ack
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WB_BURST1:
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if ( i_wb_ack )
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begin
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// burst of 4 that wraps
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o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
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wishbone_st <= WB_BURST2;
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end
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// Read burst, wait for second ack
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WB_BURST2:
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if ( i_wb_ack )
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begin
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// burst of 4 that wraps
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o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
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wishbone_st <= WB_BURST3;
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end
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// Read burst, wait for third ack
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WB_BURST3:
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if ( i_wb_ack )
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begin
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// burst of 4 that wraps
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o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
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wishbone_st <= WB_WAIT_ACK;
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end
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// Wait for the wishbone ack to be asserted
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WB_WAIT_ACK:
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if ( i_wb_ack )
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begin
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wishbone_st <= WB_IDLE;
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o_wb_stb <= 1'd0;
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o_wb_cyc <= exclusive_access;
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o_wb_we <= 1'd0;
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servicing_cache <= 1'd0;
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end
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endcase
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// ========================================================
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// Debug Wishbone bus - not synthesizable
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// ========================================================
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//synopsys translate_off
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wire [(14*8)-1:0] xAS_STATE;
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assign xAS_STATE = wishbone_st == WB_IDLE ? "WB_IDLE" :
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wishbone_st == WB_BURST1 ? "WB_BURST1" :
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wishbone_st == WB_BURST2 ? "WB_BURST2" :
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wishbone_st == WB_BURST3 ? "WB_BURST3" :
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wishbone_st == WB_WAIT_ACK ? "WB_WAIT_ACK" :
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"UNKNOWN" ;
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//synopsys translate_on
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endmodule
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