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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Amber 25 Core top-Level module //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Instantiates the core consisting of fetch, instruction //
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csantifort |
// decode, execute, memory access and write back. The //
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// Wishbone interface and Co-Processor modules are also //
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// instantiated here. //
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csantifort |
// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2011 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module a25_core
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(
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input i_clk,
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input i_irq, // Interrupt request, active high
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input i_firq, // Fast Interrupt request, active high
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input i_system_rdy, // Amber is stalled when this is low
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// Wishbone Master I/F
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output [31:0] o_wb_adr,
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csantifort |
output [15:0] o_wb_sel,
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output o_wb_we,
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input [127:0] i_wb_dat,
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output [127:0] o_wb_dat,
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output o_wb_cyc,
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output o_wb_stb,
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input i_wb_ack,
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input i_wb_err
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);
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wire [31:0] execute_iaddress;
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wire execute_iaddress_valid;
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wire [31:0] execute_iaddress_nxt; // un-registered version of execute_address
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// to the instruction cache rams
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wire [31:0] execute_daddress;
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wire execute_daddress_valid;
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wire [31:0] execute_daddress_nxt; // un-registered version of execute_daddress
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// to the data cache rams
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wire [31:0] write_data;
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wire write_enable;
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wire [31:0] fetch_instruction;
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wire decode_exclusive;
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wire decode_iaccess;
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wire decode_daccess;
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wire [3:0] byte_enable;
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wire exclusive; // swap access
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wire cache_enable; // Enabel the cache
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wire cache_flush; // Flush the cache
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wire [31:0] cacheable_area;
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wire fetch_stall;
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wire mem_stall;
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csantifort |
wire exec_stall;
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wire core_stall;
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csantifort |
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wire [1:0] status_bits_mode;
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wire status_bits_irq_mask;
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wire status_bits_firq_mask;
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wire status_bits_flags_wen;
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wire status_bits_mode_wen;
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wire status_bits_irq_mask_wen;
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wire status_bits_firq_mask_wen;
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wire [31:0] execute_status_bits;
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wire [31:0] imm32;
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wire [4:0] imm_shift_amount;
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wire shift_imm_zero;
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wire [3:0] condition;
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wire [3:0] rm_sel;
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wire [3:0] rs_sel;
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wire [7:0] decode_load_rd;
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wire [8:0] exec_load_rd;
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wire [3:0] rn_sel;
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wire [1:0] barrel_shift_amount_sel;
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wire [1:0] barrel_shift_data_sel;
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wire [1:0] barrel_shift_function;
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wire [8:0] alu_function;
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wire [1:0] multiply_function;
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wire [2:0] interrupt_vector_sel;
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wire [3:0] iaddress_sel;
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wire [3:0] daddress_sel;
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wire [2:0] pc_sel;
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wire [1:0] byte_enable_sel;
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wire [2:0] status_bits_sel;
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wire [2:0] reg_write_sel;
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wire user_mode_regs_store_nxt;
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wire firq_not_user_mode;
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wire write_data_wen;
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wire copro_write_data_wen;
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wire base_address_wen;
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wire pc_wen;
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wire [14:0] reg_bank_wen;
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wire [2:0] copro_opcode1;
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wire [2:0] copro_opcode2;
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wire [3:0] copro_crn;
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wire [3:0] copro_crm;
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wire [3:0] copro_num;
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wire [1:0] copro_operation;
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wire [31:0] copro_read_data;
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wire [31:0] copro_write_data;
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wire multiply_done;
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wire decode_fault;
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wire iabt_trigger;
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wire dabt_trigger;
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wire [7:0] decode_fault_status;
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wire [7:0] iabt_fault_status;
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wire [7:0] dabt_fault_status;
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wire [31:0] decode_fault_address;
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wire [31:0] iabt_fault_address;
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wire [31:0] dabt_fault_address;
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wire adex;
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wire [31:0] mem_read_data;
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wire mem_read_data_valid;
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csantifort |
wire [10:0] mem_load_rd;
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csantifort |
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wire [31:0] wb_read_data;
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wire wb_read_data_valid;
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csantifort |
wire [10:0] wb_load_rd;
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csantifort |
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wire dcache_wb_cached_req;
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wire dcache_wb_uncached_req;
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wire dcache_wb_qword;
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wire dcache_wb_write;
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csantifort |
wire [15:0] dcache_wb_byte_enable;
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csantifort |
wire [31:0] dcache_wb_address;
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csantifort |
wire [127:0] dcache_wb_cached_rdata;
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wire [127:0] dcache_wb_uncached_rdata;
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wire [127:0] dcache_wb_write_data;
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csantifort |
wire dcache_wb_cached_ready;
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wire dcache_wb_uncached_ready;
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wire [31:0] icache_wb_address;
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wire icache_wb_req;
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wire [31:0] icache_wb_adr;
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csantifort |
wire [127:0] icache_wb_read_data;
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csantifort |
wire icache_wb_ready;
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wire conflict;
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csantifort |
wire rn_use_read;
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wire rm_use_read;
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wire rs_use_read;
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wire rd_use_read;
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csantifort |
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// data abort has priority
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assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status;
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assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
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assign decode_fault = dabt_trigger | iabt_trigger;
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csantifort |
assign core_stall = fetch_stall || mem_stall || exec_stall;
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csantifort |
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// ======================================
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// Fetch Stage
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// ======================================
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a25_fetch u_fetch (
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.i_clk ( i_clk ),
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.i_mem_stall ( mem_stall ),
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csantifort |
.i_exec_stall ( exec_stall ),
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csantifort |
.i_conflict ( conflict ),
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.i_system_rdy ( i_system_rdy ),
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.o_fetch_stall ( fetch_stall ),
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.i_iaddress ( {execute_iaddress[31:2], 2'd0} ),
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.i_iaddress_valid ( execute_iaddress_valid ),
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.i_iaddress_nxt ( execute_iaddress_nxt ),
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.o_fetch_instruction ( fetch_instruction ),
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.i_cache_enable ( cache_enable ),
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.i_cache_flush ( cache_flush ),
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.i_cacheable_area ( cacheable_area ),
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.o_wb_req ( icache_wb_req ),
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.o_wb_address ( icache_wb_address ),
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.i_wb_read_data ( icache_wb_read_data ),
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.i_wb_ready ( icache_wb_ready )
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);
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// ======================================
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// Decode Stage
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// ======================================
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a25_decode u_decode (
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.i_clk ( i_clk ),
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csantifort |
.i_core_stall ( core_stall ),
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csantifort |
// Instruction fetch or data read signals
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.i_fetch_instruction ( fetch_instruction ),
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.i_execute_iaddress ( execute_iaddress ),
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.i_execute_daddress ( execute_daddress ),
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.i_adex ( adex ),
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.i_iabt ( 1'd0 ),
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.i_dabt ( 1'd0 ),
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.i_abt_status ( 8'd0 ),
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.i_irq ( i_irq ),
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.i_firq ( i_firq ),
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.i_execute_status_bits ( execute_status_bits ),
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.i_multiply_done ( multiply_done ),
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.o_status_bits_mode ( status_bits_mode ),
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.o_status_bits_irq_mask ( status_bits_irq_mask ),
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.o_status_bits_firq_mask ( status_bits_firq_mask ),
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.o_imm32 ( imm32 ),
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.o_imm_shift_amount ( imm_shift_amount ),
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.o_shift_imm_zero ( shift_imm_zero ),
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.o_condition ( condition ),
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.o_decode_exclusive ( decode_exclusive ),
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.o_decode_iaccess ( decode_iaccess ),
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.o_decode_daccess ( decode_daccess ),
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.o_rm_sel ( rm_sel ),
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.o_rs_sel ( rs_sel ),
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.o_load_rd ( decode_load_rd ),
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.o_rn_sel ( rn_sel ),
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.o_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
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.o_barrel_shift_data_sel ( barrel_shift_data_sel ),
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.o_barrel_shift_function ( barrel_shift_function ),
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.o_alu_function ( alu_function ),
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.o_multiply_function ( multiply_function ),
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.o_interrupt_vector_sel ( interrupt_vector_sel ),
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.o_iaddress_sel ( iaddress_sel ),
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.o_daddress_sel ( daddress_sel ),
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.o_pc_sel ( pc_sel ),
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.o_byte_enable_sel ( byte_enable_sel ),
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.o_status_bits_sel ( status_bits_sel ),
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.o_reg_write_sel ( reg_write_sel ),
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.o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
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.o_firq_not_user_mode ( firq_not_user_mode ),
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.o_write_data_wen ( write_data_wen ),
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.o_base_address_wen ( base_address_wen ),
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.o_pc_wen ( pc_wen ),
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.o_reg_bank_wen ( reg_bank_wen ),
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.o_status_bits_flags_wen ( status_bits_flags_wen ),
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.o_status_bits_mode_wen ( status_bits_mode_wen ),
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.o_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
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.o_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
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.o_copro_opcode1 ( copro_opcode1 ),
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.o_copro_opcode2 ( copro_opcode2 ),
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.o_copro_crn ( copro_crn ),
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.o_copro_crm ( copro_crm ),
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.o_copro_num ( copro_num ),
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.o_copro_operation ( copro_operation ),
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.o_copro_write_data_wen ( copro_write_data_wen ),
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.o_iabt_trigger ( iabt_trigger ),
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| 287 |
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.o_iabt_address ( iabt_fault_address ),
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.o_iabt_status ( iabt_fault_status ),
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.o_dabt_trigger ( dabt_trigger ),
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.o_dabt_address ( dabt_fault_address ),
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.o_dabt_status ( dabt_fault_status ),
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20 |
csantifort |
.o_conflict ( conflict ),
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.o_rn_use_read ( rn_use_read ),
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.o_rm_use_read ( rm_use_read ),
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.o_rs_use_read ( rs_use_read ),
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.o_rd_use_read ( rd_use_read )
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| 298 |
16 |
csantifort |
);
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| 301 |
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// ======================================
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| 302 |
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// Execute Stage
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// ======================================
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| 304 |
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a25_execute u_execute (
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| 305 |
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.i_clk ( i_clk ),
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35 |
csantifort |
.i_core_stall ( core_stall ),
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| 307 |
16 |
csantifort |
.i_mem_stall ( mem_stall ),
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| 308 |
35 |
csantifort |
.o_exec_stall ( exec_stall ),
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16 |
csantifort |
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.i_wb_read_data ( wb_read_data ),
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.i_wb_read_data_valid ( wb_read_data_valid ),
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.i_wb_load_rd ( wb_load_rd ),
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.i_copro_read_data ( copro_read_data ),
|
| 315 |
|
|
|
| 316 |
|
|
.o_write_data ( write_data ),
|
| 317 |
|
|
.o_copro_write_data ( copro_write_data ),
|
| 318 |
|
|
.o_iaddress ( execute_iaddress ),
|
| 319 |
|
|
.o_iaddress_valid ( execute_iaddress_valid ),
|
| 320 |
|
|
.o_iaddress_nxt ( execute_iaddress_nxt ),
|
| 321 |
|
|
.o_daddress ( execute_daddress ),
|
| 322 |
|
|
.o_daddress_nxt ( execute_daddress_nxt ),
|
| 323 |
|
|
.o_daddress_valid ( execute_daddress_valid ),
|
| 324 |
|
|
.o_byte_enable ( byte_enable ),
|
| 325 |
|
|
.o_write_enable ( write_enable ),
|
| 326 |
|
|
.o_exclusive ( exclusive ),
|
| 327 |
|
|
.o_priviledged ( ),
|
| 328 |
|
|
.o_exec_load_rd ( exec_load_rd ),
|
| 329 |
|
|
|
| 330 |
|
|
.o_adex ( adex ),
|
| 331 |
|
|
.o_status_bits ( execute_status_bits ),
|
| 332 |
|
|
.o_multiply_done ( multiply_done ),
|
| 333 |
|
|
|
| 334 |
|
|
.i_status_bits_mode ( status_bits_mode ),
|
| 335 |
|
|
.i_status_bits_irq_mask ( status_bits_irq_mask ),
|
| 336 |
|
|
.i_status_bits_firq_mask ( status_bits_firq_mask ),
|
| 337 |
|
|
.i_imm32 ( imm32 ),
|
| 338 |
|
|
.i_imm_shift_amount ( imm_shift_amount ),
|
| 339 |
|
|
.i_shift_imm_zero ( shift_imm_zero ),
|
| 340 |
|
|
.i_condition ( condition ),
|
| 341 |
|
|
.i_decode_exclusive ( decode_exclusive ),
|
| 342 |
|
|
.i_decode_iaccess ( decode_iaccess ),
|
| 343 |
|
|
.i_decode_daccess ( decode_daccess ),
|
| 344 |
|
|
.i_rm_sel ( rm_sel ),
|
| 345 |
|
|
.i_rs_sel ( rs_sel ),
|
| 346 |
|
|
.i_decode_load_rd ( decode_load_rd ),
|
| 347 |
|
|
.i_rn_sel ( rn_sel ),
|
| 348 |
|
|
.i_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
|
| 349 |
|
|
.i_barrel_shift_data_sel ( barrel_shift_data_sel ),
|
| 350 |
|
|
.i_barrel_shift_function ( barrel_shift_function ),
|
| 351 |
|
|
.i_alu_function ( alu_function ),
|
| 352 |
|
|
.i_multiply_function ( multiply_function ),
|
| 353 |
|
|
.i_interrupt_vector_sel ( interrupt_vector_sel ),
|
| 354 |
|
|
.i_iaddress_sel ( iaddress_sel ),
|
| 355 |
|
|
.i_daddress_sel ( daddress_sel ),
|
| 356 |
|
|
.i_pc_sel ( pc_sel ),
|
| 357 |
|
|
.i_byte_enable_sel ( byte_enable_sel ),
|
| 358 |
|
|
.i_status_bits_sel ( status_bits_sel ),
|
| 359 |
|
|
.i_reg_write_sel ( reg_write_sel ),
|
| 360 |
|
|
.i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
|
| 361 |
|
|
.i_firq_not_user_mode ( firq_not_user_mode ),
|
| 362 |
|
|
.i_write_data_wen ( write_data_wen ),
|
| 363 |
|
|
.i_base_address_wen ( base_address_wen ),
|
| 364 |
|
|
.i_pc_wen ( pc_wen ),
|
| 365 |
|
|
.i_reg_bank_wen ( reg_bank_wen ),
|
| 366 |
|
|
.i_status_bits_flags_wen ( status_bits_flags_wen ),
|
| 367 |
|
|
.i_status_bits_mode_wen ( status_bits_mode_wen ),
|
| 368 |
|
|
.i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
|
| 369 |
|
|
.i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
|
| 370 |
|
|
.i_copro_write_data_wen ( copro_write_data_wen ),
|
| 371 |
20 |
csantifort |
.i_conflict ( conflict ),
|
| 372 |
|
|
.i_rn_use_read ( rn_use_read ),
|
| 373 |
|
|
.i_rm_use_read ( rm_use_read ),
|
| 374 |
|
|
.i_rs_use_read ( rs_use_read ),
|
| 375 |
|
|
.i_rd_use_read ( rd_use_read )
|
| 376 |
16 |
csantifort |
);
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
// ======================================
|
| 380 |
|
|
// Memory access stage with data cache
|
| 381 |
|
|
// ======================================
|
| 382 |
|
|
a25_mem u_mem (
|
| 383 |
|
|
.i_clk ( i_clk ),
|
| 384 |
|
|
.i_fetch_stall ( fetch_stall ),
|
| 385 |
35 |
csantifort |
.i_exec_stall ( exec_stall ),
|
| 386 |
16 |
csantifort |
.o_mem_stall ( mem_stall ),
|
| 387 |
|
|
|
| 388 |
|
|
.i_daddress ( execute_daddress ),
|
| 389 |
|
|
.i_daddress_valid ( execute_daddress_valid ),
|
| 390 |
|
|
.i_daddress_nxt ( execute_daddress_nxt ),
|
| 391 |
|
|
.i_write_data ( write_data ),
|
| 392 |
|
|
.i_write_enable ( write_enable ),
|
| 393 |
|
|
.i_byte_enable ( byte_enable ),
|
| 394 |
|
|
.i_exclusive ( exclusive ),
|
| 395 |
|
|
.i_exec_load_rd ( exec_load_rd ),
|
| 396 |
|
|
|
| 397 |
|
|
.o_mem_read_data ( mem_read_data ),
|
| 398 |
|
|
.o_mem_read_data_valid ( mem_read_data_valid ),
|
| 399 |
|
|
.o_mem_load_rd ( mem_load_rd ),
|
| 400 |
|
|
|
| 401 |
|
|
.i_cache_enable ( cache_enable ),
|
| 402 |
|
|
.i_cache_flush ( cache_flush ),
|
| 403 |
|
|
.i_cacheable_area ( cacheable_area ),
|
| 404 |
|
|
|
| 405 |
|
|
.o_wb_cached_req ( dcache_wb_cached_req ),
|
| 406 |
|
|
.o_wb_uncached_req ( dcache_wb_uncached_req ),
|
| 407 |
|
|
.o_wb_qword ( dcache_wb_qword ),
|
| 408 |
|
|
.o_wb_write ( dcache_wb_write ),
|
| 409 |
|
|
.o_wb_write_data ( dcache_wb_write_data ),
|
| 410 |
|
|
.o_wb_byte_enable ( dcache_wb_byte_enable ),
|
| 411 |
|
|
.o_wb_address ( dcache_wb_address ),
|
| 412 |
|
|
.i_wb_cached_ready ( dcache_wb_cached_ready ),
|
| 413 |
35 |
csantifort |
.i_wb_cached_rdata ( dcache_wb_cached_rdata ),
|
| 414 |
|
|
.i_wb_uncached_ready ( dcache_wb_uncached_ready ),
|
| 415 |
|
|
.i_wb_uncached_rdata ( dcache_wb_cached_rdata )
|
| 416 |
16 |
csantifort |
);
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
// ======================================
|
| 420 |
|
|
// Write back stage with data cache
|
| 421 |
|
|
// ======================================
|
| 422 |
|
|
a25_write_back u_write_back (
|
| 423 |
|
|
.i_clk ( i_clk ),
|
| 424 |
|
|
.i_mem_stall ( mem_stall ),
|
| 425 |
|
|
|
| 426 |
|
|
.i_daddress ( execute_daddress ),
|
| 427 |
|
|
.i_daddress_valid ( execute_daddress_valid ),
|
| 428 |
|
|
|
| 429 |
|
|
.i_mem_read_data ( mem_read_data ),
|
| 430 |
|
|
.i_mem_read_data_valid ( mem_read_data_valid ),
|
| 431 |
|
|
.i_mem_load_rd ( mem_load_rd ),
|
| 432 |
|
|
|
| 433 |
|
|
.o_wb_read_data ( wb_read_data ),
|
| 434 |
|
|
.o_wb_read_data_valid ( wb_read_data_valid ),
|
| 435 |
|
|
.o_wb_load_rd ( wb_load_rd )
|
| 436 |
|
|
);
|
| 437 |
35 |
csantifort |
|
| 438 |
|
|
|
| 439 |
|
|
|
| 440 |
|
|
|
| 441 |
16 |
csantifort |
// ======================================
|
| 442 |
|
|
// Wishbone Master I/F
|
| 443 |
|
|
// ======================================
|
| 444 |
|
|
a25_wishbone u_wishbone (
|
| 445 |
|
|
// CPU Side
|
| 446 |
|
|
.i_clk ( i_clk ),
|
| 447 |
|
|
|
| 448 |
35 |
csantifort |
// Port 0 - dcache uncached
|
| 449 |
|
|
.i_port0_req ( dcache_wb_uncached_req ),
|
| 450 |
|
|
.i_port0_write ( dcache_wb_write ),
|
| 451 |
|
|
.i_port0_wdata ( dcache_wb_write_data ),
|
| 452 |
|
|
.i_port0_be ( dcache_wb_byte_enable ),
|
| 453 |
|
|
.i_port0_addr ( dcache_wb_address ),
|
| 454 |
|
|
.o_port0_rdata ( dcache_wb_uncached_rdata ),
|
| 455 |
|
|
.o_port0_ready ( dcache_wb_uncached_ready ),
|
| 456 |
16 |
csantifort |
|
| 457 |
35 |
csantifort |
// Port 1 - dcache cached
|
| 458 |
|
|
.i_port1_req ( dcache_wb_cached_req ),
|
| 459 |
|
|
.i_port1_write ( dcache_wb_write ),
|
| 460 |
|
|
.i_port1_wdata ( dcache_wb_write_data ),
|
| 461 |
|
|
.i_port1_be ( dcache_wb_byte_enable ),
|
| 462 |
|
|
.i_port1_addr ( dcache_wb_address ),
|
| 463 |
|
|
.o_port1_rdata ( dcache_wb_cached_rdata ),
|
| 464 |
|
|
.o_port1_ready ( dcache_wb_cached_ready ),
|
| 465 |
16 |
csantifort |
|
| 466 |
35 |
csantifort |
// Port 2 - instruction cache accesses, read only
|
| 467 |
|
|
.i_port2_req ( icache_wb_req ),
|
| 468 |
|
|
.i_port2_write ( 1'd0 ),
|
| 469 |
|
|
.i_port2_wdata ( 128'd0 ),
|
| 470 |
|
|
.i_port2_be ( 16'd0 ),
|
| 471 |
|
|
.i_port2_addr ( icache_wb_address ),
|
| 472 |
|
|
.o_port2_rdata ( icache_wb_read_data ),
|
| 473 |
|
|
.o_port2_ready ( icache_wb_ready ),
|
| 474 |
|
|
|
| 475 |
|
|
// Wishbone
|
| 476 |
16 |
csantifort |
.o_wb_adr ( o_wb_adr ),
|
| 477 |
|
|
.o_wb_sel ( o_wb_sel ),
|
| 478 |
|
|
.o_wb_we ( o_wb_we ),
|
| 479 |
|
|
.i_wb_dat ( i_wb_dat ),
|
| 480 |
|
|
.o_wb_dat ( o_wb_dat ),
|
| 481 |
|
|
.o_wb_cyc ( o_wb_cyc ),
|
| 482 |
|
|
.o_wb_stb ( o_wb_stb ),
|
| 483 |
|
|
.i_wb_ack ( i_wb_ack ),
|
| 484 |
|
|
.i_wb_err ( i_wb_err )
|
| 485 |
|
|
);
|
| 486 |
|
|
|
| 487 |
|
|
|
| 488 |
|
|
// ======================================
|
| 489 |
|
|
// Co-Processor #15
|
| 490 |
|
|
// ======================================
|
| 491 |
|
|
a25_coprocessor u_coprocessor (
|
| 492 |
|
|
.i_clk ( i_clk ),
|
| 493 |
35 |
csantifort |
.i_core_stall ( core_stall ),
|
| 494 |
16 |
csantifort |
|
| 495 |
|
|
.i_copro_opcode1 ( copro_opcode1 ),
|
| 496 |
|
|
.i_copro_opcode2 ( copro_opcode2 ),
|
| 497 |
|
|
.i_copro_crn ( copro_crn ),
|
| 498 |
|
|
.i_copro_crm ( copro_crm ),
|
| 499 |
|
|
.i_copro_num ( copro_num ),
|
| 500 |
|
|
.i_copro_operation ( copro_operation ),
|
| 501 |
|
|
.i_copro_write_data ( copro_write_data ),
|
| 502 |
|
|
|
| 503 |
|
|
.i_fault ( decode_fault ),
|
| 504 |
|
|
.i_fault_status ( decode_fault_status ),
|
| 505 |
|
|
.i_fault_address ( decode_fault_address ),
|
| 506 |
|
|
|
| 507 |
|
|
.o_copro_read_data ( copro_read_data ),
|
| 508 |
|
|
.o_cache_enable ( cache_enable ),
|
| 509 |
|
|
.o_cache_flush ( cache_flush ),
|
| 510 |
|
|
.o_cacheable_area ( cacheable_area )
|
| 511 |
|
|
);
|
| 512 |
|
|
|
| 513 |
|
|
|
| 514 |
|
|
endmodule
|
| 515 |
|
|
|
