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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_core.v] - Blame information for rev 83

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1 16 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Amber 25 Core top-Level module                              //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Instantiates the core consisting of fetch, instruction      //
10 17 csantifort
//  decode, execute, memory access and write back. The          //
11
//  Wishbone interface and Co-Processor modules are also        //
12
//  instantiated here.                                          //
13 16 csantifort
//                                                              //
14
//  Author(s):                                                  //
15
//      - Conor Santifort, csantifort.amber@gmail.com           //
16
//                                                              //
17
//////////////////////////////////////////////////////////////////
18
//                                                              //
19
// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
20
//                                                              //
21
// This source file may be used and distributed without         //
22
// restriction provided that this copyright statement is not    //
23
// removed from the file and that any derivative work contains  //
24
// the original copyright notice and the associated disclaimer. //
25
//                                                              //
26
// This source file is free software; you can redistribute it   //
27
// and/or modify it under the terms of the GNU Lesser General   //
28
// Public License as published by the Free Software Foundation; //
29
// either version 2.1 of the License, or (at your option) any   //
30
// later version.                                               //
31
//                                                              //
32
// This source is distributed in the hope that it will be       //
33
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
34
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
35
// PURPOSE.  See the GNU Lesser General Public License for more //
36
// details.                                                     //
37
//                                                              //
38
// You should have received a copy of the GNU Lesser General    //
39
// Public License along with this source; if not, download it   //
40
// from http://www.opencores.org/lgpl.shtml                     //
41
//                                                              //
42
//////////////////////////////////////////////////////////////////
43
 
44
 
45
module a25_core
46
(
47
input                       i_clk,
48
 
49
input                       i_irq,              // Interrupt request, active high
50
input                       i_firq,             // Fast Interrupt request, active high
51
 
52
input                       i_system_rdy,       // Amber is stalled when this is low
53
 
54
// Wishbone Master I/F
55
output      [31:0]          o_wb_adr,
56 35 csantifort
output      [15:0]          o_wb_sel,
57 16 csantifort
output                      o_wb_we,
58 35 csantifort
input       [127:0]         i_wb_dat,
59
output      [127:0]         o_wb_dat,
60 16 csantifort
output                      o_wb_cyc,
61
output                      o_wb_stb,
62
input                       i_wb_ack,
63
input                       i_wb_err
64
 
65
);
66
 
67
wire      [31:0]          execute_iaddress;
68
wire                      execute_iaddress_valid;
69
wire      [31:0]          execute_iaddress_nxt;  // un-registered version of execute_address
70
                                                 // to the instruction cache rams
71
wire      [31:0]          execute_daddress;
72
wire                      execute_daddress_valid;
73
wire      [31:0]          execute_daddress_nxt; // un-registered version of execute_daddress
74
                                                // to the data cache rams
75
wire      [31:0]          write_data;
76
wire                      write_enable;
77
wire      [31:0]          fetch_instruction;
78
wire                      decode_exclusive;
79
wire                      decode_iaccess;
80
wire                      decode_daccess;
81
wire      [3:0]           byte_enable;
82
wire                      exclusive;            // swap access
83
wire                      cache_enable;         // Enabel the cache
84
wire                      cache_flush;          // Flush the cache
85
wire      [31:0]          cacheable_area;
86
 
87
wire                      fetch_stall;
88
wire                      mem_stall;
89 35 csantifort
wire                      exec_stall;
90
wire                      core_stall;
91 16 csantifort
 
92
wire     [1:0]            status_bits_mode;
93
wire                      status_bits_irq_mask;
94
wire                      status_bits_firq_mask;
95
wire                      status_bits_flags_wen;
96
wire                      status_bits_mode_wen;
97
wire                      status_bits_irq_mask_wen;
98
wire                      status_bits_firq_mask_wen;
99
wire     [31:0]           execute_status_bits;
100
 
101
wire     [31:0]           imm32;
102
wire     [4:0]            imm_shift_amount;
103
wire                      shift_imm_zero;
104
wire     [3:0]            condition;
105
 
106
wire     [3:0]            rm_sel;
107
wire     [3:0]            rs_sel;
108
wire     [7:0]            decode_load_rd;
109 35 csantifort
wire     [8:0]            exec_load_rd;
110 16 csantifort
wire     [3:0]            rn_sel;
111
wire     [1:0]            barrel_shift_amount_sel;
112
wire     [1:0]            barrel_shift_data_sel;
113
wire     [1:0]            barrel_shift_function;
114
wire     [8:0]            alu_function;
115
wire     [1:0]            multiply_function;
116
wire     [2:0]            interrupt_vector_sel;
117
wire     [3:0]            iaddress_sel;
118
wire     [3:0]            daddress_sel;
119
wire     [2:0]            pc_sel;
120
wire     [1:0]            byte_enable_sel;
121
wire     [2:0]            status_bits_sel;
122
wire     [2:0]            reg_write_sel;
123
wire                      user_mode_regs_store_nxt;
124
wire                      firq_not_user_mode;
125 83 csantifort
wire                      use_carry_in;
126 16 csantifort
wire                      write_data_wen;
127
wire                      copro_write_data_wen;
128
wire                      base_address_wen;
129
wire                      pc_wen;
130
wire     [14:0]           reg_bank_wen;
131
 
132
wire     [2:0]            copro_opcode1;
133
wire     [2:0]            copro_opcode2;
134
wire     [3:0]            copro_crn;
135
wire     [3:0]            copro_crm;
136
wire     [3:0]            copro_num;
137
wire     [1:0]            copro_operation;
138
wire     [31:0]           copro_read_data;
139
wire     [31:0]           copro_write_data;
140
wire                      multiply_done;
141
 
142
wire                      decode_fault;
143
wire                      iabt_trigger;
144
wire                      dabt_trigger;
145
 
146
wire     [7:0]            decode_fault_status;
147
wire     [7:0]            iabt_fault_status;
148
wire     [7:0]            dabt_fault_status;
149
 
150
wire     [31:0]           decode_fault_address;
151
wire     [31:0]           iabt_fault_address;
152
wire     [31:0]           dabt_fault_address;
153
 
154
wire                      adex;
155
 
156
wire     [31:0]           mem_read_data;
157
wire                      mem_read_data_valid;
158 35 csantifort
wire     [10:0]           mem_load_rd;
159 16 csantifort
 
160
wire     [31:0]           wb_read_data;
161
wire                      wb_read_data_valid;
162 35 csantifort
wire     [10:0]           wb_load_rd;
163 16 csantifort
 
164
wire                      dcache_wb_cached_req;
165
wire                      dcache_wb_uncached_req;
166
wire                      dcache_wb_write;
167 35 csantifort
wire     [15:0]           dcache_wb_byte_enable;
168 16 csantifort
wire     [31:0]           dcache_wb_address;
169 35 csantifort
wire     [127:0]          dcache_wb_cached_rdata;
170
wire     [127:0]          dcache_wb_write_data;
171 16 csantifort
wire                      dcache_wb_cached_ready;
172
wire                      dcache_wb_uncached_ready;
173
wire     [31:0]           icache_wb_address;
174
wire                      icache_wb_req;
175
wire     [31:0]           icache_wb_adr;
176 35 csantifort
wire     [127:0]          icache_wb_read_data;
177 16 csantifort
wire                      icache_wb_ready;
178
 
179
wire                      conflict;
180 20 csantifort
wire                      rn_use_read;
181
wire                      rm_use_read;
182
wire                      rs_use_read;
183
wire                      rd_use_read;
184 16 csantifort
 
185
// data abort has priority
186
assign decode_fault_status  = dabt_trigger ? dabt_fault_status  : iabt_fault_status;
187
assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
188
assign decode_fault         = dabt_trigger | iabt_trigger;
189
 
190 35 csantifort
assign core_stall           = fetch_stall || mem_stall || exec_stall;
191 16 csantifort
 
192
// ======================================
193
//  Fetch Stage
194
// ======================================
195
a25_fetch u_fetch (
196
    .i_clk                              ( i_clk                             ),
197
    .i_mem_stall                        ( mem_stall                         ),
198 35 csantifort
    .i_exec_stall                       ( exec_stall                        ),
199 16 csantifort
    .i_conflict                         ( conflict                          ),
200
    .i_system_rdy                       ( i_system_rdy                      ),
201
    .o_fetch_stall                      ( fetch_stall                       ),
202
 
203
    .i_iaddress                         ( {execute_iaddress[31:2], 2'd0}    ),
204
    .i_iaddress_valid                   ( execute_iaddress_valid            ),
205
    .i_iaddress_nxt                     ( execute_iaddress_nxt              ),
206
    .o_fetch_instruction                ( fetch_instruction                 ),
207
    .i_cache_enable                     ( cache_enable                      ),
208
    .i_cache_flush                      ( cache_flush                       ),
209
    .i_cacheable_area                   ( cacheable_area                    ),
210
 
211
    .o_wb_req                           ( icache_wb_req                     ),
212
    .o_wb_address                       ( icache_wb_address                 ),
213
    .i_wb_read_data                     ( icache_wb_read_data               ),
214
    .i_wb_ready                         ( icache_wb_ready                   )
215
);
216
 
217
 
218
// ======================================
219
//  Decode Stage
220
// ======================================
221
a25_decode u_decode (
222
    .i_clk                              ( i_clk                             ),
223 35 csantifort
    .i_core_stall                       ( core_stall                        ),
224
 
225 16 csantifort
    // Instruction fetch or data read signals
226
    .i_fetch_instruction                ( fetch_instruction                 ),
227
    .i_execute_iaddress                 ( execute_iaddress                  ),
228
    .i_execute_daddress                 ( execute_daddress                  ),
229
    .i_adex                             ( adex                              ),
230
    .i_iabt                             ( 1'd0                              ),
231
    .i_dabt                             ( 1'd0                              ),
232
    .i_abt_status                       ( 8'd0                              ),
233
 
234
    .i_irq                              ( i_irq                             ),
235
    .i_firq                             ( i_firq                            ),
236
    .i_execute_status_bits              ( execute_status_bits               ),
237
    .i_multiply_done                    ( multiply_done                     ),
238
 
239
    .o_status_bits_mode                 ( status_bits_mode                  ),
240
    .o_status_bits_irq_mask             ( status_bits_irq_mask              ),
241
    .o_status_bits_firq_mask            ( status_bits_firq_mask             ),
242
    .o_imm32                            ( imm32                             ),
243
    .o_imm_shift_amount                 ( imm_shift_amount                  ),
244
    .o_shift_imm_zero                   ( shift_imm_zero                    ),
245
    .o_condition                        ( condition                         ),
246
    .o_decode_exclusive                 ( decode_exclusive                  ),
247
    .o_decode_iaccess                   ( decode_iaccess                    ),
248
    .o_decode_daccess                   ( decode_daccess                    ),
249
    .o_rm_sel                           ( rm_sel                            ),
250
    .o_rs_sel                           ( rs_sel                            ),
251
    .o_load_rd                          ( decode_load_rd                    ),
252
    .o_rn_sel                           ( rn_sel                            ),
253
    .o_barrel_shift_amount_sel          ( barrel_shift_amount_sel           ),
254
    .o_barrel_shift_data_sel            ( barrel_shift_data_sel             ),
255
    .o_barrel_shift_function            ( barrel_shift_function             ),
256
    .o_alu_function                     ( alu_function                      ),
257
    .o_multiply_function                ( multiply_function                 ),
258
    .o_interrupt_vector_sel             ( interrupt_vector_sel              ),
259
    .o_iaddress_sel                     ( iaddress_sel                      ),
260
    .o_daddress_sel                     ( daddress_sel                      ),
261
    .o_pc_sel                           ( pc_sel                            ),
262
    .o_byte_enable_sel                  ( byte_enable_sel                   ),
263
    .o_status_bits_sel                  ( status_bits_sel                   ),
264
    .o_reg_write_sel                    ( reg_write_sel                     ),
265
    .o_user_mode_regs_store_nxt         ( user_mode_regs_store_nxt          ),
266
    .o_firq_not_user_mode               ( firq_not_user_mode                ),
267 83 csantifort
    .o_use_carry_in                     ( use_carry_in                      ),
268 16 csantifort
    .o_write_data_wen                   ( write_data_wen                    ),
269
    .o_base_address_wen                 ( base_address_wen                  ),
270
    .o_pc_wen                           ( pc_wen                            ),
271
    .o_reg_bank_wen                     ( reg_bank_wen                      ),
272
    .o_status_bits_flags_wen            ( status_bits_flags_wen             ),
273
    .o_status_bits_mode_wen             ( status_bits_mode_wen              ),
274
    .o_status_bits_irq_mask_wen         ( status_bits_irq_mask_wen          ),
275
    .o_status_bits_firq_mask_wen        ( status_bits_firq_mask_wen         ),
276
 
277
    .o_copro_opcode1                    ( copro_opcode1                     ),
278
    .o_copro_opcode2                    ( copro_opcode2                     ),
279
    .o_copro_crn                        ( copro_crn                         ),
280
    .o_copro_crm                        ( copro_crm                         ),
281
    .o_copro_num                        ( copro_num                         ),
282
    .o_copro_operation                  ( copro_operation                   ),
283
    .o_copro_write_data_wen             ( copro_write_data_wen              ),
284
 
285
    .o_iabt_trigger                     ( iabt_trigger                      ),
286
    .o_iabt_address                     ( iabt_fault_address                ),
287
    .o_iabt_status                      ( iabt_fault_status                 ),
288
    .o_dabt_trigger                     ( dabt_trigger                      ),
289
    .o_dabt_address                     ( dabt_fault_address                ),
290
    .o_dabt_status                      ( dabt_fault_status                 ),
291
 
292 20 csantifort
    .o_conflict                         ( conflict                          ),
293
    .o_rn_use_read                      ( rn_use_read                       ),
294
    .o_rm_use_read                      ( rm_use_read                       ),
295
    .o_rs_use_read                      ( rs_use_read                       ),
296
    .o_rd_use_read                      ( rd_use_read                       )
297 16 csantifort
);
298
 
299
 
300
// ======================================
301
//  Execute Stage
302
// ======================================
303
a25_execute u_execute (
304
    .i_clk                              ( i_clk                             ),
305 35 csantifort
    .i_core_stall                       ( core_stall                        ),
306 16 csantifort
    .i_mem_stall                        ( mem_stall                         ),
307 35 csantifort
    .o_exec_stall                       ( exec_stall                        ),
308 16 csantifort
 
309
    .i_wb_read_data                     ( wb_read_data                      ),
310
    .i_wb_read_data_valid               ( wb_read_data_valid                ),
311
    .i_wb_load_rd                       ( wb_load_rd                        ),
312
 
313
    .i_copro_read_data                  ( copro_read_data                   ),
314
 
315
    .o_write_data                       ( write_data                        ),
316
    .o_copro_write_data                 ( copro_write_data                  ),
317
    .o_iaddress                         ( execute_iaddress                  ),
318
    .o_iaddress_valid                   ( execute_iaddress_valid            ),
319
    .o_iaddress_nxt                     ( execute_iaddress_nxt              ),
320
    .o_daddress                         ( execute_daddress                  ),
321
    .o_daddress_nxt                     ( execute_daddress_nxt              ),
322
    .o_daddress_valid                   ( execute_daddress_valid            ),
323
    .o_byte_enable                      ( byte_enable                       ),
324
    .o_write_enable                     ( write_enable                      ),
325
    .o_exclusive                        ( exclusive                         ),
326
    .o_priviledged                      (                                   ),
327
    .o_exec_load_rd                     ( exec_load_rd                      ),
328
 
329
    .o_adex                             ( adex                              ),
330
    .o_status_bits                      ( execute_status_bits               ),
331
    .o_multiply_done                    ( multiply_done                     ),
332
 
333
    .i_status_bits_mode                 ( status_bits_mode                  ),
334
    .i_status_bits_irq_mask             ( status_bits_irq_mask              ),
335
    .i_status_bits_firq_mask            ( status_bits_firq_mask             ),
336
    .i_imm32                            ( imm32                             ),
337
    .i_imm_shift_amount                 ( imm_shift_amount                  ),
338
    .i_shift_imm_zero                   ( shift_imm_zero                    ),
339
    .i_condition                        ( condition                         ),
340
    .i_decode_exclusive                 ( decode_exclusive                  ),
341
    .i_decode_iaccess                   ( decode_iaccess                    ),
342
    .i_decode_daccess                   ( decode_daccess                    ),
343
    .i_rm_sel                           ( rm_sel                            ),
344
    .i_rs_sel                           ( rs_sel                            ),
345
    .i_decode_load_rd                   ( decode_load_rd                    ),
346
    .i_rn_sel                           ( rn_sel                            ),
347
    .i_barrel_shift_amount_sel          ( barrel_shift_amount_sel           ),
348
    .i_barrel_shift_data_sel            ( barrel_shift_data_sel             ),
349
    .i_barrel_shift_function            ( barrel_shift_function             ),
350
    .i_alu_function                     ( alu_function                      ),
351
    .i_multiply_function                ( multiply_function                 ),
352
    .i_interrupt_vector_sel             ( interrupt_vector_sel              ),
353
    .i_iaddress_sel                     ( iaddress_sel                      ),
354
    .i_daddress_sel                     ( daddress_sel                      ),
355
    .i_pc_sel                           ( pc_sel                            ),
356
    .i_byte_enable_sel                  ( byte_enable_sel                   ),
357
    .i_status_bits_sel                  ( status_bits_sel                   ),
358
    .i_reg_write_sel                    ( reg_write_sel                     ),
359
    .i_user_mode_regs_store_nxt         ( user_mode_regs_store_nxt          ),
360 83 csantifort
    .i_firq_not_user_mode               ( firq_not_user_mode                ),
361
    .i_use_carry_in                     ( use_carry_in                      ),
362 16 csantifort
    .i_write_data_wen                   ( write_data_wen                    ),
363
    .i_base_address_wen                 ( base_address_wen                  ),
364
    .i_pc_wen                           ( pc_wen                            ),
365
    .i_reg_bank_wen                     ( reg_bank_wen                      ),
366
    .i_status_bits_flags_wen            ( status_bits_flags_wen             ),
367
    .i_status_bits_mode_wen             ( status_bits_mode_wen              ),
368
    .i_status_bits_irq_mask_wen         ( status_bits_irq_mask_wen          ),
369
    .i_status_bits_firq_mask_wen        ( status_bits_firq_mask_wen         ),
370
    .i_copro_write_data_wen             ( copro_write_data_wen              ),
371 20 csantifort
    .i_conflict                         ( conflict                          ),
372
    .i_rn_use_read                      ( rn_use_read                       ),
373
    .i_rm_use_read                      ( rm_use_read                       ),
374
    .i_rs_use_read                      ( rs_use_read                       ),
375
    .i_rd_use_read                      ( rd_use_read                       )
376 16 csantifort
);
377
 
378
 
379
// ======================================
380
//  Memory access stage with data cache
381
// ======================================
382
a25_mem u_mem (
383
    .i_clk                              ( i_clk                             ),
384
    .i_fetch_stall                      ( fetch_stall                       ),
385 35 csantifort
    .i_exec_stall                       ( exec_stall                        ),
386 16 csantifort
    .o_mem_stall                        ( mem_stall                         ),
387
 
388
    .i_daddress                         ( execute_daddress                  ),
389
    .i_daddress_valid                   ( execute_daddress_valid            ),
390
    .i_daddress_nxt                     ( execute_daddress_nxt              ),
391
    .i_write_data                       ( write_data                        ),
392
    .i_write_enable                     ( write_enable                      ),
393
    .i_byte_enable                      ( byte_enable                       ),
394
    .i_exclusive                        ( exclusive                         ),
395
    .i_exec_load_rd                     ( exec_load_rd                      ),
396
 
397
    .o_mem_read_data                    ( mem_read_data                     ),
398
    .o_mem_read_data_valid              ( mem_read_data_valid               ),
399
    .o_mem_load_rd                      ( mem_load_rd                       ),
400
 
401
    .i_cache_enable                     ( cache_enable                      ),
402
    .i_cache_flush                      ( cache_flush                       ),
403
    .i_cacheable_area                   ( cacheable_area                    ),
404
 
405
    .o_wb_cached_req                    ( dcache_wb_cached_req              ),
406
    .o_wb_uncached_req                  ( dcache_wb_uncached_req            ),
407
    .o_wb_write                         ( dcache_wb_write                   ),
408
    .o_wb_write_data                    ( dcache_wb_write_data              ),
409
    .o_wb_byte_enable                   ( dcache_wb_byte_enable             ),
410
    .o_wb_address                       ( dcache_wb_address                 ),
411
    .i_wb_cached_ready                  ( dcache_wb_cached_ready            ),
412 35 csantifort
    .i_wb_cached_rdata                  ( dcache_wb_cached_rdata            ),
413
    .i_wb_uncached_ready                ( dcache_wb_uncached_ready          ),
414
    .i_wb_uncached_rdata                ( dcache_wb_cached_rdata            )
415 16 csantifort
);
416
 
417
 
418
// ======================================
419
//  Write back stage with data cache
420
// ======================================
421
a25_write_back u_write_back (
422
    .i_clk                              ( i_clk                             ),
423
    .i_mem_stall                        ( mem_stall                         ),
424
 
425
    .i_daddress                         ( execute_daddress                  ),
426
    .i_daddress_valid                   ( execute_daddress_valid            ),
427
 
428
    .i_mem_read_data                    ( mem_read_data                     ),
429
    .i_mem_read_data_valid              ( mem_read_data_valid               ),
430
    .i_mem_load_rd                      ( mem_load_rd                       ),
431
 
432
    .o_wb_read_data                     ( wb_read_data                      ),
433
    .o_wb_read_data_valid               ( wb_read_data_valid                ),
434
    .o_wb_load_rd                       ( wb_load_rd                        )
435
);
436 35 csantifort
 
437
 
438
 
439
 
440 16 csantifort
// ======================================
441
//  Wishbone Master I/F
442
// ======================================
443
a25_wishbone u_wishbone (
444
    // CPU Side
445
    .i_clk                              ( i_clk                             ),
446
 
447 35 csantifort
    // Port 0 - dcache uncached
448
    .i_port0_req                        ( dcache_wb_uncached_req            ),
449 39 csantifort
    .o_port0_ack                        ( dcache_wb_uncached_ready          ),
450 35 csantifort
    .i_port0_write                      ( dcache_wb_write                   ),
451
    .i_port0_wdata                      ( dcache_wb_write_data              ),
452
    .i_port0_be                         ( dcache_wb_byte_enable             ),
453
    .i_port0_addr                       ( dcache_wb_address                 ),
454 53 csantifort
    .o_port0_rdata                      (                                   ),
455 16 csantifort
 
456 35 csantifort
    // Port 1 - dcache cached
457
    .i_port1_req                        ( dcache_wb_cached_req              ),
458 39 csantifort
    .o_port1_ack                        ( dcache_wb_cached_ready            ),
459 35 csantifort
    .i_port1_write                      ( dcache_wb_write                   ),
460
    .i_port1_wdata                      ( dcache_wb_write_data              ),
461
    .i_port1_be                         ( dcache_wb_byte_enable             ),
462
    .i_port1_addr                       ( dcache_wb_address                 ),
463
    .o_port1_rdata                      ( dcache_wb_cached_rdata            ),
464 16 csantifort
 
465 35 csantifort
    // Port 2 - instruction cache accesses, read only
466
    .i_port2_req                        ( icache_wb_req                     ),
467 39 csantifort
    .o_port2_ack                        ( icache_wb_ready                   ),
468 35 csantifort
    .i_port2_write                      ( 1'd0                              ),
469
    .i_port2_wdata                      ( 128'd0                            ),
470
    .i_port2_be                         ( 16'd0                             ),
471
    .i_port2_addr                       ( icache_wb_address                 ),
472
    .o_port2_rdata                      ( icache_wb_read_data               ),
473
 
474
    // Wishbone
475 16 csantifort
    .o_wb_adr                           ( o_wb_adr                          ),
476
    .o_wb_sel                           ( o_wb_sel                          ),
477
    .o_wb_we                            ( o_wb_we                           ),
478
    .i_wb_dat                           ( i_wb_dat                          ),
479
    .o_wb_dat                           ( o_wb_dat                          ),
480
    .o_wb_cyc                           ( o_wb_cyc                          ),
481
    .o_wb_stb                           ( o_wb_stb                          ),
482
    .i_wb_ack                           ( i_wb_ack                          ),
483
    .i_wb_err                           ( i_wb_err                          )
484
);
485
 
486
 
487
// ======================================
488
//  Co-Processor #15
489
// ======================================
490
a25_coprocessor u_coprocessor (
491
    .i_clk                              ( i_clk                             ),
492 35 csantifort
    .i_core_stall                       ( core_stall                        ),
493 16 csantifort
 
494
    .i_copro_opcode1                    ( copro_opcode1                     ),
495
    .i_copro_opcode2                    ( copro_opcode2                     ),
496
    .i_copro_crn                        ( copro_crn                         ),
497
    .i_copro_crm                        ( copro_crm                         ),
498
    .i_copro_num                        ( copro_num                         ),
499
    .i_copro_operation                  ( copro_operation                   ),
500
    .i_copro_write_data                 ( copro_write_data                  ),
501
 
502
    .i_fault                            ( decode_fault                      ),
503
    .i_fault_status                     ( decode_fault_status               ),
504
    .i_fault_address                    ( decode_fault_address              ),
505
 
506
    .o_copro_read_data                  ( copro_read_data                   ),
507
    .o_cache_enable                     ( cache_enable                      ),
508
    .o_cache_flush                      ( cache_flush                       ),
509
    .o_cacheable_area                   ( cacheable_area                    )
510
);
511
 
512
 
513
endmodule
514
 

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