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1 16 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Decode stage of Amber 25 Core                               //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  This module is the most complex part of the Amber core      //
10
//  It decodes and sequences all instructions and handles all   //
11
//  interrupts                                                  //
12
//                                                              //
13
//  Author(s):                                                  //
14
//      - Conor Santifort, csantifort.amber@gmail.com           //
15
//                                                              //
16
//////////////////////////////////////////////////////////////////
17
//                                                              //
18
// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
19
//                                                              //
20
// This source file may be used and distributed without         //
21
// restriction provided that this copyright statement is not    //
22
// removed from the file and that any derivative work contains  //
23
// the original copyright notice and the associated disclaimer. //
24
//                                                              //
25
// This source file is free software; you can redistribute it   //
26
// and/or modify it under the terms of the GNU Lesser General   //
27
// Public License as published by the Free Software Foundation; //
28
// either version 2.1 of the License, or (at your option) any   //
29
// later version.                                               //
30
//                                                              //
31
// This source is distributed in the hope that it will be       //
32
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
33
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
34
// PURPOSE.  See the GNU Lesser General Public License for more //
35
// details.                                                     //
36
//                                                              //
37
// You should have received a copy of the GNU Lesser General    //
38
// Public License along with this source; if not, download it   //
39
// from http://www.opencores.org/lgpl.shtml                     //
40
//                                                              //
41
//////////////////////////////////////////////////////////////////
42 82 csantifort
`include "global_defines.vh"
43 16 csantifort
 
44
module a25_decode
45
(
46
input                       i_clk,
47
input       [31:0]          i_fetch_instruction,
48 35 csantifort
input                       i_core_stall,                   // stall all stages of the Amber core at the same time
49 16 csantifort
input                       i_irq,                          // interrupt request
50
input                       i_firq,                         // Fast interrupt request
51
input                       i_dabt,                         // data abort interrupt request
52
input                       i_iabt,                         // instruction pre-fetch abort flag
53
input                       i_adex,                         // Address Exception
54
input       [31:0]          i_execute_iaddress,             // Registered instruction address output by execute stage
55
input       [31:0]          i_execute_daddress,             // Registered instruction address output by execute stage
56
input       [7:0]           i_abt_status,                   // Abort status
57
input       [31:0]          i_execute_status_bits,          // current status bits values in execute stage
58
input                       i_multiply_done,                // multiply unit is nearly done
59
 
60
 
61
// --------------------------------------------------
62
// Control signals to execute stage
63
// --------------------------------------------------
64
output reg  [31:0]          o_imm32 = 'd0,
65
output reg  [4:0]           o_imm_shift_amount = 'd0,
66
output reg                  o_shift_imm_zero = 'd0,
67
output reg  [3:0]           o_condition = 4'he,             // 4'he = al
68
output reg                  o_decode_exclusive = 'd0,       // exclusive access request ( swap instruction )
69
output reg                  o_decode_iaccess = 1'd1,        // Indicates an instruction access
70
output reg                  o_decode_daccess = 'd0,         // Indicates a data access
71
output reg  [1:0]           o_status_bits_mode = 2'b11,     // SVC
72
output reg                  o_status_bits_irq_mask = 1'd1,
73
output reg                  o_status_bits_firq_mask = 1'd1,
74
 
75
output reg  [3:0]           o_rm_sel  = 'd0,
76
output reg  [3:0]           o_rs_sel  = 'd0,
77
output reg  [7:0]           o_load_rd = 'd0,                // [7] load flags with PC
78
                                                            // [6] load status bits with PC
79
                                                            // [5] Write into User Mode register
80
                                                            // [4] zero-extend load
81
                                                            // [3:0] destination register, Rd
82
output reg  [3:0]           o_rn_sel  = 'd0,
83
output reg  [1:0]           o_barrel_shift_amount_sel = 'd0,
84
output reg  [1:0]           o_barrel_shift_data_sel = 'd0,
85
output reg  [1:0]           o_barrel_shift_function = 'd0,
86
output reg  [8:0]           o_alu_function = 'd0,
87
output reg  [1:0]           o_multiply_function = 'd0,
88
output reg  [2:0]           o_interrupt_vector_sel = 'd0,
89
output reg  [3:0]           o_iaddress_sel = 4'd2,
90
output reg  [3:0]           o_daddress_sel = 4'd2,
91
output reg  [2:0]           o_pc_sel = 3'd2,
92
output reg  [1:0]           o_byte_enable_sel = 'd0,        // byte, halfword or word write
93
output reg  [2:0]           o_status_bits_sel = 'd0,
94
output reg  [2:0]           o_reg_write_sel,
95
output reg                  o_user_mode_regs_store_nxt,
96
output reg                  o_firq_not_user_mode,
97
 
98
output reg                  o_write_data_wen = 'd0,
99
output reg                  o_base_address_wen = 'd0,       // save ldm base address register
100
                                                            // in case of data abort
101
output reg                  o_pc_wen = 1'd1,
102
output reg  [14:0]          o_reg_bank_wen = 'd0,
103
output reg                  o_status_bits_flags_wen = 'd0,
104
output reg                  o_status_bits_mode_wen = 'd0,
105
output reg                  o_status_bits_irq_mask_wen = 'd0,
106
output reg                  o_status_bits_firq_mask_wen = 'd0,
107
 
108
// --------------------------------------------------
109
// Co-Processor interface
110
// --------------------------------------------------
111
output reg  [2:0]           o_copro_opcode1 = 'd0,
112
output reg  [2:0]           o_copro_opcode2 = 'd0,
113
output reg  [3:0]           o_copro_crn = 'd0,
114
output reg  [3:0]           o_copro_crm = 'd0,
115
output reg  [3:0]           o_copro_num = 'd0,
116
output reg  [1:0]           o_copro_operation = 'd0, // 0 = no operation, 
117
                                                     // 1 = Move to Amber Core Register from Coprocessor
118
                                                     // 2 = Move to Coprocessor from Amber Core Register
119
output reg                  o_copro_write_data_wen = 'd0,
120
output                      o_iabt_trigger,
121
output      [31:0]          o_iabt_address,
122
output      [7:0]           o_iabt_status,
123
output                      o_dabt_trigger,
124
output      [31:0]          o_dabt_address,
125
output      [7:0]           o_dabt_status,
126 20 csantifort
output                      o_conflict,
127
output reg                  o_rn_use_read,
128
output reg                  o_rm_use_read,
129
output reg                  o_rs_use_read,
130
output reg                  o_rd_use_read
131 16 csantifort
 
132
);
133
 
134 82 csantifort
`include "a25_localparams.vh"
135
`include "a25_functions.vh"
136 16 csantifort
 
137
localparam [4:0] RST_WAIT1      = 5'd0,
138
                 RST_WAIT2      = 5'd1,
139
                 INT_WAIT1      = 5'd2,
140
                 INT_WAIT2      = 5'd3,
141
                 EXECUTE        = 5'd4,
142
                 PRE_FETCH_EXEC = 5'd5,  // Execute the Pre-Fetched Instruction
143
                 MEM_WAIT1      = 5'd6,  // conditionally decode current instruction, in case
144
                                         // previous instruction does not execute in S2
145
                 MEM_WAIT2      = 5'd7,
146
                 PC_STALL1      = 5'd8,  // Program Counter altered
147
                                         // conditionally decude current instruction, in case
148
                                         // previous instruction does not execute in S2
149
                 PC_STALL2      = 5'd9,
150
                 MTRANS_EXEC1   = 5'd10,
151
                 MTRANS_EXEC2   = 5'd11,
152
                 MTRANS_ABORT   = 5'd12,
153
                 MULT_PROC1     = 5'd13,  // first cycle, save pre fetch instruction
154
                 MULT_PROC2     = 5'd14,  // do multiplication
155
                 MULT_STORE     = 5'd15,  // save RdLo
156
                 MULT_ACCUMU    = 5'd16,  // Accumulate add lower 32 bits
157
                 SWAP_WRITE     = 5'd17,
158
                 SWAP_WAIT1     = 5'd18,
159
                 SWAP_WAIT2     = 5'd19,
160
                 COPRO_WAIT     = 5'd20;
161
 
162
 
163
// ========================================================
164
// Internal signals
165
// ========================================================
166
wire    [31:0]         instruction;
167 35 csantifort
wire    [3:0]          type;                    // regop, mem access etc.
168 16 csantifort
wire                   instruction_iabt;        // abort flag, follows the instruction
169
wire                   instruction_adex;        // address exception flag, follows the instruction
170
wire    [31:0]         instruction_address;     // instruction virtual address, follows 
171
                                                // the instruction
172
wire    [7:0]          instruction_iabt_status; // abort status, follows the instruction
173
wire    [1:0]          instruction_sel;
174
wire    [3:0]          opcode;
175
wire    [7:0]          imm8;
176
wire    [31:0]         offset12;
177
wire    [31:0]         offset24;
178
wire    [4:0]          shift_imm;
179
 
180
wire                   opcode_compare;
181
wire                   mem_op;
182
wire                   load_op;
183
wire                   store_op;
184
wire                   write_pc;
185
wire                   current_write_pc;
186
reg                    load_pc_nxt;
187
reg                    load_pc_r = 'd0;
188
wire                   immediate_shift_op;
189
wire                   rds_use_rs;
190
wire                   branch;
191
wire                   mem_op_pre_indexed;
192
wire                   mem_op_post_indexed;
193
 
194
// Flop inputs
195
wire    [31:0]         imm32_nxt;
196
wire    [4:0]          imm_shift_amount_nxt;
197
wire                   shift_imm_zero_nxt;
198
wire    [3:0]          condition_nxt;
199
reg                    decode_exclusive_nxt;
200
reg                    decode_iaccess_nxt;
201
reg                    decode_daccess_nxt;
202
 
203
reg     [1:0]          barrel_shift_function_nxt;
204
wire    [8:0]          alu_function_nxt;
205
reg     [1:0]          multiply_function_nxt;
206
reg     [1:0]          status_bits_mode_nxt;
207
reg                    status_bits_irq_mask_nxt;
208
reg                    status_bits_firq_mask_nxt;
209
 
210
wire    [3:0]          rm_sel_nxt;
211
wire    [3:0]          rs_sel_nxt;
212
 
213
wire    [3:0]          rn_sel_nxt;
214
reg     [1:0]          barrel_shift_amount_sel_nxt;
215
reg     [1:0]          barrel_shift_data_sel_nxt;
216
reg     [3:0]          iaddress_sel_nxt;
217
reg     [3:0]          daddress_sel_nxt;
218
reg     [2:0]          pc_sel_nxt;
219
reg     [1:0]          byte_enable_sel_nxt;
220
reg     [2:0]          status_bits_sel_nxt;
221
reg     [2:0]          reg_write_sel_nxt;
222
wire                   firq_not_user_mode_nxt;
223
 
224
// ALU Function signals
225
reg                    alu_swap_sel_nxt;
226
reg                    alu_not_sel_nxt;
227
reg     [1:0]          alu_cin_sel_nxt;
228
reg                    alu_cout_sel_nxt;
229
reg     [3:0]          alu_out_sel_nxt;
230
 
231
reg                    write_data_wen_nxt;
232
reg                    copro_write_data_wen_nxt;
233
reg                    base_address_wen_nxt;
234
reg                    pc_wen_nxt;
235
reg     [14:0]         reg_bank_wen_nxt;
236
reg                    status_bits_flags_wen_nxt;
237
reg                    status_bits_mode_wen_nxt;
238
reg                    status_bits_irq_mask_wen_nxt;
239
reg                    status_bits_firq_mask_wen_nxt;
240
 
241
reg                    saved_current_instruction_wen;   // saved load instruction
242
reg                    pre_fetch_instruction_wen;       // pre-fetch instruction
243
 
244
reg     [4:0]          control_state = RST_WAIT1;
245
reg     [4:0]          control_state_nxt;
246
 
247
 
248
wire                   dabt;
249
reg                    dabt_reg = 'd0;
250
reg                    dabt_reg_d1;
251
reg                    iabt_reg = 'd0;
252
reg                    adex_reg = 'd0;
253
reg     [31:0]         fetch_address_r = 'd0;
254
reg     [7:0]          abt_status_reg = 'd0;
255
reg     [31:0]         fetch_instruction_r = 'd0;
256 35 csantifort
reg     [3:0]          fetch_instruction_type_r = 'd0;
257 16 csantifort
reg     [31:0]         saved_current_instruction = 'd0;
258 35 csantifort
reg     [3:0]          saved_current_instruction_type = 'd0;
259 16 csantifort
reg                    saved_current_instruction_iabt = 'd0;          // access abort flag
260
reg                    saved_current_instruction_adex = 'd0;          // address exception
261
reg     [31:0]         saved_current_instruction_address = 'd0;       // virtual address of abort instruction
262
reg     [7:0]          saved_current_instruction_iabt_status = 'd0;   // status of abort instruction
263
reg     [31:0]         pre_fetch_instruction = 'd0;
264 35 csantifort
reg     [3:0]          pre_fetch_instruction_type = 'd0;
265 16 csantifort
reg                    pre_fetch_instruction_iabt = 'd0;              // access abort flag
266
reg                    pre_fetch_instruction_adex = 'd0;              // address exception
267
reg     [31:0]         pre_fetch_instruction_address = 'd0;           // virtual address of abort instruction
268
reg     [7:0]          pre_fetch_instruction_iabt_status = 'd0;       // status of abort instruction
269
reg     [31:0]         hold_instruction = 'd0;
270 35 csantifort
reg     [3:0]          hold_instruction_type = 'd0;
271 16 csantifort
reg                    hold_instruction_iabt = 'd0;                   // access abort flag
272
reg                    hold_instruction_adex = 'd0;                   // address exception
273
reg     [31:0]         hold_instruction_address = 'd0;                // virtual address of abort instruction
274
reg     [7:0]          hold_instruction_iabt_status = 'd0;            // status of abort instruction
275
 
276
wire                   instruction_valid;
277
wire                   instruction_execute;
278 20 csantifort
reg                    instruction_execute_r = 'd0;
279 16 csantifort
 
280
reg     [3:0]          mtrans_reg1;             // the current register being accessed as part of stm/ldm
281
reg     [3:0]          mtrans_reg2;             // the next register being accessed as part of stm/ldm
282
reg     [31:0]         mtrans_instruction_nxt;
283
wire    [15:0]         mtrans_reg2_mask;
284
 
285
wire   [31:0]          mtrans_base_reg_change;
286
wire   [4:0]           mtrans_num_registers;
287
wire                   use_saved_current_instruction;
288
wire                   use_hold_instruction;
289
wire                   use_pre_fetch_instruction;
290
wire                   interrupt;
291 60 csantifort
wire                   interrupt_or_conflict;
292 16 csantifort
wire   [1:0]           interrupt_mode;
293
wire   [2:0]           next_interrupt;
294
reg                    irq = 'd0;
295
reg                    firq = 'd0;
296
wire                   firq_request;
297
wire                   irq_request;
298
wire                   swi_request;
299
wire                   und_request;
300
wire                   dabt_request;
301
reg    [1:0]           copro_operation_nxt;
302
reg                    restore_base_address = 'd0;
303
reg                    restore_base_address_nxt;
304
 
305
wire                   regop_set_flags;
306
 
307
wire    [7:0]          load_rd_nxt;
308
wire                   load_rd_byte;
309
wire                   ldm_user_mode;
310
wire                   ldm_status_bits;
311
wire                   ldm_flags;
312
wire    [6:0]          load_rd_d1_nxt;
313
reg     [6:0]          load_rd_d1 = 'd0;  // MSB is the valid bit
314 35 csantifort
 
315 16 csantifort
wire                   rn_valid;
316
wire                   rm_valid;
317
wire                   rs_valid;
318
wire                   rd_valid;
319
wire                   stm_valid;
320
wire                   rn_conflict1;
321
wire                   rn_conflict2;
322
wire                   rm_conflict1;
323
wire                   rm_conflict2;
324
wire                   rs_conflict1;
325
wire                   rs_conflict2;
326
wire                   rd_conflict1;
327
wire                   rd_conflict2;
328
wire                   stm_conflict1a;
329
wire                   stm_conflict1b;
330
wire                   stm_conflict2a;
331
wire                   stm_conflict2b;
332
wire                   conflict1;          // Register conflict1 with ldr operation
333
wire                   conflict2;          // Register conflict1 with ldr operation
334 35 csantifort
wire                   conflict;           // Register conflict1 with ldr operation
335 16 csantifort
reg                    conflict_r = 'd0;
336 20 csantifort
reg                    rn_conflict1_r = 'd0;
337
reg                    rm_conflict1_r = 'd0;
338
reg                    rs_conflict1_r = 'd0;
339
reg                    rd_conflict1_r = 'd0;
340 16 csantifort
 
341
 
342
// ========================================================
343
// Instruction Abort and Data Abort outputs
344
// ========================================================
345
 
346
assign o_iabt_trigger     = instruction_iabt && o_status_bits_mode == SVC && control_state == INT_WAIT1;
347
assign o_iabt_address     = instruction_address;
348
assign o_iabt_status      = instruction_iabt_status;
349
 
350
assign o_dabt_trigger     = dabt_reg && !dabt_reg_d1;
351
assign o_dabt_address     = fetch_address_r;
352
assign o_dabt_status      = abt_status_reg;
353
 
354
 
355
// ========================================================
356
// Instruction Decode
357
// ========================================================
358
 
359
// for instructions that take more than one cycle
360
// the instruction is saved in the 'saved_mem_instruction'
361
// register and then that register is used for the rest of
362
// the execution of the instruction.
363
// But if the instruction does not execute because of the
364
// condition, then need to select the next instruction to
365
// decode
366
assign use_saved_current_instruction = instruction_execute &&
367
                          ( control_state == MEM_WAIT1     ||
368
                            control_state == MEM_WAIT2     ||
369
                            control_state == MTRANS_EXEC1  ||
370
                            control_state == MTRANS_EXEC2  ||
371
                            control_state == MTRANS_ABORT  ||
372
                            control_state == MULT_PROC1    ||
373
                            control_state == MULT_PROC2    ||
374
                            control_state == MULT_ACCUMU   ||
375
                            control_state == MULT_STORE    ||
376
                            control_state == INT_WAIT1     ||
377
                            control_state == INT_WAIT2     ||
378
                            control_state == SWAP_WRITE    ||
379
                            control_state == SWAP_WAIT1    ||
380
                            control_state == SWAP_WAIT2    ||
381
                            control_state == COPRO_WAIT     );
382
 
383
assign use_hold_instruction = conflict_r;
384
 
385
assign use_pre_fetch_instruction = control_state == PRE_FETCH_EXEC;
386
 
387
 
388
assign instruction_sel  =         use_hold_instruction           ? 2'd3 :  // hold_instruction
389
                                  use_saved_current_instruction  ? 2'd1 :  // saved_current_instruction 
390
                                  use_pre_fetch_instruction      ? 2'd2 :  // pre_fetch_instruction     
391
                                                                   2'd0 ;  // fetch_instruction_r               
392
 
393
assign instruction      =         instruction_sel == 2'd0 ? fetch_instruction_r       :
394
                                  instruction_sel == 2'd1 ? saved_current_instruction :
395
                                  instruction_sel == 2'd3 ? hold_instruction          :
396
                                                            pre_fetch_instruction     ;
397 35 csantifort
 
398
assign type             =         instruction_sel == 2'd0 ? fetch_instruction_type_r       :
399
                                  instruction_sel == 2'd1 ? saved_current_instruction_type :
400
                                  instruction_sel == 2'd3 ? hold_instruction_type          :
401
                                                            pre_fetch_instruction_type     ;
402 16 csantifort
 
403
// abort flag
404
assign instruction_iabt =         instruction_sel == 2'd0 ? iabt_reg                       :
405
                                  instruction_sel == 2'd1 ? saved_current_instruction_iabt :
406
                                  instruction_sel == 2'd3 ? hold_instruction_iabt          :
407
                                                            pre_fetch_instruction_iabt     ;
408
 
409
assign instruction_address =      instruction_sel == 2'd0 ? fetch_address_r                   :
410
                                  instruction_sel == 2'd1 ? saved_current_instruction_address :
411
                                  instruction_sel == 2'd3 ? hold_instruction_address          :
412
                                                            pre_fetch_instruction_address     ;
413
 
414
assign instruction_iabt_status =  instruction_sel == 2'd0 ? abt_status_reg                        :
415
                                  instruction_sel == 2'd1 ? saved_current_instruction_iabt_status :
416
                                  instruction_sel == 2'd3 ? hold_instruction_iabt_status          :
417
                                                            pre_fetch_instruction_iabt_status     ;
418
 
419
// instruction address exception
420
assign instruction_adex =         instruction_sel == 2'd0 ? adex_reg                       :
421
                                  instruction_sel == 2'd1 ? saved_current_instruction_adex :
422
                                  instruction_sel == 2'd3 ? hold_instruction_adex          :
423
                                                            pre_fetch_instruction_adex     ;
424
 
425
 
426
// ========================================================
427
// Fixed fields within the instruction
428
// ========================================================
429
 
430
assign opcode               = instruction[24:21];
431
assign condition_nxt        = instruction[31:28];
432
 
433
assign rm_sel_nxt           = instruction[3:0];
434
assign rn_sel_nxt           = branch ? 4'd15 : instruction[19:16]; // Use PC to calculate branch destination
435
assign rs_sel_nxt           = control_state == SWAP_WRITE  ? instruction[3:0]   : // Rm gets written out to memory
436
                              type == MTRANS               ? mtrans_reg1         :
437
                              branch                       ? 4'd15              : // Update the PC
438
                              rds_use_rs                   ? instruction[11:8]  :
439
                                                             instruction[15:12] ;
440
 
441
// Load from memory into registers
442 82 csantifort
assign ldm_user_mode        = type == MTRANS && {instruction[22],instruction[20],instruction[15]} == 3'b110;
443 16 csantifort
assign ldm_flags            = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22];
444
assign ldm_status_bits      = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR;
445
assign load_rd_byte         = (type == TRANS || type == SWAP) && instruction[22];
446
assign load_rd_nxt          = {ldm_flags, ldm_status_bits, ldm_user_mode, load_rd_byte, rs_sel_nxt};
447
 
448
 
449
                            // MSB indicates valid dirty target register
450
assign load_rd_d1_nxt       = {o_decode_daccess && !o_write_data_wen, o_load_rd[3:0]};
451
assign shift_imm            = instruction[11:7];
452
assign offset12             = { 20'h0, instruction[11:0]};
453
assign offset24             = {{6{instruction[23]}}, instruction[23:0], 2'd0 }; // sign extend
454
assign imm8                 = instruction[7:0];
455
 
456
assign immediate_shift_op   = instruction[25];
457
assign rds_use_rs           = (type == REGOP && !instruction[25] && instruction[4]) ||
458
                              (type == MULT &&
459
                               (control_state == MULT_PROC1  ||
460
                                control_state == MULT_PROC2  ||
461 60 csantifort
//                                instruction_valid && !interrupt )) ;
462
// remove the '!conflict' term from the interrupt logic used here
463
// to break a combinational loop
464
                                (instruction_valid && !interrupt_or_conflict))) ;
465
 
466
 
467 16 csantifort
assign branch               = type == BRANCH;
468
assign opcode_compare       = opcode == CMP || opcode == CMN || opcode == TEQ || opcode == TST ;
469
assign mem_op               = type == TRANS;
470
assign load_op              = mem_op && instruction[20];
471
assign store_op             = mem_op && !instruction[20];
472
assign write_pc             = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_r || load_pc_nxt;
473
assign current_write_pc     = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_nxt;
474
assign regop_set_flags      = type == REGOP && instruction[20];
475
 
476
assign mem_op_pre_indexed   =  instruction[24] && instruction[21];
477
assign mem_op_post_indexed  = !instruction[24];
478
 
479
assign imm32_nxt            =  // add 0 to Rm
480
                               type == MULT               ? {  32'd0                      } :
481
 
482
                               // 4 x number of registers
483
                               type == MTRANS             ? {  mtrans_base_reg_change     } :
484
                               type == BRANCH             ? {  offset24                   } :
485
                               type == TRANS              ? {  offset12                   } :
486
                               instruction[11:8] == 4'h0  ? {            24'h0, imm8[7:0] } :
487
                               instruction[11:8] == 4'h1  ? { imm8[1:0], 24'h0, imm8[7:2] } :
488
                               instruction[11:8] == 4'h2  ? { imm8[3:0], 24'h0, imm8[7:4] } :
489
                               instruction[11:8] == 4'h3  ? { imm8[5:0], 24'h0, imm8[7:6] } :
490
                               instruction[11:8] == 4'h4  ? { imm8[7:0], 24'h0            } :
491
                               instruction[11:8] == 4'h5  ? { 2'h0,  imm8[7:0], 22'h0     } :
492
                               instruction[11:8] == 4'h6  ? { 4'h0,  imm8[7:0], 20'h0     } :
493
                               instruction[11:8] == 4'h7  ? { 6'h0,  imm8[7:0], 18'h0     } :
494
                               instruction[11:8] == 4'h8  ? { 8'h0,  imm8[7:0], 16'h0     } :
495
                               instruction[11:8] == 4'h9  ? { 10'h0, imm8[7:0], 14'h0     } :
496
                               instruction[11:8] == 4'ha  ? { 12'h0, imm8[7:0], 12'h0     } :
497
                               instruction[11:8] == 4'hb  ? { 14'h0, imm8[7:0], 10'h0     } :
498
                               instruction[11:8] == 4'hc  ? { 16'h0, imm8[7:0], 8'h0      } :
499
                               instruction[11:8] == 4'hd  ? { 18'h0, imm8[7:0], 6'h0      } :
500
                               instruction[11:8] == 4'he  ? { 20'h0, imm8[7:0], 4'h0      } :
501
                                                            { 22'h0, imm8[7:0], 2'h0      } ;
502
 
503
 
504
assign imm_shift_amount_nxt = shift_imm ;
505
 
506
       // This signal is encoded in the decode stage because 
507
       // it is on the critical path in the execute stage
508
assign shift_imm_zero_nxt   = imm_shift_amount_nxt == 5'd0 &&       // immediate amount = 0
509
                              barrel_shift_amount_sel_nxt == 2'd2;  // shift immediate amount
510
 
511
assign alu_function_nxt     = { alu_swap_sel_nxt,
512
                                alu_not_sel_nxt,
513
                                alu_cin_sel_nxt,
514
                                alu_cout_sel_nxt,
515
                                alu_out_sel_nxt  };
516
 
517
// ========================================================
518
// Register Conflict Detection
519
// ========================================================
520 20 csantifort
assign rn_valid       = type == REGOP || type == MULT || type == SWAP || type == TRANS || type == MTRANS || type == CODTRANS;
521
assign rm_valid       = type == REGOP || type == MULT || type == SWAP || (type == TRANS && immediate_shift_op);
522
assign rs_valid       = rds_use_rs;
523
assign rd_valid       = (type == TRANS  && store_op) || (type == REGOP || type == SWAP);
524
assign stm_valid      = type == MTRANS && !instruction[20];   // stm instruction
525
 
526
 
527
assign rn_conflict1   = instruction_execute   && rn_valid  && ( load_rd_d1_nxt[4] && rn_sel_nxt         == load_rd_d1_nxt[3:0] );
528
assign rn_conflict2   = instruction_execute_r && rn_valid  && ( load_rd_d1    [4] && rn_sel_nxt         == load_rd_d1    [3:0] );
529
assign rm_conflict1   = instruction_execute   && rm_valid  && ( load_rd_d1_nxt[4] && rm_sel_nxt         == load_rd_d1_nxt[3:0] );
530
assign rm_conflict2   = instruction_execute_r && rm_valid  && ( load_rd_d1    [4] && rm_sel_nxt         == load_rd_d1    [3:0] );
531
assign rs_conflict1   = instruction_execute   && rs_valid  && ( load_rd_d1_nxt[4] && rs_sel_nxt         == load_rd_d1_nxt[3:0] );
532
assign rs_conflict2   = instruction_execute_r && rs_valid  && ( load_rd_d1    [4] && rs_sel_nxt         == load_rd_d1    [3:0] );
533
assign rd_conflict1   = instruction_execute   && rd_valid  && ( load_rd_d1_nxt[4] && instruction[15:12] == load_rd_d1_nxt[3:0] );
534
assign rd_conflict2   = instruction_execute_r && rd_valid  && ( load_rd_d1    [4] && instruction[15:12] == load_rd_d1    [3:0] );
535
 
536
assign stm_conflict1a = instruction_execute   && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg1        == load_rd_d1_nxt[3:0] );
537
assign stm_conflict1b = instruction_execute   && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg2        == load_rd_d1_nxt[3:0] );
538
assign stm_conflict2a = instruction_execute_r && stm_valid && ( load_rd_d1    [4] && mtrans_reg1        == load_rd_d1    [3:0] );
539
assign stm_conflict2b = instruction_execute_r && stm_valid && ( load_rd_d1    [4] && mtrans_reg2        == load_rd_d1    [3:0] );
540 16 csantifort
 
541
assign conflict1      = instruction_valid &&
542
                        (rn_conflict1 || rm_conflict1 || rs_conflict1 || rd_conflict1 ||
543
                         stm_conflict1a || stm_conflict1b);
544
 
545 20 csantifort
assign conflict2      = instruction_valid && (stm_conflict2a || stm_conflict2b);
546 16 csantifort
 
547
assign conflict       = conflict1 || conflict2;
548
 
549
 
550
always @( posedge i_clk )
551 35 csantifort
    if ( !i_core_stall )
552 16 csantifort
        begin
553 20 csantifort
        conflict_r              <= conflict;
554
        instruction_execute_r   <= instruction_execute;
555
        rn_conflict1_r          <= rn_conflict1 && instruction_execute;
556
        rm_conflict1_r          <= rm_conflict1 && instruction_execute;
557
        rs_conflict1_r          <= rs_conflict1 && instruction_execute;
558
        rd_conflict1_r          <= rd_conflict1 && instruction_execute;
559
        o_rn_use_read           <= instruction_valid && ( rn_conflict1_r || rn_conflict2 );
560
        o_rm_use_read           <= instruction_valid && ( rm_conflict1_r || rm_conflict2 );
561
        o_rs_use_read           <= instruction_valid && ( rs_conflict1_r || rs_conflict2 );
562
        o_rd_use_read           <= instruction_valid && ( rd_conflict1_r || rd_conflict2 );
563 16 csantifort
        end
564
 
565
assign o_conflict = conflict;
566
 
567
 
568
// ========================================================
569
// MTRANS Operations
570
// ========================================================
571
 
572
   // Bit 15 = r15
573
   // Bit 0  = r0
574
   // In ldm and stm instructions r0 is loaded or stored first 
575
always @*
576
    casez ( instruction[15:0] )
577
    16'b???????????????1 : mtrans_reg1 = 4'h0 ;
578
    16'b??????????????10 : mtrans_reg1 = 4'h1 ;
579
    16'b?????????????100 : mtrans_reg1 = 4'h2 ;
580
    16'b????????????1000 : mtrans_reg1 = 4'h3 ;
581
    16'b???????????10000 : mtrans_reg1 = 4'h4 ;
582
    16'b??????????100000 : mtrans_reg1 = 4'h5 ;
583
    16'b?????????1000000 : mtrans_reg1 = 4'h6 ;
584
    16'b????????10000000 : mtrans_reg1 = 4'h7 ;
585
    16'b???????100000000 : mtrans_reg1 = 4'h8 ;
586
    16'b??????1000000000 : mtrans_reg1 = 4'h9 ;
587
    16'b?????10000000000 : mtrans_reg1 = 4'ha ;
588
    16'b????100000000000 : mtrans_reg1 = 4'hb ;
589
    16'b???1000000000000 : mtrans_reg1 = 4'hc ;
590
    16'b??10000000000000 : mtrans_reg1 = 4'hd ;
591
    16'b?100000000000000 : mtrans_reg1 = 4'he ;
592
    default              : mtrans_reg1 = 4'hf ;
593
    endcase
594
 
595
 
596
assign mtrans_reg2_mask = 1'd1<<mtrans_reg1;
597
 
598
always @*
599
    casez ( instruction[15:0] & ~mtrans_reg2_mask )
600
    16'b???????????????1 : mtrans_reg2 = 4'h0 ;
601
    16'b??????????????10 : mtrans_reg2 = 4'h1 ;
602
    16'b?????????????100 : mtrans_reg2 = 4'h2 ;
603
    16'b????????????1000 : mtrans_reg2 = 4'h3 ;
604
    16'b???????????10000 : mtrans_reg2 = 4'h4 ;
605
    16'b??????????100000 : mtrans_reg2 = 4'h5 ;
606
    16'b?????????1000000 : mtrans_reg2 = 4'h6 ;
607
    16'b????????10000000 : mtrans_reg2 = 4'h7 ;
608
    16'b???????100000000 : mtrans_reg2 = 4'h8 ;
609
    16'b??????1000000000 : mtrans_reg2 = 4'h9 ;
610
    16'b?????10000000000 : mtrans_reg2 = 4'ha ;
611
    16'b????100000000000 : mtrans_reg2 = 4'hb ;
612
    16'b???1000000000000 : mtrans_reg2 = 4'hc ;
613
    16'b??10000000000000 : mtrans_reg2 = 4'hd ;
614
    16'b?100000000000000 : mtrans_reg2 = 4'he ;
615
    default              : mtrans_reg2 = 4'hf ;
616
    endcase
617
 
618
always @*
619
    casez (instruction[15:0])
620
    16'b???????????????1 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 1],  1'd0};
621
    16'b??????????????10 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 2],  2'd0};
622
    16'b?????????????100 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 3],  3'd0};
623
    16'b????????????1000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 4],  4'd0};
624
    16'b???????????10000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 5],  5'd0};
625
    16'b??????????100000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 6],  6'd0};
626
    16'b?????????1000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 7],  7'd0};
627
    16'b????????10000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 8],  8'd0};
628
    16'b???????100000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 9],  9'd0};
629
    16'b??????1000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:10], 10'd0};
630
    16'b?????10000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:11], 11'd0};
631
    16'b????100000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:12], 12'd0};
632
    16'b???1000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:13], 13'd0};
633
    16'b??10000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:14], 14'd0};
634
    16'b?100000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15   ], 15'd0};
635
    default              : mtrans_instruction_nxt = {instruction[31:16],                     16'd0};
636
    endcase
637
 
638
 
639
// number of registers to be stored
640
assign mtrans_num_registers =   {4'd0, instruction[15]} +
641
                                {4'd0, instruction[14]} +
642
                                {4'd0, instruction[13]} +
643
                                {4'd0, instruction[12]} +
644
                                {4'd0, instruction[11]} +
645
                                {4'd0, instruction[10]} +
646
                                {4'd0, instruction[ 9]} +
647
                                {4'd0, instruction[ 8]} +
648
                                {4'd0, instruction[ 7]} +
649
                                {4'd0, instruction[ 6]} +
650
                                {4'd0, instruction[ 5]} +
651
                                {4'd0, instruction[ 4]} +
652
                                {4'd0, instruction[ 3]} +
653
                                {4'd0, instruction[ 2]} +
654
                                {4'd0, instruction[ 1]} +
655
                                {4'd0, instruction[ 0]} ;
656
 
657
// 4 x number of registers to be stored
658
assign mtrans_base_reg_change = {25'd0, mtrans_num_registers, 2'd0};
659
 
660
// ========================================================
661
// Interrupts
662
// ========================================================
663
 
664
assign firq_request = firq && !i_execute_status_bits[26];
665
assign irq_request  = irq  && !i_execute_status_bits[27];
666
assign swi_request  = type == SWI;
667
assign dabt_request = dabt_reg;
668
 
669
// copro15 and copro13 only supports reg trans opcodes
670
// all other opcodes involving co-processors cause an 
671
// undefined instrution interrupt
672
assign und_request  =   type == CODTRANS ||
673
                        type == COREGOP  ||
674
                      ( type == CORTRANS && instruction[11:8] != 4'd15 );
675
 
676
 
677
  // in order of priority !!                 
678
  // Highest 
679
  // 1 Reset
680
  // 2 Data Abort (including data TLB miss)
681
  // 3 FIRQ
682
  // 4 IRQ
683
  // 5 Prefetch Abort (including prefetch TLB miss)
684
  // 6 Undefined instruction, SWI
685
  // Lowest                        
686
assign next_interrupt = dabt_request     ? 3'd1 :  // Data Abort
687
                        firq_request     ? 3'd2 :  // FIRQ
688
                        irq_request      ? 3'd3 :  // IRQ
689
                        instruction_adex ? 3'd4 :  // Address Exception 
690
                        instruction_iabt ? 3'd5 :  // PreFetch Abort, only triggered 
691
                                                   // if the instruction is used
692
                        und_request      ? 3'd6 :  // Undefined Instruction
693
                        swi_request      ? 3'd7 :  // SWI
694
                                           3'd0 ;  // none             
695
 
696 60 csantifort
 
697
// SWI and undefined instructions do not cause an interrupt in the decode
698
// stage. They only trigger interrupts if they arfe executed, so the
699
// interrupt is triggered if the execute condition is met in the execute stage
700 16 csantifort
assign interrupt      = next_interrupt != 3'd0 &&
701
                        next_interrupt != 3'd7 &&  // SWI
702 17 csantifort
                        next_interrupt != 3'd6 &&  // undefined interrupt
703
                        !conflict               ;  // Wait for conflicts to resolve before
704
                                                   // triggering int
705 16 csantifort
 
706 60 csantifort
 
707
// Added to use in rds_use_rs logic to break a combinational loop invloving
708
// the conflict signal
709
assign interrupt_or_conflict
710
                     =  next_interrupt != 3'd0 &&
711
                        next_interrupt != 3'd7 &&  // SWI
712
                        next_interrupt != 3'd6  ;  // undefined interrupt
713
 
714 16 csantifort
assign interrupt_mode = next_interrupt == 3'd2 ? FIRQ :
715
                        next_interrupt == 3'd3 ? IRQ  :
716
                        next_interrupt == 3'd4 ? SVC  :
717
                        next_interrupt == 3'd5 ? SVC  :
718
                        next_interrupt == 3'd6 ? SVC  :
719
                        next_interrupt == 3'd7 ? SVC  :
720
                        next_interrupt == 3'd1 ? SVC  :
721
                                                 USR  ;
722
 
723
 
724
// ========================================================
725
// Generate control signals
726
// ========================================================
727
always @*
728
    begin
729
    // default mode
730
    status_bits_mode_nxt            = i_execute_status_bits[1:0];   // change to mode in execute stage get reflected
731
                                                                    // back to this stage automatically
732
    status_bits_irq_mask_nxt        = o_status_bits_irq_mask;
733
    status_bits_firq_mask_nxt       = o_status_bits_firq_mask;
734
    decode_exclusive_nxt            = 1'd0;
735
    decode_daccess_nxt              = 1'd0;
736
    decode_iaccess_nxt              = 1'd1;
737
    copro_operation_nxt             = 'd0;
738
 
739
    // Save an instruction to use later
740
    saved_current_instruction_wen   = 1'd0;
741
    pre_fetch_instruction_wen       = 1'd0;
742
    restore_base_address_nxt        = restore_base_address;
743
 
744
    // default Mux Select values
745
    barrel_shift_amount_sel_nxt     = 'd0;  // don't shift the input
746
    barrel_shift_data_sel_nxt       = 'd0;  // immediate value
747
    barrel_shift_function_nxt       = 'd0;
748
    multiply_function_nxt           = 'd0;
749
    iaddress_sel_nxt                = 'd0;
750
    daddress_sel_nxt                = 'd0;
751
    pc_sel_nxt                      = 'd0;
752
    load_pc_nxt                     = 'd0;
753
    byte_enable_sel_nxt             = 'd0;
754
    status_bits_sel_nxt             = 'd0;
755
    reg_write_sel_nxt               = 'd0;
756
    o_user_mode_regs_store_nxt      = 'd0;
757
 
758
    // ALU Muxes
759
    alu_swap_sel_nxt                = 'd0;
760
    alu_not_sel_nxt                 = 'd0;
761
    alu_cin_sel_nxt                 = 'd0;
762
    alu_cout_sel_nxt                = 'd0;
763
    alu_out_sel_nxt                 = 'd0;
764
 
765
    // default Flop Write Enable values
766
    write_data_wen_nxt              = 'd0;
767
    copro_write_data_wen_nxt        = 'd0;
768
    base_address_wen_nxt            = 'd0;
769
    pc_wen_nxt                      = 'd1;
770
    reg_bank_wen_nxt                = 'd0;  // Don't select any
771
 
772
    status_bits_flags_wen_nxt       = 'd0;
773
    status_bits_mode_wen_nxt        = 'd0;
774
    status_bits_irq_mask_wen_nxt    = 'd0;
775
    status_bits_firq_mask_wen_nxt   = 'd0;
776
 
777
    if ( instruction_valid && !interrupt && !conflict )
778
        begin
779
        if ( type == REGOP )
780
            begin
781
            if ( !opcode_compare )
782
                begin
783
                // Check is the load destination is the PC
784
                if (instruction[15:12]  == 4'd15)
785
                    begin
786
                    pc_sel_nxt       = 3'd1; // alu_out
787
                    iaddress_sel_nxt = 4'd1; // alu_out
788
                    end
789
                else
790
                    reg_bank_wen_nxt = decode (instruction[15:12]);
791
                end
792 35 csantifort
 
793 16 csantifort
            if ( !immediate_shift_op )
794 35 csantifort
                begin
795 16 csantifort
                barrel_shift_function_nxt  = instruction[6:5];
796 35 csantifort
                end
797 16 csantifort
 
798
            if ( !immediate_shift_op )
799
                barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
800
 
801
            if ( !immediate_shift_op && instruction[4] )
802
                barrel_shift_amount_sel_nxt = 2'd1; // Shift amount from Rs registter
803
 
804
            if ( !immediate_shift_op && !instruction[4] )
805
                barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount 
806 82 csantifort
 
807
            // regops that do not change the overflow flag
808
            if ( opcode == AND || opcode == EOR || opcode == TST || opcode == TEQ ||
809
                 opcode == ORR || opcode == MOV || opcode == BIC || opcode == MVN )
810
                status_bits_sel_nxt = 3'd5;
811 16 csantifort
 
812
            if ( opcode == ADD || opcode == CMN )   // CMN is just like an ADD
813
                begin
814
                alu_out_sel_nxt  = 4'd1; // Add
815
                end
816
 
817
            if ( opcode == ADC ) // Add with Carry
818
                begin
819
                alu_out_sel_nxt  = 4'd1; // Add
820
                alu_cin_sel_nxt  = 2'd2; // carry in from status_bits
821
                end
822
 
823
            if ( opcode == SUB || opcode == CMP ) // Subtract
824
                begin
825
                alu_out_sel_nxt  = 4'd1; // Add
826
                alu_cin_sel_nxt  = 2'd1; // cin = 1
827
                alu_not_sel_nxt  = 1'd1; // invert B
828
                end
829
 
830
            // SBC (Subtract with Carry) subtracts the value of its 
831
            // second operand and the value of NOT(Carry flag) from
832
            // the value of its first operand.
833
            //  Rd = Rn - shifter_operand - NOT(C Flag)
834
            if ( opcode == SBC ) // Subtract with Carry
835
                begin
836
                alu_out_sel_nxt  = 4'd1; // Add
837
                alu_cin_sel_nxt  = 2'd2; // carry in from status_bits
838
                alu_not_sel_nxt  = 1'd1; // invert B
839
                end
840
 
841
            if ( opcode == RSB ) // Reverse Subtract
842
                begin
843
                alu_out_sel_nxt  = 4'd1; // Add
844
                alu_cin_sel_nxt  = 2'd1; // cin = 1
845
                alu_not_sel_nxt  = 1'd1; // invert B
846
                alu_swap_sel_nxt = 1'd1; // swap A and B
847
                end
848
 
849
            if ( opcode == RSC ) // Reverse Subtract with carry
850
                begin
851
                alu_out_sel_nxt  = 4'd1; // Add
852
                alu_cin_sel_nxt  = 2'd2; // carry in from status_bits
853
                alu_not_sel_nxt  = 1'd1; // invert B
854
                alu_swap_sel_nxt = 1'd1; // swap A and B
855
                end
856
 
857
            if ( opcode == AND || opcode == TST ) // Logical AND, Test  (using AND operator)
858
                begin
859
                alu_out_sel_nxt  = 4'd8;  // AND
860
                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
861
                end
862
 
863
            if ( opcode == EOR || opcode == TEQ ) // Logical Exclusive OR, Test Equivalence (using EOR operator)
864
                begin
865
                alu_out_sel_nxt = 4'd6;  // XOR
866
                alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
867
                end
868
 
869
            if ( opcode == ORR )
870
                begin
871
                alu_out_sel_nxt  = 4'd7; // OR
872
                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
873
                end
874
 
875
            if ( opcode == BIC ) // Bit Clear (using AND & NOT operators)
876
                begin
877
                alu_out_sel_nxt  = 4'd8;  // AND
878
                alu_not_sel_nxt  = 1'd1;  // invert B
879
                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
880
                end
881
 
882
            if ( opcode == MOV ) // Move
883
                begin
884
                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
885
                end
886
 
887
            if ( opcode == MVN ) // Move NOT
888
                begin
889
                alu_not_sel_nxt  = 1'd1; // invert B
890
                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
891
                end
892
            end
893
 
894
        // Load & Store instructions
895
        if ( mem_op )
896
            begin
897
            if ( load_op && instruction[15:12]  == 4'd15 ) // Write to PC
898
                begin
899
                saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
900
                pc_wen_nxt                      = 1'd0; // hold current PC value rather than an instruction fetch
901
                load_pc_nxt                     = 1'd1;
902
                end
903
 
904
            decode_daccess_nxt              = 1'd1; // indicate a valid data access
905
            alu_out_sel_nxt                 = 4'd1; // Add
906
 
907
            if ( !instruction[23] )  // U: Subtract offset
908
                begin
909
                alu_cin_sel_nxt  = 2'd1; // cin = 1
910
                alu_not_sel_nxt  = 1'd1; // invert B
911
                end
912
 
913
            if ( store_op )
914
                begin
915
                write_data_wen_nxt = 1'd1;
916
                if ( type == TRANS && instruction[22] )
917
                    byte_enable_sel_nxt = 2'd1;         // Save byte
918
                end
919
 
920
                // need to update the register holding the address ?
921
                // This is Rn bits [19:16]
922
            if ( mem_op_pre_indexed || mem_op_post_indexed )
923
                begin
924
                // Check is the load destination is the PC
925
                if ( rn_sel_nxt  == 4'd15 )
926
                    pc_sel_nxt = 3'd1;
927
                else
928
                    reg_bank_wen_nxt = decode ( rn_sel_nxt );
929
                end
930
 
931
                // if post-indexed, then use Rn rather than ALU output, as address
932
            if ( mem_op_post_indexed )
933
               daddress_sel_nxt = 4'd4; // Rn
934
            else
935
               daddress_sel_nxt = 4'd1; // alu out
936
 
937
            if ( instruction[25] && type ==  TRANS )
938
                barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
939
 
940
            if ( type == TRANS && instruction[25] && shift_imm != 5'd0 )
941
                begin
942
                barrel_shift_function_nxt   = instruction[6:5];
943
                barrel_shift_amount_sel_nxt = 2'd2; // imm_shift_amount
944
                end
945
            end
946
 
947
 
948
        if ( type == BRANCH )
949
            begin
950 35 csantifort
            pc_sel_nxt            = 3'd1; // alu_out
951
            iaddress_sel_nxt      = 4'd1; // alu_out
952
            alu_out_sel_nxt       = 4'd1; // Add
953 16 csantifort
 
954
            if ( instruction[24] ) // Link
955
                begin
956
                reg_bank_wen_nxt  = decode (4'd14);  // Save PC to LR
957
                reg_write_sel_nxt = 3'd1;            // pc - 32'd4
958
                end
959
            end
960
 
961
 
962
        if ( type == MTRANS )
963
            begin
964
            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
965
            decode_daccess_nxt              = 1'd1; // valid data access
966
            alu_out_sel_nxt                 = 4'd1; // Add
967
            base_address_wen_nxt            = 1'd1; // Save the value of the register used for the base address,
968
                                                    // in case of a data abort, and need to restore the value                        
969
 
970
            if ( mtrans_num_registers > 4'd1 )
971
                begin
972
                iaddress_sel_nxt        = 4'd3; // pc  (not pc + 4)
973
                pc_wen_nxt              = 1'd0; // hold current PC value rather than an instruction fetch
974
                end
975
 
976
 
977
            // The spec says -
978
            // If the instruction would have overwritten the base with data 
979
            // (that is, it has the base in the transfer list), the overwriting is prevented.
980
            // This is true even when the abort occurs after the base word gets loaded
981
            restore_base_address_nxt        = instruction[20] &&
982
                                                (instruction[15:0] & (1'd1 << instruction[19:16]));
983
 
984
            // Increment
985
            if ( instruction[23] )
986
                begin
987
                if ( instruction[24] )    // increment before
988
                    daddress_sel_nxt = 4'd7; // Rn + 4
989
                else
990
                    daddress_sel_nxt = 4'd4; // Rn
991
                end
992
            else
993
            // Decrement
994
                begin
995
                alu_cin_sel_nxt  = 2'd1; // cin = 1
996
                alu_not_sel_nxt  = 1'd1; // invert B
997
                if ( !instruction[24] )    // decrement after
998
                    daddress_sel_nxt  = 4'd6; // alu out + 4
999
                else
1000
                    daddress_sel_nxt  = 4'd1; // alu out
1001
                end
1002
 
1003
            // Load or store ?
1004
            if ( !instruction[20] )  // Store
1005
                write_data_wen_nxt = 1'd1;
1006
 
1007
            // stm: store the user mode registers, when in priviledged mode     
1008 82 csantifort
            if ( {instruction[22],instruction[20]} == 2'b10 )
1009 16 csantifort
                o_user_mode_regs_store_nxt = 1'd1;
1010
 
1011
            // update the base register ?
1012
            if ( instruction[21] )  // the W bit
1013
                reg_bank_wen_nxt  = decode (rn_sel_nxt);
1014
 
1015
            // write to the pc ?
1016
            if ( instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC
1017
                begin
1018
                saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
1019
                pc_wen_nxt                      = 1'd0; // hold current PC value rather than an instruction fetch
1020
                load_pc_nxt                     = 1'd1;
1021
                end
1022
            end
1023
 
1024
 
1025
        if ( type == MULT )
1026
            begin
1027
            multiply_function_nxt[0]        = 1'd1; // set enable
1028
                                                    // some bits can be changed just below
1029
            saved_current_instruction_wen   = 1'd1; // Save the Multiply instruction to 
1030
                                                    // refer back to later
1031
            pc_wen_nxt                      = 1'd0; // hold current PC value
1032
 
1033
            if ( instruction[21] )
1034
                multiply_function_nxt[1]    = 1'd1; // accumulate
1035
            end
1036
 
1037
 
1038
        // swp - do read part first
1039
        if ( type == SWAP )
1040
            begin
1041
            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
1042
            pc_wen_nxt                      = 1'd0; // hold current PC value
1043
            decode_iaccess_nxt              = 1'd0; // skip the instruction fetch
1044
            decode_daccess_nxt              = 1'd1; // data access
1045
            barrel_shift_data_sel_nxt       = 2'd2; // Shift value from Rm register
1046
            daddress_sel_nxt                = 4'd4; // Rn
1047
            decode_exclusive_nxt            = 1'd1; // signal an exclusive access
1048
            end
1049
 
1050
 
1051
        // mcr & mrc - takes two cycles
1052
        if ( type == CORTRANS && !und_request )
1053
            begin
1054
            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
1055
            pc_wen_nxt                      = 1'd0; // hold current PC value
1056
            iaddress_sel_nxt                = 4'd3; // pc  (not pc + 4)
1057
 
1058
            if ( instruction[20] ) // MRC
1059
                copro_operation_nxt         = 2'd1;  // Register transfer from Co-Processor
1060
            else // MCR
1061
                begin
1062
                 // Don't enable operation to Co-Processor until next period
1063
                 // So it gets the Rd value from the execution stage at the same time
1064
                copro_operation_nxt      = 2'd0;
1065
                copro_write_data_wen_nxt = 1'd1;  // Rd register value to co-processor
1066
                end
1067
            end
1068
 
1069
 
1070
        if ( type == SWI || und_request )
1071
            begin
1072
            // save address of next instruction to Supervisor Mode LR
1073
            reg_write_sel_nxt               = 3'd1;            // pc -4
1074
            reg_bank_wen_nxt                = decode (4'd14);  // LR
1075
 
1076
            iaddress_sel_nxt                = 4'd2;            // interrupt_vector
1077
            pc_sel_nxt                      = 3'd2;            // interrupt_vector
1078
 
1079
            status_bits_mode_nxt            = interrupt_mode;  // e.g. Supervisor mode
1080
            status_bits_mode_wen_nxt        = 1'd1;
1081
 
1082
            // disable normal interrupts
1083
            status_bits_irq_mask_nxt        = 1'd1;
1084
            status_bits_irq_mask_wen_nxt    = 1'd1;
1085
            end
1086
 
1087
 
1088
        if ( regop_set_flags )
1089
            begin
1090
            status_bits_flags_wen_nxt = 1'd1;
1091
 
1092
            // If <Rd> is r15, the ALU output is copied to the Status Bits. 
1093
            // Not allowed to use r15 for mul or lma instructions           
1094
            if ( instruction[15:12] == 4'd15 )
1095
                begin
1096
                status_bits_sel_nxt       = 3'd1; // alu out
1097
 
1098
                // Priviledged mode? Then also update the other status bits
1099
                if ( i_execute_status_bits[1:0] != USR )
1100
                    begin
1101
                    status_bits_mode_wen_nxt      = 1'd1;
1102
                    status_bits_irq_mask_wen_nxt  = 1'd1;
1103
                    status_bits_firq_mask_wen_nxt = 1'd1;
1104
                    end
1105
                end
1106
            end
1107
 
1108
        end
1109
 
1110
    // Handle asynchronous interrupts.
1111
    // interrupts are processed only during execution states
1112
    // multicycle instructions must complete before the interrupt starts
1113
    // SWI, Address Exception and Undefined Instruction interrupts are only executed if the
1114
    // instruction that causes the interrupt is conditionally executed so
1115
    // its not handled here
1116
    if ( instruction_valid && interrupt &&  next_interrupt != 3'd6 )
1117
        begin
1118
        // Save the interrupt causing instruction to refer back to later
1119
        // This also saves the instruction abort vma and status, in the case of an
1120
        // instruction abort interrupt
1121
        saved_current_instruction_wen   = 1'd1;
1122
 
1123
        // save address of next instruction to Supervisor Mode LR
1124
        // Address Exception ?
1125
        if ( next_interrupt == 3'd4 )
1126
            reg_write_sel_nxt               = 3'd7;            // pc
1127
        else
1128
            reg_write_sel_nxt               = 3'd1;            // pc -4
1129
 
1130
        reg_bank_wen_nxt                = decode (4'd14);  // LR
1131
 
1132
        iaddress_sel_nxt                = 4'd2;            // interrupt_vector
1133
        pc_sel_nxt                      = 3'd2;            // interrupt_vector
1134
 
1135
        status_bits_mode_nxt            = interrupt_mode;  // e.g. Supervisor mode
1136
        status_bits_mode_wen_nxt        = 1'd1;
1137
 
1138
        // disable normal interrupts
1139
        status_bits_irq_mask_nxt        = 1'd1;
1140
        status_bits_irq_mask_wen_nxt    = 1'd1;
1141
 
1142
        // disable fast interrupts
1143
        if ( next_interrupt == 3'd2 ) // FIRQ
1144
            begin
1145
            status_bits_firq_mask_nxt        = 1'd1;
1146
            status_bits_firq_mask_wen_nxt    = 1'd1;
1147
            end
1148
        end
1149
 
1150
 
1151
    // previous instruction was ldr
1152
    // if it is currently executing in the execute stage do the following    
1153
    if ( control_state == MEM_WAIT1 && !conflict )
1154
        begin
1155
        // Save the next instruction to execute later
1156
        // Do this even if the ldr instruction does not execute because of Condition
1157
        pre_fetch_instruction_wen   = 1'd1;
1158
 
1159
        if ( instruction_execute ) // conditional execution state
1160
            begin
1161
            iaddress_sel_nxt            = 4'd3; // pc  (not pc + 4)
1162
            pc_wen_nxt                  = 1'd0; // hold current PC value
1163
            load_pc_nxt                 = load_pc_r;
1164
            end
1165
        end
1166
 
1167
 
1168
    // completion of ldr instruction
1169
    if ( control_state == MEM_WAIT2 )
1170
        begin
1171
        if ( !dabt )  // dont load data there is an abort on the data read
1172
            begin
1173
            pc_wen_nxt                  = 1'd0; // hold current PC value
1174
 
1175
            // Check if the load destination is the PC
1176
            if (( type == TRANS && instruction[15:12]  == 4'd15 ) ||
1177
                ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))
1178
                begin
1179
                pc_sel_nxt       = 3'd3; // read_data_filtered
1180
                iaddress_sel_nxt = 4'd3; // hold value after reading in from mem
1181
                load_pc_nxt      = load_pc_r;
1182
                end
1183
            end
1184
        end
1185
 
1186
 
1187
    // second cycle of multiple load or store
1188
    if ( control_state == MTRANS_EXEC1 && !conflict )
1189
        begin
1190
        // Save the next instruction to execute later
1191
        pre_fetch_instruction_wen   = 1'd1;
1192
 
1193
        if ( instruction_execute ) // conditional execution state
1194
            begin
1195
            daddress_sel_nxt            = 4'd5;  // o_address
1196
            decode_daccess_nxt          = 1'd1;  // data access
1197
 
1198
            if ( mtrans_num_registers > 4'd2 )
1199
                decode_iaccess_nxt      = 1'd0;  // skip the instruction fetch
1200
 
1201
 
1202
            if ( mtrans_num_registers != 4'd1 )
1203
                begin
1204
                pc_wen_nxt              = 1'd0;  // hold current PC value
1205
                iaddress_sel_nxt        = 4'd3;  // pc  (not pc + 4)
1206
                end
1207
 
1208
 
1209
            if ( !instruction[20] ) // Store
1210
                write_data_wen_nxt = 1'd1;
1211
 
1212
            // stm: store the user mode registers, when in priviledged mode     
1213 82 csantifort
            if ( {instruction[22],instruction[20]} == 2'b10 )
1214 16 csantifort
                o_user_mode_regs_store_nxt = 1'd1;
1215
 
1216
            // write to the pc ?
1217
            if ( instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC
1218
                begin
1219
                saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
1220
                pc_wen_nxt                      = 1'd0; // hold current PC value rather than an instruction fetch
1221
                load_pc_nxt                     = 1'd1;
1222
                end
1223
            end
1224
        end
1225
 
1226
 
1227
    // third cycle of multiple load or store
1228
    if ( control_state == MTRANS_EXEC2 )
1229
        begin
1230
        daddress_sel_nxt            = 4'd5;  // o_address
1231
        decode_daccess_nxt          = 1'd1;  // data access
1232
 
1233
        if ( mtrans_num_registers > 4'd2 )
1234
            begin
1235
            decode_iaccess_nxt      = 1'd0;  // skip the instruction fetch
1236
            end
1237
 
1238
        if ( mtrans_num_registers > 4'd1 )
1239
            begin
1240
            pc_wen_nxt              = 1'd0; // hold current PC value
1241
            iaddress_sel_nxt        = 4'd3;  // pc  (not pc + 4)
1242
            end
1243
 
1244
        // Store
1245
        if ( !instruction[20] )
1246
            write_data_wen_nxt = 1'd1;
1247
 
1248
        // stm: store the user mode registers, when in priviledged mode     
1249 82 csantifort
        if ( {instruction[22],instruction[20]} == 2'b10 )
1250 16 csantifort
            o_user_mode_regs_store_nxt = 1'd1;
1251
 
1252
        // write to the pc ?
1253
        if ( instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC
1254
            begin
1255
            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
1256
            pc_wen_nxt                      = 1'd0; // hold current PC value rather than an instruction fetch
1257
            load_pc_nxt                     = 1'd1;
1258
            end
1259
        end
1260
 
1261
 
1262
    // state is for when a data abort interrupt is triggered during an ldm
1263
    if ( control_state == MTRANS_ABORT )
1264
        begin
1265
        // Restore the Base Address, if the base register is included in the
1266
        // list of registers being loaded
1267
        if (restore_base_address) // ldm with base address in register list
1268
            begin
1269
            reg_write_sel_nxt = 3'd6;                        // write base_register
1270
            reg_bank_wen_nxt  = decode ( instruction[19:16] ); // to Rn
1271
            end
1272
        end
1273
 
1274
 
1275
        // Multiply or Multiply-Accumulate
1276
    if ( control_state == MULT_PROC1 && instruction_execute && !conflict )
1277
        begin
1278
        // Save the next instruction to execute later
1279
        // Do this even if this instruction does not execute because of Condition
1280
        pre_fetch_instruction_wen   = 1'd1;
1281
        pc_wen_nxt                  = 1'd0;  // hold current PC value
1282
        multiply_function_nxt       = o_multiply_function;
1283
        end
1284
 
1285
 
1286
        // Multiply or Multiply-Accumulate
1287
        // Do multiplication
1288
        // Wait for done or accumulate signal
1289
    if ( control_state == MULT_PROC2 )
1290
        begin
1291
        // Save the next instruction to execute later
1292
        // Do this even if this instruction does not execute because of Condition
1293
        pc_wen_nxt              = 1'd0;  // hold current PC value
1294
        iaddress_sel_nxt        = 4'd3;  // pc  (not pc + 4)
1295
        multiply_function_nxt   = o_multiply_function;
1296
        end
1297
 
1298
 
1299
    // Save RdLo
1300
    // always last cycle of all multiply or multiply accumulate operations
1301
    if ( control_state == MULT_STORE )
1302
        begin
1303
        reg_write_sel_nxt     = 3'd2; // multiply_out
1304
        multiply_function_nxt = o_multiply_function;
1305
 
1306
        if ( type == MULT ) // 32-bit
1307
            reg_bank_wen_nxt      = decode (instruction[19:16]); // Rd
1308
        else  // 64-bit / Long
1309
            reg_bank_wen_nxt      = decode (instruction[15:12]); // RdLo
1310
 
1311
        if ( instruction[20] )  // the 'S' bit
1312
            begin
1313
            status_bits_sel_nxt       = 3'd4; // { multiply_flags, status_bits_flags[1:0] } 
1314
            status_bits_flags_wen_nxt = 1'd1;
1315
            end
1316
        end
1317
 
1318
 
1319
    // Add lower 32 bits to multiplication product
1320
    if ( control_state == MULT_ACCUMU )
1321
        begin
1322
        multiply_function_nxt = o_multiply_function;
1323
        pc_wen_nxt            = 1'd0;  // hold current PC value
1324
        iaddress_sel_nxt      = 4'd3;  // pc  (not pc + 4)
1325
        end
1326
 
1327
 
1328
    // swp - do write request in 2nd cycle
1329
    if ( control_state == SWAP_WRITE && instruction_execute && !conflict )
1330
        begin
1331
        barrel_shift_data_sel_nxt       = 2'd2; // Shift value from Rm register
1332
        daddress_sel_nxt                = 4'd4; // Rn
1333
        write_data_wen_nxt              = 1'd1;
1334
        decode_iaccess_nxt              = 1'd0; // skip the instruction fetch
1335
        decode_daccess_nxt              = 1'd1; // data access
1336
 
1337
        if ( instruction[22] )
1338
            byte_enable_sel_nxt = 2'd1;         // Save byte
1339
 
1340
        if ( instruction_execute )              // conditional execution state
1341
            pc_wen_nxt                  = 1'd0; // hold current PC value
1342
 
1343
        // Save the next instruction to execute later
1344
        // Do this even if this instruction does not execute because of Condition
1345
        pre_fetch_instruction_wen       = 1'd1;
1346
 
1347
        load_pc_nxt                     = load_pc_r;
1348
        end
1349
 
1350
 
1351
    // swp - receive read response in 3rd cycle
1352
    if ( control_state == SWAP_WAIT1 )
1353
        begin
1354
 
1355
        if ( instruction_execute ) // conditional execution state
1356
            begin
1357
            iaddress_sel_nxt            = 4'd3; // pc  (not pc + 4)
1358
            pc_wen_nxt                  = 1'd0; // hold current PC value
1359
            end
1360
 
1361
        if ( !dabt )
1362
            begin
1363
            // Check is the load destination is the PC
1364
            if ( instruction[15:12]  == 4'd15 )
1365
                begin
1366
                pc_sel_nxt       = 3'd3; // read_data_filtered
1367
                iaddress_sel_nxt = 4'd3; // hold value after reading in from mem
1368
                load_pc_nxt      = load_pc_r;
1369
                end
1370
            end
1371
        end
1372
 
1373
 
1374
    // 1 cycle delay for Co-Processor Register access
1375
    if ( control_state == COPRO_WAIT && instruction_execute && !conflict )
1376
        begin
1377
        pre_fetch_instruction_wen = 1'd1;
1378
 
1379
        if ( instruction[20] ) // mrc instruction
1380
            begin
1381
            // Check is the load destination is the PC
1382
            if ( instruction[15:12]  == 4'd15 )
1383
                begin
1384
                // If r15 is specified for <Rd>, the condition code flags are 
1385
                // updated instead of a general-purpose register.
1386
                status_bits_sel_nxt           = 3'd3;  // i_copro_data
1387
                status_bits_flags_wen_nxt     = 1'd1;
1388
 
1389
                // Can't change these in USR mode
1390
                if ( i_execute_status_bits[1:0] != USR )
1391
                   begin
1392
                   status_bits_mode_wen_nxt      = 1'd1;
1393
                   status_bits_irq_mask_wen_nxt  = 1'd1;
1394
                   status_bits_firq_mask_wen_nxt = 1'd1;
1395
                   end
1396
                end
1397
            else
1398
                reg_bank_wen_nxt = decode (instruction[15:12]);
1399
 
1400
            reg_write_sel_nxt = 3'd5;     // i_copro_data
1401
            end
1402
        else // mcr instruction
1403
            begin
1404
            copro_operation_nxt      = 2'd2;  // Register transfer to Co-Processor 
1405
            end
1406
        end
1407
 
1408
 
1409
    // Have just changed the status_bits mode but this
1410
    // creates a 1 cycle gap with the old mode
1411
    // coming back from execute into instruction_decode
1412
    // So squash that old mode value during this
1413
    // cycle of the interrupt transition    
1414
    if ( control_state == INT_WAIT1 )
1415
        status_bits_mode_nxt            = o_status_bits_mode;   // Supervisor mode
1416
 
1417
    end
1418
 
1419
 
1420
// Speed up the long path from u_decode/fetch_instruction_r to u_register_bank/r8_firq
1421
// This pre-encodes the firq_s3 signal thats used in u_register_bank
1422
assign firq_not_user_mode_nxt = status_bits_mode_nxt == FIRQ;
1423
 
1424
 
1425
// ========================================================
1426
// Next State Logic
1427
// ========================================================
1428
 
1429
// this replicates the current value of the execute signal in the execute stage
1430
assign instruction_execute = conditional_execute ( o_condition, i_execute_status_bits[31:28] );
1431
 
1432
 
1433
// First state of executing a new instruction
1434
// Its complex because of conditional execution of multi-cycle instructions
1435
assign instruction_valid = ((control_state == EXECUTE || control_state == PRE_FETCH_EXEC) ||
1436
                              // when last instruction was multi-cycle instruction but did not execute
1437
                              // because condition was false then act like you're in the execute state
1438
                             (!instruction_execute && (control_state == PC_STALL1    ||
1439
                                                       control_state == MEM_WAIT1    ||
1440
                                                       control_state == COPRO_WAIT   ||
1441
                                                       control_state == SWAP_WRITE   ||
1442
                                                       control_state == MULT_PROC1   ||
1443
                                                       control_state == MTRANS_EXEC1  ) ));
1444
 
1445
 
1446
 always @*
1447
    begin
1448
    // default is to hold the current state
1449
    control_state_nxt = control_state;
1450
 
1451
    // Note: The order is important here
1452
    if ( control_state == RST_WAIT1 )     control_state_nxt = RST_WAIT2;
1453
    if ( control_state == RST_WAIT2 )     control_state_nxt = EXECUTE;
1454
    if ( control_state == INT_WAIT1 )     control_state_nxt = INT_WAIT2;
1455
    if ( control_state == INT_WAIT2 )     control_state_nxt = EXECUTE;
1456
    if ( control_state == COPRO_WAIT )    control_state_nxt = PRE_FETCH_EXEC;
1457
    if ( control_state == PC_STALL1 )     control_state_nxt = PC_STALL2;
1458
    if ( control_state == PC_STALL2 )     control_state_nxt = EXECUTE;
1459
    if ( control_state == SWAP_WRITE )    control_state_nxt = SWAP_WAIT1;
1460
    if ( control_state == SWAP_WAIT1 )    control_state_nxt = SWAP_WAIT2;
1461
    if ( control_state == MULT_STORE )    control_state_nxt = PRE_FETCH_EXEC;
1462
    if ( control_state == MTRANS_ABORT )  control_state_nxt = PRE_FETCH_EXEC;
1463
 
1464
    if ( control_state == MEM_WAIT1 )
1465
        control_state_nxt = MEM_WAIT2;
1466
 
1467
    if ( control_state == MEM_WAIT2   ||
1468
        control_state == SWAP_WAIT2    )
1469
        begin
1470
        if ( write_pc ) // writing to the PC!! 
1471
            control_state_nxt = PC_STALL1;
1472
        else
1473
            control_state_nxt = PRE_FETCH_EXEC;
1474
        end
1475
 
1476
    if ( control_state == MTRANS_EXEC1 )
1477
        begin
1478
        if ( mtrans_instruction_nxt[15:0] != 16'd0 )
1479
            control_state_nxt = MTRANS_EXEC2;
1480
        else   // if the register list holds a single register 
1481
            begin
1482
            if ( dabt ) // data abort
1483
                control_state_nxt = MTRANS_ABORT;
1484
            else if ( write_pc ) // writing to the PC!! 
1485
                control_state_nxt = MEM_WAIT1;
1486
            else
1487
                control_state_nxt = PRE_FETCH_EXEC;
1488
            end
1489
        end
1490
 
1491
        // Stay in State MTRANS_EXEC2 until the full list of registers to
1492
        // load or store has been processed
1493
    if ( control_state == MTRANS_EXEC2 && mtrans_num_registers == 5'd1 )
1494
        begin
1495
        if ( dabt ) // data abort
1496
            control_state_nxt = MTRANS_ABORT;
1497
        else if ( write_pc ) // writing to the PC!! 
1498
            control_state_nxt = MEM_WAIT1;
1499
        else
1500
            control_state_nxt = PRE_FETCH_EXEC;
1501
        end
1502
 
1503
 
1504
    if ( control_state == MULT_PROC1 )
1505
        begin
1506
        if (!instruction_execute)
1507
            control_state_nxt = PRE_FETCH_EXEC;
1508
        else
1509
            control_state_nxt = MULT_PROC2;
1510
        end
1511
 
1512
    if ( control_state == MULT_PROC2 )
1513
        begin
1514
        if ( i_multiply_done )
1515
            if      ( o_multiply_function[1] )  // Accumulate ?
1516
                control_state_nxt = MULT_ACCUMU;
1517
            else
1518
                control_state_nxt = MULT_STORE;
1519
        end
1520
 
1521
 
1522
    if ( control_state == MULT_ACCUMU )
1523
        begin
1524
        control_state_nxt = MULT_STORE;
1525
        end
1526
 
1527
 
1528
    // This should come at the end, so that conditional execution works
1529
    // correctly
1530
    if ( instruction_valid )
1531
        begin
1532
        // default is to stay in execute state, or to move into this
1533
        // state from a conditional execute state
1534
        control_state_nxt = EXECUTE;
1535
 
1536
        if ( current_write_pc )
1537
             control_state_nxt = PC_STALL1;
1538
 
1539
        if ( load_op && instruction[15:12]  == 4'd15 )  // load new PC value
1540
             control_state_nxt = MEM_WAIT1;
1541
 
1542
        // ldm rx, {pc}
1543
        if ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC
1544
             control_state_nxt = MEM_WAIT1;
1545
 
1546
        if ( type == MTRANS && !conflict && mtrans_num_registers != 5'd0 && mtrans_num_registers != 5'd1 )
1547
            control_state_nxt = MTRANS_EXEC1;
1548
 
1549
        if ( type == MULT && !conflict )
1550
                control_state_nxt = MULT_PROC1;
1551
 
1552
        if ( type == SWAP && !conflict )
1553
                control_state_nxt = SWAP_WRITE;
1554
 
1555
        if ( type == CORTRANS && !und_request && !conflict )
1556
                control_state_nxt = COPRO_WAIT;
1557
 
1558
         // interrupt overrides everything else so its last       
1559
        if ( interrupt && !conflict )
1560
                control_state_nxt = INT_WAIT1;
1561
        end
1562
 
1563
    end
1564
 
1565
 
1566
// ========================================================
1567
// Register Update
1568
// ========================================================
1569
always @ ( posedge i_clk )
1570 35 csantifort
    if ( !i_core_stall )
1571 16 csantifort
        begin
1572
        if (!conflict)
1573
            begin
1574
            fetch_instruction_r         <= i_fetch_instruction;
1575 35 csantifort
            fetch_instruction_type_r    <= instruction_type(i_fetch_instruction);
1576 16 csantifort
            fetch_address_r             <= i_execute_iaddress;
1577
            iabt_reg                    <= i_iabt;
1578
            adex_reg                    <= i_adex;
1579
            abt_status_reg              <= i_abt_status;
1580
            end
1581
 
1582
        o_status_bits_mode          <= status_bits_mode_nxt;
1583
        o_status_bits_irq_mask      <= status_bits_irq_mask_nxt;
1584
        o_status_bits_firq_mask     <= status_bits_firq_mask_nxt;
1585
        o_imm32                     <= imm32_nxt;
1586
        o_imm_shift_amount          <= imm_shift_amount_nxt;
1587
        o_shift_imm_zero            <= shift_imm_zero_nxt;
1588
 
1589
                                        // when have an interrupt, execute the interrupt operation
1590
                                        // unconditionally in the execute stage
1591
                                        // ensures that status_bits register gets updated correctly
1592
                                        // Likewise when in middle of multi-cycle instructions
1593
                                        // execute them unconditionally
1594
        o_condition                 <= instruction_valid && !interrupt ? condition_nxt : AL;
1595
        o_decode_exclusive          <= decode_exclusive_nxt;
1596
        o_decode_iaccess            <= decode_iaccess_nxt;
1597
        o_decode_daccess            <= decode_daccess_nxt;
1598
 
1599
        o_rm_sel                    <= rm_sel_nxt;
1600
        o_rs_sel                    <= rs_sel_nxt;
1601
        o_load_rd                   <= load_rd_nxt;
1602
        load_rd_d1                  <= load_rd_d1_nxt;
1603
        load_pc_r                   <= load_pc_nxt;
1604
        o_rn_sel                    <= rn_sel_nxt;
1605
        o_barrel_shift_amount_sel   <= barrel_shift_amount_sel_nxt;
1606
        o_barrel_shift_data_sel     <= barrel_shift_data_sel_nxt;
1607
        o_barrel_shift_function     <= barrel_shift_function_nxt;
1608
        o_alu_function              <= alu_function_nxt;
1609
        o_multiply_function         <= multiply_function_nxt;
1610
        o_interrupt_vector_sel      <= next_interrupt;
1611
        o_iaddress_sel              <= iaddress_sel_nxt;
1612
        o_daddress_sel              <= daddress_sel_nxt;
1613
        o_pc_sel                    <= pc_sel_nxt;
1614
        o_byte_enable_sel           <= byte_enable_sel_nxt;
1615
        o_status_bits_sel           <= status_bits_sel_nxt;
1616
        o_reg_write_sel             <= reg_write_sel_nxt;
1617
        o_firq_not_user_mode        <= firq_not_user_mode_nxt;
1618
        o_write_data_wen            <= write_data_wen_nxt;
1619
        o_base_address_wen          <= base_address_wen_nxt;
1620
        o_pc_wen                    <= pc_wen_nxt;
1621
        o_reg_bank_wen              <= reg_bank_wen_nxt;
1622
        o_status_bits_flags_wen     <= status_bits_flags_wen_nxt;
1623
        o_status_bits_mode_wen      <= status_bits_mode_wen_nxt;
1624
        o_status_bits_irq_mask_wen  <= status_bits_irq_mask_wen_nxt;
1625
        o_status_bits_firq_mask_wen <= status_bits_firq_mask_wen_nxt;
1626
 
1627
        o_copro_opcode1             <= instruction[23:21];
1628
        o_copro_opcode2             <= instruction[7:5];
1629
        o_copro_crn                 <= instruction[19:16];
1630
        o_copro_crm                 <= instruction[3:0];
1631
        o_copro_num                 <= instruction[11:8];
1632
        o_copro_operation           <= copro_operation_nxt;
1633
        o_copro_write_data_wen      <= copro_write_data_wen_nxt;
1634
        restore_base_address        <= restore_base_address_nxt;
1635
        control_state               <= control_state_nxt;
1636
        end
1637
 
1638
 
1639
 
1640
always @ ( posedge i_clk )
1641 35 csantifort
    if ( !i_core_stall )
1642 16 csantifort
        begin
1643
        // sometimes this is a pre-fetch instruction
1644
        // e.g. two ldr instructions in a row. The second ldr will be saved
1645
        // to the pre-fetch instruction register
1646
        // then when its decoded, a copy is saved to the saved_current_instruction
1647
        // register
1648
        if      ( type == MTRANS )
1649
            begin
1650
            saved_current_instruction              <= mtrans_instruction_nxt;
1651 35 csantifort
            saved_current_instruction_type         <= type;
1652 16 csantifort
            saved_current_instruction_iabt         <= instruction_iabt;
1653
            saved_current_instruction_adex         <= instruction_adex;
1654
            saved_current_instruction_address      <= instruction_address;
1655
            saved_current_instruction_iabt_status  <= instruction_iabt_status;
1656
            end
1657
        else if ( saved_current_instruction_wen )
1658
            begin
1659
            saved_current_instruction              <= instruction;
1660 35 csantifort
            saved_current_instruction_type         <= type;
1661 16 csantifort
            saved_current_instruction_iabt         <= instruction_iabt;
1662
            saved_current_instruction_adex         <= instruction_adex;
1663
            saved_current_instruction_address      <= instruction_address;
1664
            saved_current_instruction_iabt_status  <= instruction_iabt_status;
1665
            end
1666
 
1667
        if      ( pre_fetch_instruction_wen )
1668
            begin
1669
            pre_fetch_instruction                  <= fetch_instruction_r;
1670 35 csantifort
            pre_fetch_instruction_type             <= fetch_instruction_type_r;
1671 16 csantifort
            pre_fetch_instruction_iabt             <= iabt_reg;
1672
            pre_fetch_instruction_adex             <= adex_reg;
1673
            pre_fetch_instruction_address          <= fetch_address_r;
1674
            pre_fetch_instruction_iabt_status      <= abt_status_reg;
1675
            end
1676 35 csantifort
 
1677
 
1678
        // TODO possible to use saved_current_instruction instead and save some regs?          
1679 16 csantifort
        hold_instruction              <= instruction;
1680 35 csantifort
        hold_instruction_type         <= type;
1681 16 csantifort
        hold_instruction_iabt         <= instruction_iabt;
1682
        hold_instruction_adex         <= instruction_adex;
1683
        hold_instruction_address      <= instruction_address;
1684
        hold_instruction_iabt_status  <= instruction_iabt_status;
1685
        end
1686
 
1687
 
1688
 
1689
always @ ( posedge i_clk )
1690 35 csantifort
    if ( !i_core_stall )
1691 16 csantifort
        begin
1692
        irq   <= i_irq;
1693
        firq  <= i_firq;
1694
 
1695
        if ( control_state == INT_WAIT1 && o_status_bits_mode == SVC )
1696
            begin
1697
            dabt_reg  <= 1'd0;
1698
            end
1699
        else
1700
            begin
1701
            dabt_reg  <= dabt_reg || i_dabt;
1702
            end
1703
 
1704
        dabt_reg_d1  <= dabt_reg;
1705
        end
1706
 
1707
assign dabt = dabt_reg || i_dabt;
1708
 
1709
 
1710
// ========================================================
1711
// Decompiler for debugging core - not synthesizable
1712
// ========================================================
1713
//synopsys translate_off
1714
 
1715 82 csantifort
`include "debug_functions.vh"
1716 16 csantifort
 
1717
a25_decompile  u_decompile (
1718
    .i_clk                      ( i_clk                            ),
1719 35 csantifort
    .i_core_stall               ( i_core_stall                     ),
1720 16 csantifort
    .i_instruction              ( instruction                      ),
1721
    .i_instruction_valid        ( instruction_valid &&!conflict    ),
1722
    .i_instruction_execute      ( instruction_execute              ),
1723
    .i_instruction_address      ( instruction_address              ),
1724
    .i_interrupt                ( {3{interrupt}} & next_interrupt  ),
1725
    .i_interrupt_state          ( control_state == INT_WAIT2       ),
1726
    .i_instruction_undefined    ( und_request                      ),
1727
    .i_pc_sel                   ( o_pc_sel                         ),
1728
    .i_pc_wen                   ( o_pc_wen                         )
1729
);
1730
 
1731
 
1732
wire    [(15*8)-1:0]    xCONTROL_STATE;
1733
wire    [(15*8)-1:0]    xMODE;
1734
wire    [( 8*8)-1:0]    xTYPE;
1735
 
1736
assign xCONTROL_STATE        =
1737
                               control_state == RST_WAIT1      ? "RST_WAIT1"      :
1738
                               control_state == RST_WAIT2      ? "RST_WAIT2"      :
1739
 
1740
 
1741
                               control_state == INT_WAIT1      ? "INT_WAIT1"      :
1742
                               control_state == INT_WAIT2      ? "INT_WAIT2"      :
1743
                               control_state == EXECUTE        ? "EXECUTE"        :
1744
                               control_state == PRE_FETCH_EXEC ? "PRE_FETCH_EXEC" :
1745
                               control_state == MEM_WAIT1      ? "MEM_WAIT1"      :
1746
                               control_state == MEM_WAIT2      ? "MEM_WAIT2"      :
1747
                               control_state == PC_STALL1      ? "PC_STALL1"      :
1748
                               control_state == PC_STALL2      ? "PC_STALL2"      :
1749
                               control_state == MTRANS_EXEC1   ? "MTRANS_EXEC1"   :
1750
                               control_state == MTRANS_EXEC2   ? "MTRANS_EXEC2"   :
1751
                               control_state == MTRANS_ABORT   ? "MTRANS_ABORT"   :
1752
                               control_state == MULT_PROC1     ? "MULT_PROC1"     :
1753
                               control_state == MULT_PROC2     ? "MULT_PROC2"     :
1754
                               control_state == MULT_STORE     ? "MULT_STORE"     :
1755
                               control_state == MULT_ACCUMU    ? "MULT_ACCUMU"    :
1756
                               control_state == SWAP_WRITE     ? "SWAP_WRITE"     :
1757
                               control_state == SWAP_WAIT1     ? "SWAP_WAIT1"     :
1758
                               control_state == SWAP_WAIT2     ? "SWAP_WAIT2"     :
1759
                               control_state == COPRO_WAIT     ? "COPRO_WAIT"     :
1760
                                                                 "UNKNOWN "       ;
1761
 
1762
assign xMODE  = mode_name ( o_status_bits_mode );
1763
 
1764
assign xTYPE  =
1765
                               type == REGOP    ? "REGOP"    :
1766
                               type == MULT     ? "MULT"     :
1767
                               type == SWAP     ? "SWAP"     :
1768
                               type == TRANS    ? "TRANS"    :
1769
                               type == MTRANS   ? "MTRANS"   :
1770
                               type == BRANCH   ? "BRANCH"   :
1771
                               type == CODTRANS ? "CODTRANS" :
1772
                               type == COREGOP  ? "COREGOP"  :
1773
                               type == CORTRANS ? "CORTRANS" :
1774
                               type == SWI      ? "SWI"      :
1775
                                                  "UNKNOWN"  ;
1776
 
1777
 
1778
always @( posedge i_clk )
1779
    if (control_state == EXECUTE && ((instruction[0] === 1'bx) || (instruction[31] === 1'bx)))
1780
        begin
1781
        `TB_ERROR_MESSAGE
1782
        $display("Instruction with x's =%08h", instruction);
1783
        end
1784
//synopsys translate_on
1785
 
1786
endmodule
1787
 
1788
 

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