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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_execute.v] - Blame information for rev 53

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1 16 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Execute stage of Amber 25 Core                              //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Executes instructions. Instantiates the register file, ALU  //
10
//  multiplication unit and barrel shifter. This stage is       //
11
//  relitively simple. All the complex stuff is done in the     //
12
//  decode stage.                                               //
13
//                                                              //
14
//  Author(s):                                                  //
15
//      - Conor Santifort, csantifort.amber@gmail.com           //
16
//                                                              //
17
//////////////////////////////////////////////////////////////////
18
//                                                              //
19
// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
20
//                                                              //
21
// This source file may be used and distributed without         //
22
// restriction provided that this copyright statement is not    //
23
// removed from the file and that any derivative work contains  //
24
// the original copyright notice and the associated disclaimer. //
25
//                                                              //
26
// This source file is free software; you can redistribute it   //
27
// and/or modify it under the terms of the GNU Lesser General   //
28
// Public License as published by the Free Software Foundation; //
29
// either version 2.1 of the License, or (at your option) any   //
30
// later version.                                               //
31
//                                                              //
32
// This source is distributed in the hope that it will be       //
33
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
34
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
35
// PURPOSE.  See the GNU Lesser General Public License for more //
36
// details.                                                     //
37
//                                                              //
38
// You should have received a copy of the GNU Lesser General    //
39
// Public License along with this source; if not, download it   //
40
// from http://www.opencores.org/lgpl.shtml                     //
41
//                                                              //
42
//////////////////////////////////////////////////////////////////
43
 
44
 
45
module a25_execute (
46
 
47
input                       i_clk,
48 35 csantifort
input                       i_core_stall,               // stall all stages of the Amber core at the same time
49 16 csantifort
input                       i_mem_stall,                // data memory access stalls
50 35 csantifort
output                      o_exec_stall,               // stall the core pipeline
51 16 csantifort
 
52
input       [31:0]          i_wb_read_data,             // data reads
53
input                       i_wb_read_data_valid,       // read data is valid
54 35 csantifort
input       [10:0]          i_wb_load_rd,               // Rd for data reads
55 16 csantifort
 
56
input       [31:0]          i_copro_read_data,          // From Co-Processor, to either Register 
57
                                                        // or Memory
58
input                       i_decode_iaccess,           // Indicates an instruction access
59
input                       i_decode_daccess,           // Indicates a data access
60
input       [7:0]           i_decode_load_rd,           // The destination register for a load instruction
61
 
62
output reg  [31:0]          o_copro_write_data = 'd0,
63
output reg  [31:0]          o_write_data = 'd0,
64
output reg  [31:0]          o_iaddress = 32'hdead_dead,
65
output      [31:0]          o_iaddress_nxt,             // un-registered version of address to the 
66
                                                        // cache rams address ports
67
output reg                  o_iaddress_valid = 'd0,     // High when instruction address is valid
68
output reg  [31:0]          o_daddress = 32'h0,         // Address to data cache
69
output      [31:0]          o_daddress_nxt,             // un-registered version of address to the 
70
                                                        // cache rams address ports
71
output reg                  o_daddress_valid = 'd0,     // High when data address is valid
72
output reg                  o_adex = 'd0,               // Address Exception
73
output reg                  o_priviledged = 'd0,        // Priviledged access
74
output reg                  o_exclusive = 'd0,          // swap access
75
output reg                  o_write_enable = 'd0,
76
output reg  [3:0]           o_byte_enable = 'd0,
77 35 csantifort
output reg  [8:0]           o_exec_load_rd = 'd0,       // The destination register for a load instruction
78 16 csantifort
output      [31:0]          o_status_bits,              // Full PC will all status bits, but PC part zero'ed out
79
output                      o_multiply_done,
80
 
81
 
82
// --------------------------------------------------
83
// Control signals from Instruction Decode stage
84
// --------------------------------------------------
85
input      [1:0]            i_status_bits_mode,
86
input                       i_status_bits_irq_mask,
87
input                       i_status_bits_firq_mask,
88
input      [31:0]           i_imm32,
89
input      [4:0]            i_imm_shift_amount,
90
input                       i_shift_imm_zero,
91
input      [3:0]            i_condition,
92
input                       i_decode_exclusive,       // swap access
93
 
94
input      [3:0]            i_rm_sel,
95
input      [3:0]            i_rs_sel,
96
input      [3:0]            i_rn_sel,
97
input      [1:0]            i_barrel_shift_amount_sel,
98
input      [1:0]            i_barrel_shift_data_sel,
99
input      [1:0]            i_barrel_shift_function,
100
input      [8:0]            i_alu_function,
101
input      [1:0]            i_multiply_function,
102
input      [2:0]            i_interrupt_vector_sel,
103
input      [3:0]            i_iaddress_sel,
104
input      [3:0]            i_daddress_sel,
105
input      [2:0]            i_pc_sel,
106
input      [1:0]            i_byte_enable_sel,
107
input      [2:0]            i_status_bits_sel,
108
input      [2:0]            i_reg_write_sel,
109
// input                       i_user_mode_regs_load,
110
input                       i_user_mode_regs_store_nxt,
111
input                       i_firq_not_user_mode,
112
 
113
input                       i_write_data_wen,
114
input                       i_base_address_wen,     // save LDM base address register, 
115
                                                    // in case of data abort
116
input                       i_pc_wen,
117
input      [14:0]           i_reg_bank_wen,
118
input                       i_status_bits_flags_wen,
119
input                       i_status_bits_mode_wen,
120
input                       i_status_bits_irq_mask_wen,
121
input                       i_status_bits_firq_mask_wen,
122
input                       i_copro_write_data_wen,
123 20 csantifort
input                       i_conflict,
124
input                       i_rn_use_read,
125
input                       i_rm_use_read,
126
input                       i_rs_use_read,
127
input                       i_rd_use_read
128 16 csantifort
);
129
 
130
`include "a25_localparams.v"
131
`include "a25_functions.v"
132
 
133
// ========================================================
134
// Internal signals
135
// ========================================================
136
wire [31:0]         write_data_nxt;
137
wire [3:0]          byte_enable_nxt;
138
wire [31:0]         pc_plus4;
139
wire [31:0]         pc_minus4;
140
wire [31:0]         daddress_plus4;
141
wire [31:0]         alu_plus4;
142
wire [31:0]         rn_plus4;
143
wire [31:0]         alu_out;
144
wire [3:0]          alu_flags;
145
wire [31:0]         rm;
146
wire [31:0]         rs;
147
wire [31:0]         rd;
148
wire [31:0]         rn;
149 20 csantifort
wire [31:0]         reg_bank_rn;
150
wire [31:0]         reg_bank_rm;
151
wire [31:0]         reg_bank_rs;
152
wire [31:0]         reg_bank_rd;
153 16 csantifort
wire [31:0]         pc;
154
wire [31:0]         pc_nxt;
155
wire [31:0]         interrupt_vector;
156
wire [7:0]          shift_amount;
157
wire [31:0]         barrel_shift_in;
158
wire [31:0]         barrel_shift_out;
159
wire                barrel_shift_carry;
160 35 csantifort
wire                barrel_shift_stall;
161 16 csantifort
 
162
wire [3:0]          status_bits_flags_nxt;
163
reg  [3:0]          status_bits_flags = 'd0;
164
wire [1:0]          status_bits_mode_nxt;
165
reg  [1:0]          status_bits_mode = SVC;
166
                    // one-hot encoded rs select
167
wire [3:0]          status_bits_mode_rds_oh_nxt;
168
reg  [3:0]          status_bits_mode_rds_oh = 1'd1 << OH_SVC;
169
wire                status_bits_mode_rds_oh_update;
170
wire                status_bits_irq_mask_nxt;
171
reg                 status_bits_irq_mask = 1'd1;
172
wire                status_bits_firq_mask_nxt;
173
reg                 status_bits_firq_mask = 1'd1;
174 35 csantifort
wire [8:0]          exec_load_rd_nxt;
175 16 csantifort
 
176
wire                execute;                    // high when condition execution is true
177
wire [31:0]         reg_write_nxt;
178
wire                pc_wen;
179
wire [14:0]         reg_bank_wen;
180
wire [31:0]         multiply_out;
181
wire [1:0]          multiply_flags;
182
reg  [31:0]         base_address = 'd0;             // Saves base address during LDM instruction in 
183
                                                    // case of data abort
184
wire [31:0]         read_data_filtered1;
185
wire [31:0]         read_data_filtered;
186 20 csantifort
wire [31:0]         read_data_filtered_c;
187
reg  [31:0]         read_data_filtered_r = 'd0;
188
reg  [3:0]          load_rd_r = 'd0;
189
wire [3:0]          load_rd_c;
190 16 csantifort
 
191
wire                write_enable_nxt;
192
wire                daddress_valid_nxt;
193
wire                iaddress_valid_nxt;
194
wire                priviledged_nxt;
195
wire                priviledged_update;
196
wire                iaddress_update;
197
wire                daddress_update;
198
wire                base_address_update;
199
wire                write_data_update;
200
wire                copro_write_data_update;
201
wire                byte_enable_update;
202
wire                exec_load_rd_update;
203
wire                write_enable_update;
204
wire                exclusive_update;
205
wire                status_bits_flags_update;
206
wire                status_bits_mode_update;
207
wire                status_bits_irq_mask_update;
208
wire                status_bits_firq_mask_update;
209
 
210
wire [31:0]         alu_out_pc_filtered;
211
wire                adex_nxt;
212
wire [31:0]         save_int_pc;
213
wire [31:0]         save_int_pc_m4;
214
wire                ldm_flags;
215
wire                ldm_status_bits;
216
 
217
// ========================================================
218
// Status Bits in PC register
219
// ========================================================
220
assign o_status_bits = {   status_bits_flags,           // 31:28
221
                           status_bits_irq_mask,        // 7
222
                           status_bits_firq_mask,       // 6
223
                           24'd0,
224
                           status_bits_mode };          // 1:0 = mode
225
 
226
 
227
// ========================================================
228
// Status Bits Select
229
// ========================================================
230 35 csantifort
assign ldm_flags                 = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[8];
231
assign ldm_status_bits           = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[7];
232 16 csantifort
 
233
 
234
assign status_bits_flags_nxt     = ldm_flags                 ? read_data_filtered[31:28]           :
235
                                   i_status_bits_sel == 3'd0 ? alu_flags                           :
236
                                   i_status_bits_sel == 3'd1 ? alu_out          [31:28]            :
237
                                   i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28]            :
238
                                   // 4 = update flags after a multiply operation
239
                                                        { multiply_flags, status_bits_flags[1:0] } ;
240
 
241
assign status_bits_mode_nxt      = ldm_status_bits           ? read_data_filtered [1:0] :
242
                                   i_status_bits_sel == 3'd0 ? i_status_bits_mode       :
243
                                   i_status_bits_sel == 3'd1 ? alu_out            [1:0] :
244
                                                               i_copro_read_data  [1:0] ;
245
 
246
 
247
// Used for the Rds output of register_bank - this special version of
248
// status_bits_mode speeds up the critical path from status_bits_mode through the
249
// register_bank, barrel_shifter and alu. It moves a mux needed for the
250
// i_user_mode_regs_store_nxt signal back into the previous stage -
251
// so its really part of the decode stage even though the logic is right here
252
// In addition the signal is one-hot encoded to further speed up the logic
253
 
254
assign status_bits_mode_rds_oh_nxt    = i_user_mode_regs_store_nxt ? 1'd1 << OH_USR                            :
255
                                        status_bits_mode_update    ? oh_status_bits_mode(status_bits_mode_nxt) :
256
                                                                     oh_status_bits_mode(status_bits_mode)     ;
257
 
258
 
259
assign status_bits_irq_mask_nxt  = ldm_status_bits           ? read_data_filtered     [27] :
260
                                   i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask      :
261
                                   i_status_bits_sel == 3'd1 ? alu_out                [27] :
262
                                                               i_copro_read_data      [27] ;
263
 
264
assign status_bits_firq_mask_nxt = ldm_status_bits           ? read_data_filtered     [26] :
265
                                   i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask     :
266
                                   i_status_bits_sel == 3'd1 ? alu_out                [26] :
267
                                                               i_copro_read_data      [26] ;
268
 
269
 
270
 
271
// ========================================================
272
// Adders
273
// ========================================================
274
assign pc_plus4       = pc         + 32'd4;
275
assign pc_minus4      = pc         - 32'd4;
276
assign daddress_plus4 = o_daddress + 32'd4;
277
assign alu_plus4      = alu_out    + 32'd4;
278
assign rn_plus4       = rn         + 32'd4;
279
 
280
// ========================================================
281
// Barrel Shift Amount Select
282
// ========================================================
283
// An immediate shift value of 0 is translated into 32
284
assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0                         :
285
                      i_barrel_shift_amount_sel == 2'd1 ? rs[7:0]                      :
286
                                                          {3'd0, i_imm_shift_amount  } ;
287
 
288
 
289
// ========================================================
290
// Barrel Shift Data Select
291
// ========================================================
292
assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32 : rm ;
293
 
294
 
295
// ========================================================
296
// Interrupt vector Select
297
// ========================================================
298
 
299
assign interrupt_vector = // Reset vector
300
                          (i_interrupt_vector_sel == 3'd0) ? 32'h00000000 :
301
                          // Data abort interrupt vector                 
302
                          (i_interrupt_vector_sel == 3'd1) ? 32'h00000010 :
303
                          // Fast interrupt vector  
304
                          (i_interrupt_vector_sel == 3'd2) ? 32'h0000001c :
305
                          // Regular interrupt vector
306
                          (i_interrupt_vector_sel == 3'd3) ? 32'h00000018 :
307
                          // Prefetch abort interrupt vector
308
                          (i_interrupt_vector_sel == 3'd5) ? 32'h0000000c :
309
                          // Undefined instruction interrupt vector
310
                          (i_interrupt_vector_sel == 3'd6) ? 32'h00000004 :
311
                          // Software (SWI) interrupt vector
312
                          (i_interrupt_vector_sel == 3'd7) ? 32'h00000008 :
313
                          // Default is the address exception interrupt
314
                                                             32'h00000014 ;
315
 
316
 
317
// ========================================================
318
// Address Select
319
// ========================================================
320
assign pc_dmem_wen    = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[3:0] == 4'd15;
321
 
322
// If rd is the pc, then seperate the address bits from the status bits for
323
// generating the next address to fetch
324
assign alu_out_pc_filtered = pc_wen && i_pc_sel == 3'd1 ? pcf(alu_out) : alu_out;
325
 
326
// if current instruction does not execute because it does not meet the condition
327
// then address advances to next instruction
328
assign o_iaddress_nxt = (pc_dmem_wen)            ? pcf(read_data_filtered) :
329
                        (!execute)               ? pc_plus4                :
330
                        (i_iaddress_sel == 4'd0) ? pc_plus4                :
331
                        (i_iaddress_sel == 4'd1) ? alu_out_pc_filtered     :
332
                        (i_iaddress_sel == 4'd2) ? interrupt_vector        :
333
                                                   pc                      ;
334
 
335
 
336
 
337
// if current instruction does not execute because it does not meet the condition
338
// then address advances to next instruction
339
assign o_daddress_nxt = (i_daddress_sel == 4'd1) ? alu_out_pc_filtered   :
340
                        (i_daddress_sel == 4'd2) ? interrupt_vector      :
341
                        (i_daddress_sel == 4'd4) ? rn                    :
342
                        (i_daddress_sel == 4'd5) ? daddress_plus4        :  // MTRANS address incrementer
343
                        (i_daddress_sel == 4'd6) ? alu_plus4             :  // MTRANS decrement after
344
                                                   rn_plus4              ;  // MTRANS increment before
345
 
346
// Data accesses use 32-bit address space, but instruction
347
// accesses are restricted to 26 bit space
348
assign adex_nxt      = |o_iaddress_nxt[31:26] && i_decode_iaccess;
349
 
350
 
351
// ========================================================
352
// Filter Read Data
353
// ========================================================
354 35 csantifort
// mem_load_rd[10:9]-> shift ROR bytes
355
// mem_load_rd[8]   -> load flags with PC
356
// mem_load_rd[7]   -> load status bits with PC
357
// mem_load_rd[6:5] -> Write into this Mode registers
358 16 csantifort
// mem_load_rd[4]   -> zero_extend byte
359
// mem_load_rd[3:0] -> Destination Register 
360 53 csantifort
assign read_data_filtered1 = i_wb_load_rd[10:9] == 2'd0 ? i_wb_read_data                                :
361
                             i_wb_load_rd[10:9] == 2'd1 ? {i_wb_read_data[7:0],  i_wb_read_data[31:8]}  :
362
                             i_wb_load_rd[10:9] == 2'd2 ? {i_wb_read_data[15:0], i_wb_read_data[31:16]} :
363
                                                          {i_wb_read_data[23:0], i_wb_read_data[31:24]} ;
364 16 csantifort
 
365
assign read_data_filtered  = i_wb_load_rd[4] ? {24'd0, read_data_filtered1[7:0]} : read_data_filtered1 ;
366
 
367
 
368
// ========================================================
369
// Program Counter Select
370
// ========================================================
371
// If current instruction does not execute because it does not meet the condition
372
// then PC advances to next instruction
373
assign pc_nxt = (!execute)       ? pc_plus4                :
374
                i_pc_sel == 3'd0 ? pc_plus4                :
375
                i_pc_sel == 3'd1 ? alu_out                 :
376
                i_pc_sel == 3'd2 ? interrupt_vector        :
377
                i_pc_sel == 3'd3 ? pcf(read_data_filtered) :
378
                                   pc_minus4               ;
379
 
380
 
381
// ========================================================
382
// Register Write Select
383
// ========================================================
384
 
385
assign save_int_pc    = { status_bits_flags,
386
                          status_bits_irq_mask,
387
                          status_bits_firq_mask,
388
                          pc[25:2],
389
                          status_bits_mode      };
390
 
391
 
392
assign save_int_pc_m4 = { status_bits_flags,
393
                          status_bits_irq_mask,
394
                          status_bits_firq_mask,
395
                          pc_minus4[25:2],
396
                          status_bits_mode      };
397
 
398
 
399
assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out               :
400
                       // save pc to lr on an interrupt                    
401
                       i_reg_write_sel == 3'd1 ? save_int_pc_m4        :
402
                       // to update Rd at the end of Multiplication
403
                       i_reg_write_sel == 3'd2 ? multiply_out          :
404
                       i_reg_write_sel == 3'd3 ? o_status_bits         :
405
                       i_reg_write_sel == 3'd5 ? i_copro_read_data     :  // mrc
406
                       i_reg_write_sel == 3'd6 ? base_address          :
407
                                                 save_int_pc           ;
408
 
409
 
410
// ========================================================
411
// Byte Enable Select
412
// ========================================================
413
assign byte_enable_nxt = i_byte_enable_sel == 2'd0   ? 4'b1111 :  // word write
414
                         i_byte_enable_sel == 2'd2   ?            // halfword write
415
                         ( o_daddress_nxt[1] == 1'd0 ? 4'b0011 :
416
                                                       4'b1100  ) :
417
 
418
                         o_daddress_nxt[1:0] == 2'd0 ? 4'b0001 :  // byte write
419
                         o_daddress_nxt[1:0] == 2'd1 ? 4'b0010 :
420
                         o_daddress_nxt[1:0] == 2'd2 ? 4'b0100 :
421
                                                       4'b1000 ;
422
 
423
 
424
// ========================================================
425
// Write Data Select
426
// ========================================================
427
assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd            :
428
                                                    {4{rd[ 7:0]}} ;
429
 
430
 
431
// ========================================================
432
// Conditional Execution
433
// ========================================================
434
assign execute = conditional_execute ( i_condition, status_bits_flags );
435
 
436
// allow the PC to increment to the next instruction when current
437
// instruction does not execute
438
assign pc_wen       = (i_pc_wen || !execute) && !i_conflict;
439
 
440
// only update register bank if current instruction executes
441
assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
442
 
443
 
444
// ========================================================
445
// Priviledged output flag
446
// ========================================================
447
// Need to look at status_bits_mode_nxt so switch to priviledged mode
448
// at the same time as assert interrupt vector address
449
assign priviledged_nxt  = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ;
450
 
451
 
452
// ========================================================
453
// Write Enable
454
// ========================================================
455
// This must be de-asserted when execute is fault
456
assign write_enable_nxt = execute && i_write_data_wen;
457
 
458
 
459
// ========================================================
460
// Address Valid
461
// ========================================================
462 35 csantifort
assign daddress_valid_nxt = execute && i_decode_daccess && !i_core_stall;
463 16 csantifort
 
464 20 csantifort
// For some multi-cycle instructions, the stream of instrution
465
// reads can be paused. However if the instruction does not execute
466
// then the read stream must not be interrupted.
467
assign iaddress_valid_nxt = i_decode_iaccess || !execute;
468 16 csantifort
 
469 20 csantifort
 
470 16 csantifort
// ========================================================
471 20 csantifort
// Use read value from data memory instead of from register
472
// ========================================================
473
assign rn = i_rn_use_read && i_rn_sel == load_rd_c ? read_data_filtered_c : reg_bank_rn;
474
assign rm = i_rm_use_read && i_rm_sel == load_rd_c ? read_data_filtered_c : reg_bank_rm;
475
assign rs = i_rs_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rs;
476
assign rd = i_rd_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rd;
477
 
478
 
479
always@( posedge i_clk )
480
    if ( i_wb_read_data_valid )
481
        begin
482
        read_data_filtered_r <= read_data_filtered;
483
        load_rd_r            <= i_wb_load_rd[3:0];
484
        end
485
 
486
assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r;
487
assign load_rd_c            = i_wb_read_data_valid ? i_wb_load_rd[3:0]  : load_rd_r;
488
 
489
 
490
// ========================================================
491 35 csantifort
// Set mode for the destination registers of a mem read
492
// ========================================================
493
// The mode is either user mode, or the current mode
494
assign  exec_load_rd_nxt   = { i_decode_load_rd[7:6],
495
                               i_decode_load_rd[5] ? USR : status_bits_mode,  // 1 bit -> 2 bits
496
                               i_decode_load_rd[4:0] };
497
 
498
 
499
// ========================================================
500 16 csantifort
// Register Update
501
// ========================================================
502 35 csantifort
assign o_exec_stall                    = barrel_shift_stall;
503 16 csantifort
 
504 35 csantifort
assign daddress_update                 = !i_core_stall;
505
assign exec_load_rd_update             = !i_core_stall && execute;
506
assign priviledged_update              = !i_core_stall;
507
assign exclusive_update                = !i_core_stall && execute;
508
assign write_enable_update             = !i_core_stall;
509
assign write_data_update               = !i_core_stall && execute && i_write_data_wen;
510
assign byte_enable_update              = !i_core_stall && execute && i_write_data_wen;
511 16 csantifort
 
512 35 csantifort
assign iaddress_update                 = pc_dmem_wen || (!i_core_stall && !i_conflict);
513
assign copro_write_data_update         = !i_core_stall && execute && i_copro_write_data_wen;
514 16 csantifort
 
515 35 csantifort
assign base_address_update             = !i_core_stall && execute && i_base_address_wen;
516
assign status_bits_flags_update        = ldm_flags       || (!i_core_stall && execute && i_status_bits_flags_wen);
517
assign status_bits_mode_update         = ldm_status_bits || (!i_core_stall && execute && i_status_bits_mode_wen);
518
assign status_bits_mode_rds_oh_update  = !i_core_stall;
519
assign status_bits_irq_mask_update     = ldm_status_bits || (!i_core_stall && execute && i_status_bits_irq_mask_wen);
520
assign status_bits_firq_mask_update    = ldm_status_bits || (!i_core_stall && execute && i_status_bits_firq_mask_wen);
521 16 csantifort
 
522
 
523
always @( posedge i_clk )
524
    begin
525
    o_daddress              <= daddress_update                ? o_daddress_nxt               : o_daddress;
526
    o_daddress_valid        <= daddress_update                ? daddress_valid_nxt           : o_daddress_valid;
527 35 csantifort
    o_exec_load_rd          <= exec_load_rd_update            ? exec_load_rd_nxt             : o_exec_load_rd;
528 16 csantifort
    o_priviledged           <= priviledged_update             ? priviledged_nxt              : o_priviledged;
529
    o_exclusive             <= exclusive_update               ? i_decode_exclusive           : o_exclusive;
530
    o_write_enable          <= write_enable_update            ? write_enable_nxt             : o_write_enable;
531
    o_write_data            <= write_data_update              ? write_data_nxt               : o_write_data;
532
    o_byte_enable           <= byte_enable_update             ? byte_enable_nxt              : o_byte_enable;
533
    o_iaddress              <= iaddress_update                ? o_iaddress_nxt               : o_iaddress;
534
    o_iaddress_valid        <= iaddress_update                ? iaddress_valid_nxt           : o_iaddress_valid;
535
    o_adex                  <= iaddress_update                ? adex_nxt                     : o_adex;
536
    o_copro_write_data      <= copro_write_data_update        ? write_data_nxt               : o_copro_write_data;
537
 
538
    base_address            <= base_address_update            ? rn                           : base_address;
539
 
540
    status_bits_flags       <= status_bits_flags_update       ? status_bits_flags_nxt        : status_bits_flags;
541
    status_bits_mode        <= status_bits_mode_update        ? status_bits_mode_nxt         : status_bits_mode;
542
    status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt  : status_bits_mode_rds_oh;
543
    status_bits_irq_mask    <= status_bits_irq_mask_update    ? status_bits_irq_mask_nxt     : status_bits_irq_mask;
544
    status_bits_firq_mask   <= status_bits_firq_mask_update   ? status_bits_firq_mask_nxt    : status_bits_firq_mask;
545
    end
546
 
547 35 csantifort
 
548 16 csantifort
// ========================================================
549
// Instantiate Barrel Shift
550
// ========================================================
551
a25_barrel_shift u_barrel_shift  (
552 35 csantifort
    .i_clk            ( i_clk                     ),
553 16 csantifort
    .i_in             ( barrel_shift_in           ),
554
    .i_carry_in       ( status_bits_flags[1]      ),
555
    .i_shift_amount   ( shift_amount              ),
556
    .i_shift_imm_zero ( i_shift_imm_zero          ),
557
    .i_function       ( i_barrel_shift_function   ),
558
 
559
    .o_out            ( barrel_shift_out          ),
560 35 csantifort
    .o_carry_out      ( barrel_shift_carry        ),
561
    .o_stall          ( barrel_shift_stall        )
562 16 csantifort
);
563
 
564
 
565
// ========================================================
566
// Instantiate ALU
567
// ========================================================
568
a25_alu u_alu (
569
    .i_a_in                 ( rn                    ),
570
    .i_b_in                 ( barrel_shift_out      ),
571
    .i_barrel_shift_carry   ( barrel_shift_carry    ),
572
    .i_status_bits_carry    ( status_bits_flags[1]  ),
573
    .i_function             ( i_alu_function        ),
574
 
575
    .o_out                  ( alu_out               ),
576
    .o_flags                ( alu_flags             )
577
);
578
 
579
 
580
// ========================================================
581
// Instantiate Booth 64-bit Multiplier-Accumulator
582
// ========================================================
583
a25_multiply u_multiply (
584
    .i_clk          ( i_clk                 ),
585 35 csantifort
    .i_core_stall   ( i_core_stall          ),
586 16 csantifort
    .i_a_in         ( rs                    ),
587
    .i_b_in         ( rm                    ),
588
    .i_function     ( i_multiply_function   ),
589
    .i_execute      ( execute               ),
590
    .o_out          ( multiply_out          ),
591
    .o_flags        ( multiply_flags        ),  // [1] = N, [0] = Z
592
    .o_done         ( o_multiply_done       )
593
);
594
 
595
 
596
// ========================================================
597
// Instantiate Register Bank
598
// ========================================================
599
a25_register_bank u_register_bank(
600
    .i_clk                   ( i_clk                     ),
601 35 csantifort
    .i_core_stall            ( i_core_stall              ),
602 16 csantifort
    .i_mem_stall             ( i_mem_stall               ),
603
    .i_rm_sel                ( i_rm_sel                  ),
604
    .i_rs_sel                ( i_rs_sel                  ),
605
    .i_rn_sel                ( i_rn_sel                  ),
606
    .i_pc_wen                ( pc_wen                    ),
607
    .i_reg_bank_wen          ( reg_bank_wen              ),
608
    .i_pc                    ( pc_nxt[25:2]              ),
609
    .i_reg                   ( reg_write_nxt             ),
610
    .i_mode_idec             ( i_status_bits_mode        ),
611
    .i_mode_exec             ( status_bits_mode          ),
612
 
613
    .i_wb_read_data          ( read_data_filtered        ),
614
    .i_wb_read_data_valid    ( i_wb_read_data_valid      ),
615
    .i_wb_read_data_rd       ( i_wb_load_rd[3:0]         ),
616 35 csantifort
    .i_wb_mode               ( i_wb_load_rd[6:5]         ),
617 16 csantifort
 
618
    .i_status_bits_flags     ( status_bits_flags         ),
619
    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
620
    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
621
 
622
    // pre-encoded in decode stage to speed up long path
623
    .i_firq_not_user_mode    ( i_firq_not_user_mode      ),
624
 
625
    // use one-hot version for speed, combine with i_user_mode_regs_store
626
    .i_mode_rds_exec         ( status_bits_mode_rds_oh   ),
627
 
628 20 csantifort
    .o_rm                    ( reg_bank_rm               ),
629
    .o_rs                    ( reg_bank_rs               ),
630
    .o_rd                    ( reg_bank_rd               ),
631
    .o_rn                    ( reg_bank_rn               ),
632 16 csantifort
    .o_pc                    ( pc                        )
633
);
634
 
635
 
636 20 csantifort
 
637 16 csantifort
// ========================================================
638
// Debug - non-synthesizable code
639
// ========================================================
640
//synopsys translate_off
641
 
642
wire    [(2*8)-1:0]    xCONDITION;
643
wire    [(4*8)-1:0]    xMODE;
644
 
645
assign  xCONDITION           = i_condition == EQ ? "EQ"  :
646
                               i_condition == NE ? "NE"  :
647
                               i_condition == CS ? "CS"  :
648
                               i_condition == CC ? "CC"  :
649
                               i_condition == MI ? "MI"  :
650
                               i_condition == PL ? "PL"  :
651
                               i_condition == VS ? "VS"  :
652
                               i_condition == VC ? "VC"  :
653
                               i_condition == HI ? "HI"  :
654
                               i_condition == LS ? "LS"  :
655
                               i_condition == GE ? "GE"  :
656
                               i_condition == LT ? "LT"  :
657
                               i_condition == GT ? "GT"  :
658
                               i_condition == LE ? "LE"  :
659
                               i_condition == AL ? "AL"  :
660
                                                   "NV " ;
661
 
662
assign  xMODE  =  status_bits_mode == SVC  ? "SVC"  :
663
                  status_bits_mode == IRQ  ? "IRQ"  :
664
                  status_bits_mode == FIRQ ? "FIRQ" :
665
                  status_bits_mode == USR  ? "USR"  :
666
                                             "XXX"  ;
667
 
668
 
669
//synopsys translate_on
670
 
671
endmodule
672
 
673
 

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