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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_execute.v] - Blame information for rev 83

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1 16 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Execute stage of Amber 25 Core                              //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Executes instructions. Instantiates the register file, ALU  //
10
//  multiplication unit and barrel shifter. This stage is       //
11
//  relitively simple. All the complex stuff is done in the     //
12
//  decode stage.                                               //
13
//                                                              //
14
//  Author(s):                                                  //
15
//      - Conor Santifort, csantifort.amber@gmail.com           //
16
//                                                              //
17
//////////////////////////////////////////////////////////////////
18
//                                                              //
19
// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
20
//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
23
// removed from the file and that any derivative work contains  //
24
// the original copyright notice and the associated disclaimer. //
25
//                                                              //
26
// This source file is free software; you can redistribute it   //
27
// and/or modify it under the terms of the GNU Lesser General   //
28
// Public License as published by the Free Software Foundation; //
29
// either version 2.1 of the License, or (at your option) any   //
30
// later version.                                               //
31
//                                                              //
32
// This source is distributed in the hope that it will be       //
33
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
34
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
35
// PURPOSE.  See the GNU Lesser General Public License for more //
36
// details.                                                     //
37
//                                                              //
38
// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
40
// from http://www.opencores.org/lgpl.shtml                     //
41
//                                                              //
42
//////////////////////////////////////////////////////////////////
43
 
44
 
45
module a25_execute (
46
 
47
input                       i_clk,
48 35 csantifort
input                       i_core_stall,               // stall all stages of the Amber core at the same time
49 16 csantifort
input                       i_mem_stall,                // data memory access stalls
50 35 csantifort
output                      o_exec_stall,               // stall the core pipeline
51 16 csantifort
 
52
input       [31:0]          i_wb_read_data,             // data reads
53
input                       i_wb_read_data_valid,       // read data is valid
54 35 csantifort
input       [10:0]          i_wb_load_rd,               // Rd for data reads
55 16 csantifort
 
56
input       [31:0]          i_copro_read_data,          // From Co-Processor, to either Register 
57
                                                        // or Memory
58
input                       i_decode_iaccess,           // Indicates an instruction access
59
input                       i_decode_daccess,           // Indicates a data access
60
input       [7:0]           i_decode_load_rd,           // The destination register for a load instruction
61
 
62
output reg  [31:0]          o_copro_write_data = 'd0,
63
output reg  [31:0]          o_write_data = 'd0,
64
output reg  [31:0]          o_iaddress = 32'hdead_dead,
65
output      [31:0]          o_iaddress_nxt,             // un-registered version of address to the 
66
                                                        // cache rams address ports
67
output reg                  o_iaddress_valid = 'd0,     // High when instruction address is valid
68
output reg  [31:0]          o_daddress = 32'h0,         // Address to data cache
69
output      [31:0]          o_daddress_nxt,             // un-registered version of address to the 
70
                                                        // cache rams address ports
71
output reg                  o_daddress_valid = 'd0,     // High when data address is valid
72
output reg                  o_adex = 'd0,               // Address Exception
73
output reg                  o_priviledged = 'd0,        // Priviledged access
74
output reg                  o_exclusive = 'd0,          // swap access
75
output reg                  o_write_enable = 'd0,
76
output reg  [3:0]           o_byte_enable = 'd0,
77 35 csantifort
output reg  [8:0]           o_exec_load_rd = 'd0,       // The destination register for a load instruction
78 16 csantifort
output      [31:0]          o_status_bits,              // Full PC will all status bits, but PC part zero'ed out
79
output                      o_multiply_done,
80
 
81
 
82
// --------------------------------------------------
83
// Control signals from Instruction Decode stage
84
// --------------------------------------------------
85
input      [1:0]            i_status_bits_mode,
86
input                       i_status_bits_irq_mask,
87
input                       i_status_bits_firq_mask,
88
input      [31:0]           i_imm32,
89
input      [4:0]            i_imm_shift_amount,
90
input                       i_shift_imm_zero,
91
input      [3:0]            i_condition,
92
input                       i_decode_exclusive,       // swap access
93
 
94
input      [3:0]            i_rm_sel,
95
input      [3:0]            i_rs_sel,
96
input      [3:0]            i_rn_sel,
97
input      [1:0]            i_barrel_shift_amount_sel,
98
input      [1:0]            i_barrel_shift_data_sel,
99
input      [1:0]            i_barrel_shift_function,
100
input      [8:0]            i_alu_function,
101
input      [1:0]            i_multiply_function,
102
input      [2:0]            i_interrupt_vector_sel,
103
input      [3:0]            i_iaddress_sel,
104
input      [3:0]            i_daddress_sel,
105
input      [2:0]            i_pc_sel,
106
input      [1:0]            i_byte_enable_sel,
107
input      [2:0]            i_status_bits_sel,
108
input      [2:0]            i_reg_write_sel,
109
input                       i_user_mode_regs_store_nxt,
110
input                       i_firq_not_user_mode,
111 83 csantifort
input                       i_use_carry_in,         // e.g. add with carry instruction
112 16 csantifort
 
113
input                       i_write_data_wen,
114
input                       i_base_address_wen,     // save LDM base address register, 
115
                                                    // in case of data abort
116
input                       i_pc_wen,
117
input      [14:0]           i_reg_bank_wen,
118
input                       i_status_bits_flags_wen,
119
input                       i_status_bits_mode_wen,
120
input                       i_status_bits_irq_mask_wen,
121
input                       i_status_bits_firq_mask_wen,
122
input                       i_copro_write_data_wen,
123 20 csantifort
input                       i_conflict,
124
input                       i_rn_use_read,
125
input                       i_rm_use_read,
126
input                       i_rs_use_read,
127
input                       i_rd_use_read
128 16 csantifort
);
129
 
130 82 csantifort
`include "a25_localparams.vh"
131
`include "a25_functions.vh"
132 16 csantifort
 
133
// ========================================================
134
// Internal signals
135
// ========================================================
136
wire [31:0]         write_data_nxt;
137
wire [3:0]          byte_enable_nxt;
138
wire [31:0]         pc_plus4;
139
wire [31:0]         pc_minus4;
140
wire [31:0]         daddress_plus4;
141
wire [31:0]         alu_plus4;
142
wire [31:0]         rn_plus4;
143
wire [31:0]         alu_out;
144
wire [3:0]          alu_flags;
145
wire [31:0]         rm;
146
wire [31:0]         rs;
147
wire [31:0]         rd;
148
wire [31:0]         rn;
149 20 csantifort
wire [31:0]         reg_bank_rn;
150
wire [31:0]         reg_bank_rm;
151
wire [31:0]         reg_bank_rs;
152
wire [31:0]         reg_bank_rd;
153 16 csantifort
wire [31:0]         pc;
154
wire [31:0]         pc_nxt;
155
wire [31:0]         interrupt_vector;
156
wire [7:0]          shift_amount;
157
wire [31:0]         barrel_shift_in;
158
wire [31:0]         barrel_shift_out;
159
wire                barrel_shift_carry;
160 35 csantifort
wire                barrel_shift_stall;
161 16 csantifort
 
162
wire [3:0]          status_bits_flags_nxt;
163
reg  [3:0]          status_bits_flags = 'd0;
164
wire [1:0]          status_bits_mode_nxt;
165
reg  [1:0]          status_bits_mode = SVC;
166
                    // one-hot encoded rs select
167
wire [3:0]          status_bits_mode_rds_oh_nxt;
168
reg  [3:0]          status_bits_mode_rds_oh = 1'd1 << OH_SVC;
169
wire                status_bits_mode_rds_oh_update;
170
wire                status_bits_irq_mask_nxt;
171
reg                 status_bits_irq_mask = 1'd1;
172
wire                status_bits_firq_mask_nxt;
173
reg                 status_bits_firq_mask = 1'd1;
174 35 csantifort
wire [8:0]          exec_load_rd_nxt;
175 16 csantifort
 
176
wire                execute;                    // high when condition execution is true
177
wire [31:0]         reg_write_nxt;
178
wire                pc_wen;
179
wire [14:0]         reg_bank_wen;
180
wire [31:0]         multiply_out;
181
wire [1:0]          multiply_flags;
182
reg  [31:0]         base_address = 'd0;             // Saves base address during LDM instruction in 
183
                                                    // case of data abort
184
wire [31:0]         read_data_filtered1;
185
wire [31:0]         read_data_filtered;
186 20 csantifort
wire [31:0]         read_data_filtered_c;
187
reg  [31:0]         read_data_filtered_r = 'd0;
188
reg  [3:0]          load_rd_r = 'd0;
189
wire [3:0]          load_rd_c;
190 16 csantifort
 
191
wire                write_enable_nxt;
192
wire                daddress_valid_nxt;
193
wire                iaddress_valid_nxt;
194
wire                priviledged_nxt;
195
wire                priviledged_update;
196
wire                iaddress_update;
197
wire                daddress_update;
198
wire                base_address_update;
199
wire                write_data_update;
200
wire                copro_write_data_update;
201
wire                byte_enable_update;
202
wire                exec_load_rd_update;
203
wire                write_enable_update;
204
wire                exclusive_update;
205
wire                status_bits_flags_update;
206
wire                status_bits_mode_update;
207
wire                status_bits_irq_mask_update;
208
wire                status_bits_firq_mask_update;
209
 
210
wire [31:0]         alu_out_pc_filtered;
211
wire                adex_nxt;
212
wire [31:0]         save_int_pc;
213
wire [31:0]         save_int_pc_m4;
214
wire                ldm_flags;
215
wire                ldm_status_bits;
216
 
217 83 csantifort
wire                carry_in;
218
 
219
 
220 16 csantifort
// ========================================================
221
// Status Bits in PC register
222
// ========================================================
223 54 csantifort
wire [1:0] status_bits_mode_out;
224
assign status_bits_mode_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && !ldm_status_bits) ?
225
                                    alu_out[1:0] : status_bits_mode ;
226
 
227 16 csantifort
assign o_status_bits = {   status_bits_flags,           // 31:28
228
                           status_bits_irq_mask,        // 7
229
                           status_bits_firq_mask,       // 6
230
                           24'd0,
231 54 csantifort
                           status_bits_mode_out };      // 1:0 = mode
232 16 csantifort
 
233
 
234
// ========================================================
235
// Status Bits Select
236
// ========================================================
237 35 csantifort
assign ldm_flags                 = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[8];
238
assign ldm_status_bits           = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[7];
239 16 csantifort
 
240
 
241
assign status_bits_flags_nxt     = ldm_flags                 ? read_data_filtered[31:28]           :
242
                                   i_status_bits_sel == 3'd0 ? alu_flags                           :
243
                                   i_status_bits_sel == 3'd1 ? alu_out          [31:28]            :
244
                                   i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28]            :
245
                                   // 4 = update flags after a multiply operation
246 82 csantifort
                                   i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } :
247
                                   // regops that do not change the overflow flag
248
                                   i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } :
249
                                                               4'b1111 ;
250 16 csantifort
 
251
assign status_bits_mode_nxt      = ldm_status_bits           ? read_data_filtered [1:0] :
252
                                   i_status_bits_sel == 3'd0 ? i_status_bits_mode       :
253 82 csantifort
                                   i_status_bits_sel == 3'd5 ? i_status_bits_mode       :
254 16 csantifort
                                   i_status_bits_sel == 3'd1 ? alu_out            [1:0] :
255
                                                               i_copro_read_data  [1:0] ;
256
 
257
 
258
// Used for the Rds output of register_bank - this special version of
259
// status_bits_mode speeds up the critical path from status_bits_mode through the
260
// register_bank, barrel_shifter and alu. It moves a mux needed for the
261
// i_user_mode_regs_store_nxt signal back into the previous stage -
262
// so its really part of the decode stage even though the logic is right here
263
// In addition the signal is one-hot encoded to further speed up the logic
264
 
265
assign status_bits_mode_rds_oh_nxt    = i_user_mode_regs_store_nxt ? 1'd1 << OH_USR                            :
266
                                        status_bits_mode_update    ? oh_status_bits_mode(status_bits_mode_nxt) :
267
                                                                     oh_status_bits_mode(status_bits_mode)     ;
268
 
269
 
270
assign status_bits_irq_mask_nxt  = ldm_status_bits           ? read_data_filtered     [27] :
271
                                   i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask      :
272 82 csantifort
                                   i_status_bits_sel == 3'd5 ? i_status_bits_irq_mask      :
273 16 csantifort
                                   i_status_bits_sel == 3'd1 ? alu_out                [27] :
274
                                                               i_copro_read_data      [27] ;
275
 
276
assign status_bits_firq_mask_nxt = ldm_status_bits           ? read_data_filtered     [26] :
277
                                   i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask     :
278 82 csantifort
                                   i_status_bits_sel == 3'd5 ? i_status_bits_firq_mask     :
279 16 csantifort
                                   i_status_bits_sel == 3'd1 ? alu_out                [26] :
280
                                                               i_copro_read_data      [26] ;
281
 
282
 
283
 
284
// ========================================================
285
// Adders
286
// ========================================================
287
assign pc_plus4       = pc         + 32'd4;
288
assign pc_minus4      = pc         - 32'd4;
289
assign daddress_plus4 = o_daddress + 32'd4;
290
assign alu_plus4      = alu_out    + 32'd4;
291
assign rn_plus4       = rn         + 32'd4;
292
 
293
// ========================================================
294
// Barrel Shift Amount Select
295
// ========================================================
296
// An immediate shift value of 0 is translated into 32
297
assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0                         :
298
                      i_barrel_shift_amount_sel == 2'd1 ? rs[7:0]                      :
299
                                                          {3'd0, i_imm_shift_amount  } ;
300
 
301
 
302
// ========================================================
303
// Barrel Shift Data Select
304
// ========================================================
305
assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32 : rm ;
306
 
307
 
308
// ========================================================
309
// Interrupt vector Select
310
// ========================================================
311
 
312
assign interrupt_vector = // Reset vector
313
                          (i_interrupt_vector_sel == 3'd0) ? 32'h00000000 :
314
                          // Data abort interrupt vector                 
315
                          (i_interrupt_vector_sel == 3'd1) ? 32'h00000010 :
316
                          // Fast interrupt vector  
317
                          (i_interrupt_vector_sel == 3'd2) ? 32'h0000001c :
318
                          // Regular interrupt vector
319
                          (i_interrupt_vector_sel == 3'd3) ? 32'h00000018 :
320
                          // Prefetch abort interrupt vector
321
                          (i_interrupt_vector_sel == 3'd5) ? 32'h0000000c :
322
                          // Undefined instruction interrupt vector
323
                          (i_interrupt_vector_sel == 3'd6) ? 32'h00000004 :
324
                          // Software (SWI) interrupt vector
325
                          (i_interrupt_vector_sel == 3'd7) ? 32'h00000008 :
326
                          // Default is the address exception interrupt
327
                                                             32'h00000014 ;
328
 
329
 
330
// ========================================================
331
// Address Select
332
// ========================================================
333
assign pc_dmem_wen    = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[3:0] == 4'd15;
334
 
335
// If rd is the pc, then seperate the address bits from the status bits for
336
// generating the next address to fetch
337
assign alu_out_pc_filtered = pc_wen && i_pc_sel == 3'd1 ? pcf(alu_out) : alu_out;
338
 
339
// if current instruction does not execute because it does not meet the condition
340
// then address advances to next instruction
341
assign o_iaddress_nxt = (pc_dmem_wen)            ? pcf(read_data_filtered) :
342
                        (!execute)               ? pc_plus4                :
343
                        (i_iaddress_sel == 4'd0) ? pc_plus4                :
344
                        (i_iaddress_sel == 4'd1) ? alu_out_pc_filtered     :
345
                        (i_iaddress_sel == 4'd2) ? interrupt_vector        :
346
                                                   pc                      ;
347
 
348
 
349
 
350
// if current instruction does not execute because it does not meet the condition
351
// then address advances to next instruction
352
assign o_daddress_nxt = (i_daddress_sel == 4'd1) ? alu_out_pc_filtered   :
353
                        (i_daddress_sel == 4'd2) ? interrupt_vector      :
354
                        (i_daddress_sel == 4'd4) ? rn                    :
355
                        (i_daddress_sel == 4'd5) ? daddress_plus4        :  // MTRANS address incrementer
356
                        (i_daddress_sel == 4'd6) ? alu_plus4             :  // MTRANS decrement after
357
                                                   rn_plus4              ;  // MTRANS increment before
358
 
359
// Data accesses use 32-bit address space, but instruction
360
// accesses are restricted to 26 bit space
361
assign adex_nxt      = |o_iaddress_nxt[31:26] && i_decode_iaccess;
362
 
363
 
364
// ========================================================
365
// Filter Read Data
366
// ========================================================
367 35 csantifort
// mem_load_rd[10:9]-> shift ROR bytes
368
// mem_load_rd[8]   -> load flags with PC
369
// mem_load_rd[7]   -> load status bits with PC
370
// mem_load_rd[6:5] -> Write into this Mode registers
371 16 csantifort
// mem_load_rd[4]   -> zero_extend byte
372
// mem_load_rd[3:0] -> Destination Register 
373 53 csantifort
assign read_data_filtered1 = i_wb_load_rd[10:9] == 2'd0 ? i_wb_read_data                                :
374
                             i_wb_load_rd[10:9] == 2'd1 ? {i_wb_read_data[7:0],  i_wb_read_data[31:8]}  :
375
                             i_wb_load_rd[10:9] == 2'd2 ? {i_wb_read_data[15:0], i_wb_read_data[31:16]} :
376
                                                          {i_wb_read_data[23:0], i_wb_read_data[31:24]} ;
377 16 csantifort
 
378
assign read_data_filtered  = i_wb_load_rd[4] ? {24'd0, read_data_filtered1[7:0]} : read_data_filtered1 ;
379
 
380
 
381
// ========================================================
382
// Program Counter Select
383
// ========================================================
384
// If current instruction does not execute because it does not meet the condition
385
// then PC advances to next instruction
386
assign pc_nxt = (!execute)       ? pc_plus4                :
387
                i_pc_sel == 3'd0 ? pc_plus4                :
388
                i_pc_sel == 3'd1 ? alu_out                 :
389
                i_pc_sel == 3'd2 ? interrupt_vector        :
390
                i_pc_sel == 3'd3 ? pcf(read_data_filtered) :
391
                                   pc_minus4               ;
392
 
393
 
394
// ========================================================
395
// Register Write Select
396
// ========================================================
397
 
398
assign save_int_pc    = { status_bits_flags,
399
                          status_bits_irq_mask,
400
                          status_bits_firq_mask,
401
                          pc[25:2],
402
                          status_bits_mode      };
403
 
404
 
405
assign save_int_pc_m4 = { status_bits_flags,
406
                          status_bits_irq_mask,
407
                          status_bits_firq_mask,
408
                          pc_minus4[25:2],
409
                          status_bits_mode      };
410
 
411
 
412
assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out               :
413
                       // save pc to lr on an interrupt                    
414
                       i_reg_write_sel == 3'd1 ? save_int_pc_m4        :
415
                       // to update Rd at the end of Multiplication
416
                       i_reg_write_sel == 3'd2 ? multiply_out          :
417
                       i_reg_write_sel == 3'd3 ? o_status_bits         :
418
                       i_reg_write_sel == 3'd5 ? i_copro_read_data     :  // mrc
419
                       i_reg_write_sel == 3'd6 ? base_address          :
420
                                                 save_int_pc           ;
421
 
422
 
423
// ========================================================
424
// Byte Enable Select
425
// ========================================================
426
assign byte_enable_nxt = i_byte_enable_sel == 2'd0   ? 4'b1111 :  // word write
427
                         i_byte_enable_sel == 2'd2   ?            // halfword write
428
                         ( o_daddress_nxt[1] == 1'd0 ? 4'b0011 :
429
                                                       4'b1100  ) :
430
 
431
                         o_daddress_nxt[1:0] == 2'd0 ? 4'b0001 :  // byte write
432
                         o_daddress_nxt[1:0] == 2'd1 ? 4'b0010 :
433
                         o_daddress_nxt[1:0] == 2'd2 ? 4'b0100 :
434
                                                       4'b1000 ;
435
 
436
 
437
// ========================================================
438
// Write Data Select
439
// ========================================================
440
assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd            :
441
                                                    {4{rd[ 7:0]}} ;
442
 
443
 
444
// ========================================================
445
// Conditional Execution
446
// ========================================================
447
assign execute = conditional_execute ( i_condition, status_bits_flags );
448
 
449
// allow the PC to increment to the next instruction when current
450
// instruction does not execute
451
assign pc_wen       = (i_pc_wen || !execute) && !i_conflict;
452
 
453
// only update register bank if current instruction executes
454
assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
455
 
456
 
457
// ========================================================
458
// Priviledged output flag
459
// ========================================================
460
// Need to look at status_bits_mode_nxt so switch to priviledged mode
461
// at the same time as assert interrupt vector address
462
assign priviledged_nxt  = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ;
463
 
464
 
465
// ========================================================
466
// Write Enable
467
// ========================================================
468
// This must be de-asserted when execute is fault
469
assign write_enable_nxt = execute && i_write_data_wen;
470
 
471
 
472
// ========================================================
473
// Address Valid
474
// ========================================================
475 35 csantifort
assign daddress_valid_nxt = execute && i_decode_daccess && !i_core_stall;
476 16 csantifort
 
477 20 csantifort
// For some multi-cycle instructions, the stream of instrution
478
// reads can be paused. However if the instruction does not execute
479
// then the read stream must not be interrupted.
480
assign iaddress_valid_nxt = i_decode_iaccess || !execute;
481 16 csantifort
 
482 20 csantifort
 
483 16 csantifort
// ========================================================
484 20 csantifort
// Use read value from data memory instead of from register
485
// ========================================================
486
assign rn = i_rn_use_read && i_rn_sel == load_rd_c ? read_data_filtered_c : reg_bank_rn;
487
assign rm = i_rm_use_read && i_rm_sel == load_rd_c ? read_data_filtered_c : reg_bank_rm;
488
assign rs = i_rs_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rs;
489
assign rd = i_rd_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rd;
490
 
491
 
492
always@( posedge i_clk )
493
    if ( i_wb_read_data_valid )
494
        begin
495
        read_data_filtered_r <= read_data_filtered;
496
        load_rd_r            <= i_wb_load_rd[3:0];
497
        end
498
 
499
assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r;
500
assign load_rd_c            = i_wb_read_data_valid ? i_wb_load_rd[3:0]  : load_rd_r;
501
 
502
 
503
// ========================================================
504 35 csantifort
// Set mode for the destination registers of a mem read
505
// ========================================================
506
// The mode is either user mode, or the current mode
507
assign  exec_load_rd_nxt   = { i_decode_load_rd[7:6],
508
                               i_decode_load_rd[5] ? USR : status_bits_mode,  // 1 bit -> 2 bits
509
                               i_decode_load_rd[4:0] };
510
 
511
 
512
// ========================================================
513 16 csantifort
// Register Update
514
// ========================================================
515 35 csantifort
assign o_exec_stall                    = barrel_shift_stall;
516 16 csantifort
 
517 35 csantifort
assign daddress_update                 = !i_core_stall;
518
assign exec_load_rd_update             = !i_core_stall && execute;
519
assign priviledged_update              = !i_core_stall;
520
assign exclusive_update                = !i_core_stall && execute;
521
assign write_enable_update             = !i_core_stall;
522
assign write_data_update               = !i_core_stall && execute && i_write_data_wen;
523
assign byte_enable_update              = !i_core_stall && execute && i_write_data_wen;
524 16 csantifort
 
525 35 csantifort
assign iaddress_update                 = pc_dmem_wen || (!i_core_stall && !i_conflict);
526
assign copro_write_data_update         = !i_core_stall && execute && i_copro_write_data_wen;
527 16 csantifort
 
528 35 csantifort
assign base_address_update             = !i_core_stall && execute && i_base_address_wen;
529
assign status_bits_flags_update        = ldm_flags       || (!i_core_stall && execute && i_status_bits_flags_wen);
530
assign status_bits_mode_update         = ldm_status_bits || (!i_core_stall && execute && i_status_bits_mode_wen);
531
assign status_bits_mode_rds_oh_update  = !i_core_stall;
532
assign status_bits_irq_mask_update     = ldm_status_bits || (!i_core_stall && execute && i_status_bits_irq_mask_wen);
533
assign status_bits_firq_mask_update    = ldm_status_bits || (!i_core_stall && execute && i_status_bits_firq_mask_wen);
534 16 csantifort
 
535
 
536
always @( posedge i_clk )
537
    begin
538
    o_daddress              <= daddress_update                ? o_daddress_nxt               : o_daddress;
539
    o_daddress_valid        <= daddress_update                ? daddress_valid_nxt           : o_daddress_valid;
540 35 csantifort
    o_exec_load_rd          <= exec_load_rd_update            ? exec_load_rd_nxt             : o_exec_load_rd;
541 16 csantifort
    o_priviledged           <= priviledged_update             ? priviledged_nxt              : o_priviledged;
542
    o_exclusive             <= exclusive_update               ? i_decode_exclusive           : o_exclusive;
543
    o_write_enable          <= write_enable_update            ? write_enable_nxt             : o_write_enable;
544
    o_write_data            <= write_data_update              ? write_data_nxt               : o_write_data;
545
    o_byte_enable           <= byte_enable_update             ? byte_enable_nxt              : o_byte_enable;
546
    o_iaddress              <= iaddress_update                ? o_iaddress_nxt               : o_iaddress;
547
    o_iaddress_valid        <= iaddress_update                ? iaddress_valid_nxt           : o_iaddress_valid;
548
    o_adex                  <= iaddress_update                ? adex_nxt                     : o_adex;
549
    o_copro_write_data      <= copro_write_data_update        ? write_data_nxt               : o_copro_write_data;
550
 
551
    base_address            <= base_address_update            ? rn                           : base_address;
552
 
553
    status_bits_flags       <= status_bits_flags_update       ? status_bits_flags_nxt        : status_bits_flags;
554
    status_bits_mode        <= status_bits_mode_update        ? status_bits_mode_nxt         : status_bits_mode;
555
    status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt  : status_bits_mode_rds_oh;
556
    status_bits_irq_mask    <= status_bits_irq_mask_update    ? status_bits_irq_mask_nxt     : status_bits_irq_mask;
557
    status_bits_firq_mask   <= status_bits_firq_mask_update   ? status_bits_firq_mask_nxt    : status_bits_firq_mask;
558
    end
559
 
560 35 csantifort
 
561 16 csantifort
// ========================================================
562
// Instantiate Barrel Shift
563
// ========================================================
564 83 csantifort
assign carry_in = i_use_carry_in ? status_bits_flags[1] : 1'd0;
565
 
566 16 csantifort
a25_barrel_shift u_barrel_shift  (
567 35 csantifort
    .i_clk            ( i_clk                     ),
568 16 csantifort
    .i_in             ( barrel_shift_in           ),
569 83 csantifort
    .i_carry_in       ( carry_in                  ),
570 16 csantifort
    .i_shift_amount   ( shift_amount              ),
571
    .i_shift_imm_zero ( i_shift_imm_zero          ),
572
    .i_function       ( i_barrel_shift_function   ),
573
 
574
    .o_out            ( barrel_shift_out          ),
575 35 csantifort
    .o_carry_out      ( barrel_shift_carry        ),
576
    .o_stall          ( barrel_shift_stall        )
577 16 csantifort
);
578
 
579
 
580
// ========================================================
581
// Instantiate ALU
582
// ========================================================
583
a25_alu u_alu (
584
    .i_a_in                 ( rn                    ),
585
    .i_b_in                 ( barrel_shift_out      ),
586
    .i_barrel_shift_carry   ( barrel_shift_carry    ),
587
    .i_status_bits_carry    ( status_bits_flags[1]  ),
588
    .i_function             ( i_alu_function        ),
589
 
590
    .o_out                  ( alu_out               ),
591
    .o_flags                ( alu_flags             )
592
);
593
 
594
 
595
// ========================================================
596
// Instantiate Booth 64-bit Multiplier-Accumulator
597
// ========================================================
598
a25_multiply u_multiply (
599
    .i_clk          ( i_clk                 ),
600 35 csantifort
    .i_core_stall   ( i_core_stall          ),
601 16 csantifort
    .i_a_in         ( rs                    ),
602
    .i_b_in         ( rm                    ),
603
    .i_function     ( i_multiply_function   ),
604
    .i_execute      ( execute               ),
605
    .o_out          ( multiply_out          ),
606
    .o_flags        ( multiply_flags        ),  // [1] = N, [0] = Z
607
    .o_done         ( o_multiply_done       )
608
);
609
 
610
 
611
// ========================================================
612
// Instantiate Register Bank
613
// ========================================================
614
a25_register_bank u_register_bank(
615
    .i_clk                   ( i_clk                     ),
616 35 csantifort
    .i_core_stall            ( i_core_stall              ),
617 16 csantifort
    .i_mem_stall             ( i_mem_stall               ),
618
    .i_rm_sel                ( i_rm_sel                  ),
619
    .i_rs_sel                ( i_rs_sel                  ),
620
    .i_rn_sel                ( i_rn_sel                  ),
621
    .i_pc_wen                ( pc_wen                    ),
622
    .i_reg_bank_wen          ( reg_bank_wen              ),
623
    .i_pc                    ( pc_nxt[25:2]              ),
624
    .i_reg                   ( reg_write_nxt             ),
625
    .i_mode_idec             ( i_status_bits_mode        ),
626
    .i_mode_exec             ( status_bits_mode          ),
627
 
628
    .i_wb_read_data          ( read_data_filtered        ),
629
    .i_wb_read_data_valid    ( i_wb_read_data_valid      ),
630
    .i_wb_read_data_rd       ( i_wb_load_rd[3:0]         ),
631 35 csantifort
    .i_wb_mode               ( i_wb_load_rd[6:5]         ),
632 16 csantifort
 
633
    .i_status_bits_flags     ( status_bits_flags         ),
634
    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
635
    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
636
 
637
    // pre-encoded in decode stage to speed up long path
638
    .i_firq_not_user_mode    ( i_firq_not_user_mode      ),
639
 
640
    // use one-hot version for speed, combine with i_user_mode_regs_store
641
    .i_mode_rds_exec         ( status_bits_mode_rds_oh   ),
642
 
643 20 csantifort
    .o_rm                    ( reg_bank_rm               ),
644
    .o_rs                    ( reg_bank_rs               ),
645
    .o_rd                    ( reg_bank_rd               ),
646
    .o_rn                    ( reg_bank_rn               ),
647 16 csantifort
    .o_pc                    ( pc                        )
648
);
649
 
650
 
651 20 csantifort
 
652 16 csantifort
// ========================================================
653
// Debug - non-synthesizable code
654
// ========================================================
655
//synopsys translate_off
656
 
657
wire    [(2*8)-1:0]    xCONDITION;
658
wire    [(4*8)-1:0]    xMODE;
659
 
660
assign  xCONDITION           = i_condition == EQ ? "EQ"  :
661
                               i_condition == NE ? "NE"  :
662
                               i_condition == CS ? "CS"  :
663
                               i_condition == CC ? "CC"  :
664
                               i_condition == MI ? "MI"  :
665
                               i_condition == PL ? "PL"  :
666
                               i_condition == VS ? "VS"  :
667
                               i_condition == VC ? "VC"  :
668
                               i_condition == HI ? "HI"  :
669
                               i_condition == LS ? "LS"  :
670
                               i_condition == GE ? "GE"  :
671
                               i_condition == LT ? "LT"  :
672
                               i_condition == GT ? "GT"  :
673
                               i_condition == LE ? "LE"  :
674
                               i_condition == AL ? "AL"  :
675
                                                   "NV " ;
676
 
677
assign  xMODE  =  status_bits_mode == SVC  ? "SVC"  :
678
                  status_bits_mode == IRQ  ? "IRQ"  :
679
                  status_bits_mode == FIRQ ? "FIRQ" :
680
                  status_bits_mode == USR  ? "USR"  :
681
                                             "XXX"  ;
682
 
683
 
684
//synopsys translate_on
685
 
686
endmodule
687
 
688
 

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