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1 16 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  L1 Instruction Cache for Amber 25 Core                      //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9 17 csantifort
//  Synthesizable L1 Instruction Cache.                         //
10
//  Cache is 2,3,4 or 8 way, 256 line and 16 bytes per line.    //
11
//  a total of 16KB. The cache is read only. Writes from        //
12
//  the core to through the data cache.                         //
13 16 csantifort
//                                                              //
14
//  Author(s):                                                  //
15
//      - Conor Santifort, csantifort.amber@gmail.com           //
16
//                                                              //
17
//////////////////////////////////////////////////////////////////
18
//                                                              //
19
// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
20
//                                                              //
21
// This source file may be used and distributed without         //
22
// restriction provided that this copyright statement is not    //
23
// removed from the file and that any derivative work contains  //
24
// the original copyright notice and the associated disclaimer. //
25
//                                                              //
26
// This source file is free software; you can redistribute it   //
27
// and/or modify it under the terms of the GNU Lesser General   //
28
// Public License as published by the Free Software Foundation; //
29
// either version 2.1 of the License, or (at your option) any   //
30
// later version.                                               //
31
//                                                              //
32
// This source is distributed in the hope that it will be       //
33
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
34
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
35
// PURPOSE.  See the GNU Lesser General Public License for more //
36
// details.                                                     //
37
//                                                              //
38
// You should have received a copy of the GNU Lesser General    //
39
// Public License along with this source; if not, download it   //
40
// from http://www.opencores.org/lgpl.shtml                     //
41
//                                                              //
42
//////////////////////////////////////////////////////////////////
43
 
44
`include "a25_config_defines.v"
45
 
46
module a25_icache
47
#(
48
 
49
// ---------------------------------------------------------
50
// Cache Configuration
51
 
52
// Limited to Linux 4k page sizes -> 256 lines
53
parameter CACHE_LINES          = 256,
54
 
55
// This cannot be changed without some major surgeory on
56
// this module                                       
57
parameter CACHE_WORDS_PER_LINE = 4,
58
 
59
// Changing this parameter is the recommended
60
// way to change the overall cache size; 2, 4 and 8 ways are supported.
61
//   2 ways -> 8KB  cache
62
//   4 ways -> 16KB cache
63
//   8 ways -> 32KB cache
64
parameter WAYS              = `A25_ICACHE_WAYS ,
65
 
66
// derived configuration parameters
67
parameter CACHE_ADDR_WIDTH  = log2 ( CACHE_LINES ),                        // = 8
68
parameter WORD_SEL_WIDTH    = log2 ( CACHE_WORDS_PER_LINE ),               // = 2
69
parameter TAG_ADDR_WIDTH    = 32 - CACHE_ADDR_WIDTH - WORD_SEL_WIDTH - 2,  // = 20
70
parameter TAG_WIDTH         = TAG_ADDR_WIDTH + 1,                          // = 21, including Valid flag
71
parameter CACHE_LINE_WIDTH  = CACHE_WORDS_PER_LINE * 32,                   // = 128
72
parameter TAG_ADDR32_LSB    = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2,       // = 12
73
parameter CACHE_ADDR32_MSB  = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2 - 1,   // = 11
74
parameter CACHE_ADDR32_LSB  =                    WORD_SEL_WIDTH + 2    ,   // = 4
75
parameter WORD_SEL_MSB      = WORD_SEL_WIDTH + 2 - 1,                      // = 3
76
parameter WORD_SEL_LSB      =                  2                           // = 2
77
// ---------------------------------------------------------
78
)
79
 
80
 
81
(
82
input                               i_clk,
83
input                               i_core_stall,
84
output                              o_stall,
85
 
86
// Read / Write requests from core
87
input                               i_select,
88
input      [31:0]                   i_address,          // registered address from execute
89
input      [31:0]                   i_address_nxt,      // un-registered version of address from execute stage
90
input                               i_cache_enable,     // from co-processor 15 configuration register
91
input                               i_cache_flush,      // from co-processor 15 register
92
 
93
output      [31:0]                  o_read_data,
94
 
95
// WB Read Request                                                          
96
output                              o_wb_req,          // Read Request
97
input      [31:0]                   i_wb_read_data,
98
input                               i_wb_ready
99
);
100
 
101
`include "a25_localparams.v"
102
`include "a25_functions.v"
103
 
104
// One-hot encoded
105
localparam       C_INIT   = 0,
106
                 C_CORE   = 1,
107
                 C_FILL   = 2,
108
                 C_INVA   = 3,
109
                 C_STATES = 4;
110
 
111
localparam [3:0] CS_INIT            = 4'd0,
112
                 CS_IDLE            = 4'd1,
113
                 CS_FILL0           = 4'd2,
114
                 CS_FILL1           = 4'd3,
115
                 CS_FILL2           = 4'd4,
116
                 CS_FILL3           = 4'd5,
117
                 CS_FILL4           = 4'd6,
118
                 CS_FILL_COMPLETE   = 4'd7,
119
                 CS_TURN_AROUND     = 4'd8,
120
                 CS_WRITE_HIT1      = 4'd9,
121
                 CS_EX_DELETE       = 4'd10;
122
 
123
 
124
reg  [3:0]                  c_state    = CS_IDLE;
125
reg  [C_STATES-1:0]         source_sel = 1'd1 << C_CORE;
126
reg  [CACHE_ADDR_WIDTH:0]   init_count = 'd0;
127
 
128
wire [TAG_WIDTH-1:0]        tag_rdata_way [WAYS-1:0];
129
wire [CACHE_LINE_WIDTH-1:0] data_rdata_way[WAYS-1:0];
130
wire [WAYS-1:0]             data_wenable_way;
131
wire [WAYS-1:0]             data_hit_way;
132
wire [WAYS-1:0]             tag_wenable_way;
133
reg  [WAYS-1:0]             select_way = 'd0;
134
wire [WAYS-1:0]             next_way;
135
reg  [WAYS-1:0]             valid_bits_r = 'd0;
136
 
137
reg  [3:0]                  random_num = 4'hf;
138
 
139
wire [CACHE_ADDR_WIDTH-1:0] tag_address;
140
wire [TAG_WIDTH-1:0]        tag_wdata;
141
wire                        tag_wenable;
142
 
143
wire [CACHE_LINE_WIDTH-1:0] data_wdata;
144
wire [CACHE_ADDR_WIDTH-1:0] data_address;
145
wire [31:0]                 write_data_word;
146
 
147
wire                        idle_hit;
148
wire                        read_miss;
149
wire                        read_miss_fill;
150
wire                        invalid_read;
151
wire                        fill_state;
152
 
153
reg  [31:0]                 miss_address = 'd0;
154
wire [CACHE_LINE_WIDTH-1:0] hit_rdata;
155
 
156
wire                        cache_busy_stall;
157
wire                        read_stall;
158
 
159
wire                        enable;
160
wire [CACHE_ADDR_WIDTH-1:0] address;
161
wire [31:0]                 address_c;
162
reg  [31:0]                 address_r = 'd0;
163
 
164
reg  [CACHE_LINE_WIDTH-1:0] wb_rdata_burst_r = 'd0;
165
wire [CACHE_LINE_WIDTH-1:0] wb_rdata_burst;
166
 
167
reg  [31:0]                 wb_address = 'd0;
168
wire                        rbuf_hit = 'd0;
169
wire                        wb_hit;
170
genvar                      i;
171
 
172
// ======================================
173
// Address to use for cache access
174
// ======================================
175
// If currently stalled then the address for the next
176
// cycle will be the same as it is in the current cycle
177
//
178
assign address_c = i_core_stall ? i_address    : //[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
179
                                i_address_nxt; //[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] ;
180
 
181
assign address   = address_c[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB];
182
 
183
// ======================================
184
// Outputs
185
// ======================================
186
assign o_read_data      = wb_hit                                       ? i_wb_read_data     :
187
                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd0 ? hit_rdata [31:0]   :
188
                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd1 ? hit_rdata [63:32]  :
189
                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd2 ? hit_rdata [95:64]  :
190
                                                                         hit_rdata [127:96] ;
191
 
192
// Don't allow the cache to stall the wb i/f for an exclusive access
193
// The cache needs a couple of cycles to flush a potential copy of the exclusive
194
// address, but the wb can do the access in parallel. So there is no
195
// stall in the state CS_EX_DELETE, even though the cache is out of action. 
196
// This works fine as long as the wb is stalling the core
197
assign o_stall          = read_stall  || cache_busy_stall;
198
 
199
assign o_wb_req         = read_miss && c_state == CS_IDLE;
200
 
201
 
202
// ======================================
203
// Cache State Machine
204
// ======================================
205
 
206
// Little State Machine to Flush Tag RAMS
207
always @ ( posedge i_clk )
208
    if ( i_cache_flush )
209
        begin
210
        c_state     <= CS_INIT;
211
        source_sel  <= 1'd1 << C_INIT;
212
        init_count  <= 'd0;
213
        `ifdef A25_CACHE_DEBUG
214
        `TB_DEBUG_MESSAGE
215
        $display("Cache Flush");
216
        `endif
217
        end
218
    else
219
        case ( c_state )
220
            CS_INIT :
221
                if ( init_count < CACHE_LINES [CACHE_ADDR_WIDTH:0] )
222
                    begin
223
                    init_count  <= init_count + 1'd1;
224
                    source_sel  <= 1'd1 << C_INIT;
225
                    end
226
                else
227
                    begin
228
                    source_sel  <= 1'd1 << C_CORE;
229
                    c_state     <= CS_TURN_AROUND;
230
                    end
231
 
232
             CS_IDLE :
233
                begin
234
                source_sel  <= 1'd1 << C_CORE;
235
 
236
                if ( read_miss )
237
                    c_state <= CS_FILL0;
238
               end
239
 
240
             CS_FILL0 :
241
                begin
242
                // wb read request asserted, wait for ack
243
                if ( i_wb_ready )
244
                    c_state <= CS_FILL1;
245
                end
246
 
247
             CS_FILL1 :
248
                begin
249
                // wb read request asserted, wait for ack
250
                if ( i_wb_ready )
251
                    c_state <= CS_FILL2;
252
                end
253
 
254
 
255
             CS_FILL2 :
256
                // first read of burst of 4
257
                // wb read request asserted, wait for ack
258
                if ( i_wb_ready )
259
                    c_state <= CS_FILL3;
260
 
261
 
262
             CS_FILL3 :
263
                begin
264
                select_way  <= next_way;
265
                random_num  <= {random_num[2], random_num[1], random_num[0],
266
                                 random_num[3]^random_num[2]};
267
 
268
                // third read of burst of 4
269
                // wb read request asserted, wait for ack
270
                if ( i_wb_ready )
271
                    begin
272
                    c_state     <= CS_FILL_COMPLETE;
273
 
274
                    // Pick a way to write the cache update into
275
                    // Either pick one of the invalid caches, or if all are valid, then pick
276
                    // one randomly
277
 
278
                    end
279
                end
280
 
281
 
282
             // Write the read fetch data in this cycle
283
             CS_FILL_COMPLETE :
284
                begin
285
                // Back to normal cache operations, but
286
                // use physical address for first read as
287
                // address moved before the stall was asserted for the read_miss
288
                // However don't use it if its a non-cached address!
289
                source_sel  <= 1'd1 << C_CORE;
290
                c_state     <= CS_TURN_AROUND;
291
                end
292
 
293
 
294
             // Ignore the tag read data in this cycle   
295
             // Wait 1 cycle to pre-read the cache and return to normal operation                 
296
             CS_TURN_AROUND :
297
                begin
298
                c_state     <= CS_IDLE;
299
                end
300
 
301
        endcase
302
 
303
 
304
// ======================================
305
// Capture WB Block Read - burst of 4 words
306
// ======================================
307
assign wb_rdata_burst = {i_wb_read_data, wb_rdata_burst_r[127:32]};
308
always @ ( posedge i_clk )
309
    if ( i_wb_ready )
310
        wb_rdata_burst_r <= wb_rdata_burst;
311
 
312
 
313
// ======================================
314
// Miss Address
315
// ======================================
316
always @ ( posedge i_clk )
317
    if ( c_state == CS_IDLE )
318
        miss_address <= i_address;
319
 
320
 
321
always @ ( posedge i_clk )
322
    address_r <= address_c;
323
 
324
assign invalid_read = address_r != i_address;
325
 
326
 
327
always @(posedge i_clk)
328
    if ( o_wb_req )
329
        wb_address <= i_address;
330
    else if ( i_wb_ready && fill_state )
331
        wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0};
332
 
333
assign fill_state       = c_state == CS_FILL0 || c_state == CS_FILL1 || c_state == CS_FILL2 || c_state == CS_FILL3 ;
334
assign wb_hit           = i_address == wb_address && i_wb_ready && fill_state;
335
 
336
assign tag_address      = read_miss_fill     ? miss_address      [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
337
                          source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0]                      :
338
                                               address                                               ;
339
 
340
 
341
assign data_address     = read_miss_fill     ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
342
                                               address                                         ;
343
 
344
 
345
assign tag_wdata        = read_miss_fill     ? {1'd1, miss_address[31:TAG_ADDR32_LSB]} :
346
                                               {TAG_WIDTH{1'd0}}                       ;
347
 
348
 
349
// Data comes in off the WB bus in wrap4 with the missed data word first
350
assign data_wdata       = miss_address[3:2] == 2'd0 ? { wb_rdata_burst[127:0]                        }:
351
                          miss_address[3:2] == 2'd1 ? { wb_rdata_burst[95:0], wb_rdata_burst[127:96] }:
352
                          miss_address[3:2] == 2'd2 ? { wb_rdata_burst[63:0], wb_rdata_burst[127:64] }:
353
                                                      { wb_rdata_burst[31:0], wb_rdata_burst[127:32] };
354
 
355
 
356
assign read_miss_fill   = c_state == CS_FILL3 && i_wb_ready;
357
 
358
 
359
 
360
assign tag_wenable      = read_miss_fill     ? 1'd1  :
361
                          source_sel[C_INVA] ? 1'd1  :
362
                          source_sel[C_FILL] ? 1'd1  :
363
                          source_sel[C_INIT] ? 1'd1  :
364
                          source_sel[C_CORE] ? 1'd0  :
365
                                               1'd0  ;
366
 
367
 
368
assign enable           = i_select && i_cache_enable;
369
 
370
assign idle_hit         = |data_hit_way;
371
 
372
assign read_miss        = enable && !idle_hit && !invalid_read;
373
 
374
assign read_stall       = enable && !idle_hit && !rbuf_hit && !wb_hit;
375
 
376
assign cache_busy_stall = (c_state == CS_TURN_AROUND  && enable) || c_state == CS_INIT;
377
 
378
 
379
// ======================================
380
// Instantiate RAMS
381
// ======================================
382
 
383
generate
384
    for ( i=0; i<WAYS;i=i+1 ) begin : rams
385
 
386
        // Tag RAMs 
387
        `ifdef XILINX_SPARTAN6_FPGA
388
        xs6_sram_256x21_line_en
389
        `endif
390
 
391
        `ifdef XILINX_VIRTEX6_FPGA
392
        xv6_sram_256x21_line_en
393
        `endif
394
 
395
        `ifndef XILINX_FPGA
396
        generic_sram_line_en
397
        `endif
398
 
399
            #(
400
            .DATA_WIDTH                 ( TAG_WIDTH             ),
401
            .INITIALIZE_TO_ZERO         ( 1                     ),
402
            .ADDRESS_WIDTH              ( CACHE_ADDR_WIDTH      ))
403
        u_tag (
404
            .i_clk                      ( i_clk                 ),
405
            .i_write_data               ( tag_wdata             ),
406
            .i_write_enable             ( tag_wenable_way[i]    ),
407
            .i_address                  ( tag_address           ),
408
 
409
            .o_read_data                ( tag_rdata_way[i]      )
410
            );
411
 
412
        // Data RAMs 
413
        `ifdef XILINX_SPARTAN6_FPGA
414
        xs6_sram_256x128_byte_en
415
        `endif
416
 
417
        `ifdef XILINX_VIRTEX6_FPGA
418
        xv6_sram_256x128_byte_en
419
        `endif
420
 
421
        `ifndef XILINX_FPGA
422
        generic_sram_byte_en
423
        `endif
424
 
425
            #(
426
            .DATA_WIDTH    ( CACHE_LINE_WIDTH) ,
427
            .ADDRESS_WIDTH ( CACHE_ADDR_WIDTH) )
428
        u_data (
429
            .i_clk                      ( i_clk                         ),
430
            .i_write_data               ( data_wdata                    ),
431
            .i_write_enable             ( data_wenable_way[i]           ),
432
            .i_address                  ( data_address                  ),
433
            .i_byte_enable              ( {CACHE_LINE_WIDTH/8{1'd1}}    ),
434
            .o_read_data                ( data_rdata_way[i]             )
435
            );
436
 
437
 
438
        // Per tag-ram write-enable
439
        assign tag_wenable_way[i]  = tag_wenable && ( select_way[i] || source_sel[C_INIT] );
440
 
441
        // Per data-ram write-enable
442
        assign data_wenable_way[i] = ( source_sel[C_FILL] || read_miss_fill ) && select_way[i];
443
 
444
        // Per data-ram idle_hit flag
445
        assign data_hit_way[i]     = tag_rdata_way[i][TAG_WIDTH-1] &&
446
                                     tag_rdata_way[i][TAG_ADDR_WIDTH-1:0] == i_address[31:TAG_ADDR32_LSB] &&
447
                                     c_state == CS_IDLE;
448
    end
449
endgenerate
450
 
451
 
452
// ======================================
453
// Register Valid Bits
454
// ======================================
455
generate
456
if ( WAYS == 2 ) begin : valid_bits_2ways
457
 
458
    always @ ( posedge i_clk )
459
        if ( c_state == CS_IDLE )
460
            valid_bits_r <= {tag_rdata_way[1][TAG_WIDTH-1],
461
                             tag_rdata_way[0][TAG_WIDTH-1]};
462
 
463
end
464
else if ( WAYS == 3 ) begin : valid_bits_3ways
465
 
466
    always @ ( posedge i_clk )
467
        if ( c_state == CS_IDLE )
468
            valid_bits_r <= {tag_rdata_way[2][TAG_WIDTH-1],
469
                             tag_rdata_way[1][TAG_WIDTH-1],
470
                             tag_rdata_way[0][TAG_WIDTH-1]};
471
 
472
end
473
else if ( WAYS == 4 ) begin : valid_bits_4ways
474
 
475
    always @ ( posedge i_clk )
476
        if ( c_state == CS_IDLE )
477
            valid_bits_r <= {tag_rdata_way[3][TAG_WIDTH-1],
478
                             tag_rdata_way[2][TAG_WIDTH-1],
479
                             tag_rdata_way[1][TAG_WIDTH-1],
480
                             tag_rdata_way[0][TAG_WIDTH-1]};
481
 
482
end
483
else begin : valid_bits_8ways
484
 
485
    always @ ( posedge i_clk )
486
        if ( c_state == CS_IDLE )
487
            valid_bits_r <= {tag_rdata_way[7][TAG_WIDTH-1],
488
                             tag_rdata_way[6][TAG_WIDTH-1],
489
                             tag_rdata_way[5][TAG_WIDTH-1],
490
                             tag_rdata_way[4][TAG_WIDTH-1],
491
                             tag_rdata_way[3][TAG_WIDTH-1],
492
                             tag_rdata_way[2][TAG_WIDTH-1],
493
                             tag_rdata_way[1][TAG_WIDTH-1],
494
                             tag_rdata_way[0][TAG_WIDTH-1]};
495
 
496
end
497
endgenerate
498
 
499
 
500
// ======================================
501
// Select read hit data
502
// ======================================
503
generate
504
if ( WAYS == 2 ) begin : read_data_2ways
505
 
506
    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
507
                          data_hit_way[1] ? data_rdata_way[1] :
508
                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
509
 
510
end
511
else if ( WAYS == 3 ) begin : read_data_3ways
512
 
513
    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
514
                          data_hit_way[1] ? data_rdata_way[1] :
515
                          data_hit_way[2] ? data_rdata_way[2] :
516
                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
517
 
518
end
519
else if ( WAYS == 4 ) begin : read_data_4ways
520
 
521
    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
522
                          data_hit_way[1] ? data_rdata_way[1] :
523
                          data_hit_way[2] ? data_rdata_way[2] :
524
                          data_hit_way[3] ? data_rdata_way[3] :
525
                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
526
 
527
end
528
else begin : read_data_8ways
529
 
530
    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
531
                          data_hit_way[1] ? data_rdata_way[1] :
532
                          data_hit_way[2] ? data_rdata_way[2] :
533
                          data_hit_way[3] ? data_rdata_way[3] :
534
                          data_hit_way[4] ? data_rdata_way[4] :
535
                          data_hit_way[5] ? data_rdata_way[5] :
536
                          data_hit_way[6] ? data_rdata_way[6] :
537
                          data_hit_way[7] ? data_rdata_way[7] :
538
                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
539
 
540
end
541
endgenerate
542
 
543
 
544
// ======================================
545
// Function to select the way to use
546
// for fills
547
// ======================================
548
generate
549
if ( WAYS == 2 ) begin : pick_way_2ways
550
 
551
    assign next_way = pick_way ( valid_bits_r, random_num );
552
 
553
    function [WAYS-1:0] pick_way;
554
    input [WAYS-1:0] valid_bits;
555
    input [3:0]      random_num;
556
    begin
557
        if (      valid_bits[0] == 1'd0 )
558
            // way 0 not occupied so use it
559
            pick_way     = 2'b01;
560
        else if ( valid_bits[1] == 1'd0 )
561
            // way 1 not occupied so use it
562
            pick_way     = 2'b10;
563
        else
564
            begin
565
            // All ways occupied so pick one randomly
566
            case (random_num[3:1])
567
                3'd0, 3'd3,
568
                3'd5, 3'd6: pick_way = 2'b10;
569
                default:    pick_way = 2'b01;
570
            endcase
571
            end
572
    end
573
    endfunction
574
 
575
end
576
else if ( WAYS == 3 ) begin : pick_way_3ways
577
 
578
    assign next_way = pick_way ( valid_bits_r, random_num );
579
 
580
    function [WAYS-1:0] pick_way;
581
    input [WAYS-1:0] valid_bits;
582
    input [3:0]      random_num;
583
    begin
584
        if (      valid_bits[0] == 1'd0 )
585
            // way 0 not occupied so use it
586
            pick_way     = 3'b001;
587
        else if ( valid_bits[1] == 1'd0 )
588
            // way 1 not occupied so use it
589
            pick_way     = 3'b010;
590
        else if ( valid_bits[2] == 1'd0 )
591
            // way 2 not occupied so use it
592
            pick_way     = 3'b100;
593
        else
594
            begin
595
            // All ways occupied so pick one randomly
596
            case (random_num[3:1])
597
                3'd0, 3'd1, 3'd2: pick_way = 3'b010;
598
                3'd2, 3'd3, 3'd4: pick_way = 3'b100;
599
                default:          pick_way = 3'b001;
600
            endcase
601
            end
602
    end
603
    endfunction
604
 
605
end
606
else if ( WAYS == 4 ) begin : pick_way_4ways
607
 
608
    assign next_way = pick_way ( valid_bits_r, random_num );
609
 
610
    function [WAYS-1:0] pick_way;
611
    input [WAYS-1:0] valid_bits;
612
    input [3:0]      random_num;
613
    begin
614
        if (      valid_bits[0] == 1'd0 )
615
            // way 0 not occupied so use it
616
            pick_way     = 4'b0001;
617
        else if ( valid_bits[1] == 1'd0 )
618
            // way 1 not occupied so use it
619
            pick_way     = 4'b0010;
620
        else if ( valid_bits[2] == 1'd0 )
621
            // way 2 not occupied so use it
622
            pick_way     = 4'b0100;
623
        else if ( valid_bits[3] == 1'd0 )
624
            // way 3 not occupied so use it
625
            pick_way     = 4'b1000;
626
        else
627
            begin
628
            // All ways occupied so pick one randomly
629
            case (random_num[3:1])
630
                3'd0, 3'd1: pick_way = 4'b0100;
631
                3'd2, 3'd3: pick_way = 4'b1000;
632
                3'd4, 3'd5: pick_way = 4'b0001;
633
                default:    pick_way = 4'b0010;
634
            endcase
635
            end
636
    end
637
    endfunction
638
 
639
end
640
else begin : pick_way_8ways
641
 
642
    assign next_way = pick_way ( valid_bits_r, random_num );
643
 
644
    function [WAYS-1:0] pick_way;
645
    input [WAYS-1:0] valid_bits;
646
    input [3:0]      random_num;
647
    begin
648
        if (      valid_bits[0] == 1'd0 )
649
            // way 0 not occupied so use it
650
            pick_way     = 8'b00000001;
651
        else if ( valid_bits[1] == 1'd0 )
652
            // way 1 not occupied so use it
653
            pick_way     = 8'b00000010;
654
        else if ( valid_bits[2] == 1'd0 )
655
            // way 2 not occupied so use it
656
            pick_way     = 8'b00000100;
657
        else if ( valid_bits[3] == 1'd0 )
658
            // way 3 not occupied so use it
659
            pick_way     = 8'b00001000;
660
        else if ( valid_bits[4] == 1'd0 )
661
            // way 3 not occupied so use it
662
            pick_way     = 8'b00010000;
663
        else if ( valid_bits[5] == 1'd0 )
664
            // way 3 not occupied so use it
665
            pick_way     = 8'b00100000;
666
        else if ( valid_bits[6] == 1'd0 )
667
            // way 3 not occupied so use it
668
            pick_way     = 8'b01000000;
669
        else if ( valid_bits[7] == 1'd0 )
670
            // way 3 not occupied so use it
671
            pick_way     = 8'b10000000;
672
        else
673
            begin
674
            // All ways occupied so pick one randomly
675
            case (random_num[3:1])
676
                3'd0:       pick_way = 8'b00010000;
677
                3'd1:       pick_way = 8'b00100000;
678
                3'd2:       pick_way = 8'b01000000;
679
                3'd3:       pick_way = 8'b10000000;
680
                3'd4:       pick_way = 8'b00000001;
681
                3'd5:       pick_way = 8'b00000010;
682
                3'd6:       pick_way = 8'b00000100;
683
                default:    pick_way = 8'b00001000;
684
            endcase
685
            end
686
    end
687
    endfunction
688
 
689
end
690
endgenerate
691
 
692
 
693
// ========================================================
694
// Debug WB bus - not synthesizable
695
// ========================================================
696
//synopsys translate_off
697
wire    [(6*8)-1:0]     xSOURCE_SEL;
698
wire    [(20*8)-1:0]    xC_STATE;
699
 
700
assign xSOURCE_SEL = source_sel[C_CORE]            ? "C_CORE"           :
701
                     source_sel[C_INIT]            ? "C_INIT"           :
702
                     source_sel[C_FILL]            ? "C_FILL"           :
703
                     source_sel[C_INVA]            ? "C_INVA"           :
704
                                                     "UNKNON"           ;
705
 
706
assign xC_STATE    = c_state == CS_INIT            ? "CS_INIT"          :
707
                     c_state == CS_IDLE            ? "CS_IDLE"          :
708
                     c_state == CS_FILL0           ? "CS_FILL0"         :
709
                     c_state == CS_FILL1           ? "CS_FILL1"         :
710
                     c_state == CS_FILL2           ? "CS_FILL2"         :
711
                     c_state == CS_FILL3           ? "CS_FILL3"         :
712
                     c_state == CS_FILL4           ? "CS_FILL4"         :
713
                     c_state == CS_FILL_COMPLETE   ? "CS_FILL_COMPLETE" :
714
                     c_state == CS_EX_DELETE       ? "CS_EX_DELETE"     :
715
                     c_state == CS_TURN_AROUND     ? "CS_TURN_AROUND"   :
716
                     c_state == CS_WRITE_HIT1      ? "CS_WRITE_HIT1"    :
717
                                                     "UNKNOWN"          ;
718
 
719
 
720
generate
721
if ( WAYS == 2 ) begin : check_hit_2ways
722
 
723
    always @( posedge i_clk )
724
        if ( (data_hit_way[0] + data_hit_way[1] ) > 4'd1 )
725
            begin
726
            `TB_ERROR_MESSAGE
727
            $display("Hit in more than one cache ways!");
728
            end
729
 
730
end
731
else if ( WAYS == 3 ) begin : check_hit_3ways
732
 
733
    always @( posedge i_clk )
734
        if ( (data_hit_way[0] + data_hit_way[1] + data_hit_way[2] ) > 4'd1 )
735
            begin
736
            `TB_ERROR_MESSAGE
737
            $display("Hit in more than one cache ways!");
738
            end
739
 
740
end
741
else if ( WAYS == 4 ) begin : check_hit_4ways
742
 
743
    always @( posedge i_clk )
744
        if ( (data_hit_way[0] + data_hit_way[1] +
745
              data_hit_way[2] + data_hit_way[3] ) > 4'd1 )
746
            begin
747
            `TB_ERROR_MESSAGE
748
            $display("Hit in more than one cache ways!");
749
            end
750
 
751
end
752
else if ( WAYS == 8 )  begin : check_hit_8ways
753
 
754
    always @( posedge i_clk )
755
        if ( (data_hit_way[0] + data_hit_way[1] +
756
              data_hit_way[2] + data_hit_way[3] +
757
              data_hit_way[4] + data_hit_way[5] +
758
              data_hit_way[6] + data_hit_way[7] ) > 4'd1 )
759
            begin
760
            `TB_ERROR_MESSAGE
761
            $display("Hit in more than one cache ways!");
762
            end
763
 
764
end
765
else begin : check_hit_nways
766
 
767
    initial
768
        begin
769
        `TB_ERROR_MESSAGE
770
        $display("Unsupported number of ways %0d", WAYS);
771
        $display("Set A25_ICACHE_WAYS in a25_config_defines.v to either 2,3,4 or 8");
772
        end
773
 
774
end
775
endgenerate
776
 
777
//synopsys translate_on
778
 
779
endmodule
780
 

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