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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_register_bank.v] - Blame information for rev 35

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1 16 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Register Bank for Amber 25 Core                             //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Contains 37 32-bit registers, 16 of which are visible       //
10
//  ina any one operating mode. Registers use real flipflops,   //
11
//  rather than SRAM. This makes sense for an FPGA              //
12
//  implementation, where flipflops are plentiful.              //
13
//                                                              //
14
//  Author(s):                                                  //
15
//      - Conor Santifort, csantifort.amber@gmail.com           //
16
//                                                              //
17
//////////////////////////////////////////////////////////////////
18
//                                                              //
19
// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
20
//                                                              //
21
// This source file may be used and distributed without         //
22
// restriction provided that this copyright statement is not    //
23
// removed from the file and that any derivative work contains  //
24
// the original copyright notice and the associated disclaimer. //
25
//                                                              //
26
// This source file is free software; you can redistribute it   //
27
// and/or modify it under the terms of the GNU Lesser General   //
28
// Public License as published by the Free Software Foundation; //
29
// either version 2.1 of the License, or (at your option) any   //
30
// later version.                                               //
31
//                                                              //
32
// This source is distributed in the hope that it will be       //
33
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
34
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
35
// PURPOSE.  See the GNU Lesser General Public License for more //
36
// details.                                                     //
37
//                                                              //
38
// You should have received a copy of the GNU Lesser General    //
39
// Public License along with this source; if not, download it   //
40
// from http://www.opencores.org/lgpl.shtml                     //
41
//                                                              //
42
//////////////////////////////////////////////////////////////////
43
 
44
module a25_register_bank (
45
 
46
input                       i_clk,
47 35 csantifort
input                       i_core_stall,
48 16 csantifort
input                       i_mem_stall,
49
 
50
input       [1:0]           i_mode_idec,            // user, supervisor, irq_idec, firq_idec etc.
51
                                                    // Used for register writes
52
input       [1:0]           i_mode_exec,            // 1 periods delayed from i_mode_idec
53
                                                    // Used for register reads
54
input       [3:0]           i_mode_rds_exec,        // Use one-hot version specifically for rds, 
55
                                                    // includes i_user_mode_regs_store
56
input                       i_firq_not_user_mode,
57
input       [3:0]           i_rm_sel,
58
input       [3:0]           i_rs_sel,
59
input       [3:0]           i_rn_sel,
60
 
61
input                       i_pc_wen,
62
input       [14:0]          i_reg_bank_wen,
63
 
64
input       [23:0]          i_pc,                   // program counter [25:2]
65
input       [31:0]          i_reg,
66
 
67
input       [31:0]          i_wb_read_data,
68
input                       i_wb_read_data_valid,
69
input       [3:0]           i_wb_read_data_rd,
70 35 csantifort
input       [1:0]           i_wb_mode,
71 16 csantifort
 
72
input       [3:0]           i_status_bits_flags,
73
input                       i_status_bits_irq_mask,
74
input                       i_status_bits_firq_mask,
75
 
76
output      [31:0]          o_rm,
77
output reg  [31:0]          o_rs,
78
output reg  [31:0]          o_rd,
79
output      [31:0]          o_rn,
80
output      [31:0]          o_pc
81
 
82
);
83
 
84
`include "a25_localparams.v"
85
`include "a25_functions.v"
86
 
87
 
88
// User Mode Registers
89
reg  [31:0] r0  = 32'hdead_beef;
90
reg  [31:0] r1  = 32'hdead_beef;
91
reg  [31:0] r2  = 32'hdead_beef;
92
reg  [31:0] r3  = 32'hdead_beef;
93
reg  [31:0] r4  = 32'hdead_beef;
94
reg  [31:0] r5  = 32'hdead_beef;
95
reg  [31:0] r6  = 32'hdead_beef;
96
reg  [31:0] r7  = 32'hdead_beef;
97
reg  [31:0] r8  = 32'hdead_beef;
98
reg  [31:0] r9  = 32'hdead_beef;
99
reg  [31:0] r10 = 32'hdead_beef;
100
reg  [31:0] r11 = 32'hdead_beef;
101
reg  [31:0] r12 = 32'hdead_beef;
102
reg  [31:0] r13 = 32'hdead_beef;
103
reg  [31:0] r14 = 32'hdead_beef;
104
reg  [23:0] r15 = 24'hc0_ffee;
105
 
106
wire  [31:0] r0_out;
107
wire  [31:0] r1_out;
108
wire  [31:0] r2_out;
109
wire  [31:0] r3_out;
110
wire  [31:0] r4_out;
111
wire  [31:0] r5_out;
112
wire  [31:0] r6_out;
113
wire  [31:0] r7_out;
114
wire  [31:0] r8_out;
115
wire  [31:0] r9_out;
116
wire  [31:0] r10_out;
117
wire  [31:0] r11_out;
118
wire  [31:0] r12_out;
119
wire  [31:0] r13_out;
120
wire  [31:0] r14_out;
121
wire  [31:0] r15_out_rm;
122
wire  [31:0] r15_out_rm_nxt;
123
wire  [31:0] r15_out_rn;
124
 
125
wire  [31:0] r8_rds;
126
wire  [31:0] r9_rds;
127
wire  [31:0] r10_rds;
128
wire  [31:0] r11_rds;
129
wire  [31:0] r12_rds;
130
wire  [31:0] r13_rds;
131
wire  [31:0] r14_rds;
132
 
133
// Supervisor Mode Registers
134
reg  [31:0] r13_svc = 32'hdead_beef;
135
reg  [31:0] r14_svc = 32'hdead_beef;
136
 
137
// Interrupt Mode Registers
138
reg  [31:0] r13_irq = 32'hdead_beef;
139
reg  [31:0] r14_irq = 32'hdead_beef;
140
 
141
// Fast Interrupt Mode Registers
142
reg  [31:0] r8_firq  = 32'hdead_beef;
143
reg  [31:0] r9_firq  = 32'hdead_beef;
144
reg  [31:0] r10_firq = 32'hdead_beef;
145
reg  [31:0] r11_firq = 32'hdead_beef;
146
reg  [31:0] r12_firq = 32'hdead_beef;
147
reg  [31:0] r13_firq = 32'hdead_beef;
148
reg  [31:0] r14_firq = 32'hdead_beef;
149
 
150
wire        usr_exec;
151
wire        svc_exec;
152
wire        irq_exec;
153
wire        firq_exec;
154
 
155
wire        usr_idec;
156
wire        svc_idec;
157
wire        irq_idec;
158
wire        firq_idec;
159
wire [14:0] read_data_wen;
160
wire [14:0] reg_bank_wen_c;
161
wire        pc_wen_c;
162
wire        pc_dmem_wen;
163
 
164
 
165
    // Write Enables from execute stage
166
assign usr_idec  = i_mode_idec == USR;
167
assign svc_idec  = i_mode_idec == SVC;
168
assign irq_idec  = i_mode_idec == IRQ;
169
 
170
// pre-encoded in decode stage to speed up long path
171
assign firq_idec = i_firq_not_user_mode;
172
 
173
    // Read Enables from stage 1 (fetch)
174
assign usr_exec  = i_mode_exec == USR;
175
assign svc_exec  = i_mode_exec == SVC;
176
assign irq_exec  = i_mode_exec == IRQ;
177
assign firq_exec = i_mode_exec == FIRQ;
178
 
179
assign read_data_wen = {15{i_wb_read_data_valid & ~i_mem_stall}} & decode (i_wb_read_data_rd);
180
 
181 35 csantifort
assign reg_bank_wen_c = {15{~i_core_stall}} & i_reg_bank_wen;
182
assign pc_wen_c       = ~i_core_stall & i_pc_wen;
183 16 csantifort
assign pc_dmem_wen    = i_wb_read_data_valid & ~i_mem_stall & i_wb_read_data_rd == 4'd15;
184
 
185
 
186
// ========================================================
187
// Register Update
188
// ========================================================
189
always @ ( posedge i_clk )
190
    begin
191 35 csantifort
    // these registers are used in all modes
192
    r0       <= reg_bank_wen_c[0 ]               ? i_reg : read_data_wen[0 ]                      ? i_wb_read_data       : r0;
193
    r1       <= reg_bank_wen_c[1 ]               ? i_reg : read_data_wen[1 ]                      ? i_wb_read_data       : r1;
194
    r2       <= reg_bank_wen_c[2 ]               ? i_reg : read_data_wen[2 ]                      ? i_wb_read_data       : r2;
195
    r3       <= reg_bank_wen_c[3 ]               ? i_reg : read_data_wen[3 ]                      ? i_wb_read_data       : r3;
196
    r4       <= reg_bank_wen_c[4 ]               ? i_reg : read_data_wen[4 ]                      ? i_wb_read_data       : r4;
197
    r5       <= reg_bank_wen_c[5 ]               ? i_reg : read_data_wen[5 ]                      ? i_wb_read_data       : r5;
198
    r6       <= reg_bank_wen_c[6 ]               ? i_reg : read_data_wen[6 ]                      ? i_wb_read_data       : r6;
199
    r7       <= reg_bank_wen_c[7 ]               ? i_reg : read_data_wen[7 ]                      ? i_wb_read_data       : r7;
200 16 csantifort
 
201 35 csantifort
    // these registers are used in all modes, except fast irq
202
    r8       <= reg_bank_wen_c[8 ] && !firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode != FIRQ ? i_wb_read_data       : r8;
203
    r9       <= reg_bank_wen_c[9 ] && !firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode != FIRQ ? i_wb_read_data       : r9;
204
    r10      <= reg_bank_wen_c[10] && !firq_idec ? i_reg : read_data_wen[10] && i_wb_mode != FIRQ ? i_wb_read_data       : r10;
205
    r11      <= reg_bank_wen_c[11] && !firq_idec ? i_reg : read_data_wen[11] && i_wb_mode != FIRQ ? i_wb_read_data       : r11;
206
    r12      <= reg_bank_wen_c[12] && !firq_idec ? i_reg : read_data_wen[12] && i_wb_mode != FIRQ ? i_wb_read_data       : r12;
207 16 csantifort
 
208 35 csantifort
    // these registers are used in fast irq mode
209
    r8_firq  <= reg_bank_wen_c[8 ] &&  firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode == FIRQ ? i_wb_read_data       : r8_firq;
210
    r9_firq  <= reg_bank_wen_c[9 ] &&  firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode == FIRQ ? i_wb_read_data       : r9_firq;
211
    r10_firq <= reg_bank_wen_c[10] &&  firq_idec ? i_reg : read_data_wen[10] && i_wb_mode == FIRQ ? i_wb_read_data       : r10_firq;
212
    r11_firq <= reg_bank_wen_c[11] &&  firq_idec ? i_reg : read_data_wen[11] && i_wb_mode == FIRQ ? i_wb_read_data       : r11_firq;
213
    r12_firq <= reg_bank_wen_c[12] &&  firq_idec ? i_reg : read_data_wen[12] && i_wb_mode == FIRQ ? i_wb_read_data       : r12_firq;
214 16 csantifort
 
215 35 csantifort
    // these registers are used in user mode
216
    r13      <= reg_bank_wen_c[13] &&  usr_idec  ? i_reg : read_data_wen[13] && i_wb_mode == USR ? i_wb_read_data        : r13;
217
    r14      <= reg_bank_wen_c[14] &&  usr_idec  ? i_reg : read_data_wen[14] && i_wb_mode == USR ? i_wb_read_data        : r14;
218 16 csantifort
 
219 35 csantifort
    // these registers are used in supervisor mode
220
    r13_svc  <= reg_bank_wen_c[13] &&  svc_idec  ? i_reg : read_data_wen[13] && i_wb_mode == SVC  ? i_wb_read_data       : r13_svc;
221
    r14_svc  <= reg_bank_wen_c[14] &&  svc_idec  ? i_reg : read_data_wen[14] && i_wb_mode == SVC  ? i_wb_read_data       : r14_svc;
222 16 csantifort
 
223 35 csantifort
    // these registers are used in irq mode
224
    r13_irq  <= reg_bank_wen_c[13] &&  irq_idec  ? i_reg : read_data_wen[13] && i_wb_mode == IRQ  ? i_wb_read_data       : r13_irq;
225
    r14_irq  <= (reg_bank_wen_c[14] && irq_idec) ? i_reg : read_data_wen[14] && i_wb_mode == IRQ  ? i_wb_read_data       : r14_irq;
226 16 csantifort
 
227 35 csantifort
    // these registers are used in fast irq mode
228
    r13_firq <= reg_bank_wen_c[13] &&  firq_idec ? i_reg : read_data_wen[13] && i_wb_mode == FIRQ ? i_wb_read_data       : r13_firq;
229
    r14_firq <= reg_bank_wen_c[14] &&  firq_idec ? i_reg : read_data_wen[14] && i_wb_mode == FIRQ ? i_wb_read_data       : r14_firq;
230 16 csantifort
 
231 35 csantifort
    // these registers are used in all modes
232
    r15      <= pc_wen_c                         ?  i_pc : pc_dmem_wen                            ? i_wb_read_data[25:2] : r15;
233 16 csantifort
    end
234
 
235
 
236
// ========================================================
237
// Register Read based on Mode
238
// ========================================================
239
assign r0_out = r0;
240
assign r1_out = r1;
241
assign r2_out = r2;
242
assign r3_out = r3;
243
assign r4_out = r4;
244
assign r5_out = r5;
245
assign r6_out = r6;
246
assign r7_out = r7;
247
 
248
assign r8_out  = firq_exec ? r8_firq  : r8;
249
assign r9_out  = firq_exec ? r9_firq  : r9;
250
assign r10_out = firq_exec ? r10_firq : r10;
251
assign r11_out = firq_exec ? r11_firq : r11;
252
assign r12_out = firq_exec ? r12_firq : r12;
253
 
254
assign r13_out = usr_exec ? r13      :
255
                 svc_exec ? r13_svc  :
256
                 irq_exec ? r13_irq  :
257
                          r13_firq ;
258
 
259
assign r14_out = usr_exec ? r14      :
260
                 svc_exec ? r14_svc  :
261
                 irq_exec ? r14_irq  :
262
                          r14_firq ;
263
 
264
 
265
assign r15_out_rm     = { i_status_bits_flags,
266
                          i_status_bits_irq_mask,
267
                          i_status_bits_firq_mask,
268
                          r15,
269
                          i_mode_exec};
270
 
271
assign r15_out_rm_nxt = { i_status_bits_flags,
272
                          i_status_bits_irq_mask,
273
                          i_status_bits_firq_mask,
274
                          i_pc,
275
                          i_mode_exec};
276
 
277
assign r15_out_rn     = {6'd0, r15, 2'd0};
278
 
279
 
280
// rds outputs
281
assign r8_rds  = i_mode_rds_exec[OH_FIRQ] ? r8_firq  : r8;
282
assign r9_rds  = i_mode_rds_exec[OH_FIRQ] ? r9_firq  : r9;
283
assign r10_rds = i_mode_rds_exec[OH_FIRQ] ? r10_firq : r10;
284
assign r11_rds = i_mode_rds_exec[OH_FIRQ] ? r11_firq : r11;
285
assign r12_rds = i_mode_rds_exec[OH_FIRQ] ? r12_firq : r12;
286
 
287
assign r13_rds = i_mode_rds_exec[OH_USR]  ? r13      :
288
                 i_mode_rds_exec[OH_SVC]  ? r13_svc  :
289
                 i_mode_rds_exec[OH_IRQ]  ? r13_irq  :
290
                                            r13_firq ;
291
 
292
assign r14_rds = i_mode_rds_exec[OH_USR]  ? r14      :
293
                 i_mode_rds_exec[OH_SVC]  ? r14_svc  :
294
                 i_mode_rds_exec[OH_IRQ]  ? r14_irq  :
295
                                            r14_firq ;
296
 
297
 
298
// ========================================================
299
// Program Counter out
300
// ========================================================
301
assign o_pc = r15_out_rn;
302
 
303
// ========================================================
304
// Rm Selector
305
// ========================================================
306
assign o_rm = i_rm_sel == 4'd0  ? r0_out  :
307
              i_rm_sel == 4'd1  ? r1_out  :
308
              i_rm_sel == 4'd2  ? r2_out  :
309
              i_rm_sel == 4'd3  ? r3_out  :
310
              i_rm_sel == 4'd4  ? r4_out  :
311
              i_rm_sel == 4'd5  ? r5_out  :
312
              i_rm_sel == 4'd6  ? r6_out  :
313
              i_rm_sel == 4'd7  ? r7_out  :
314
              i_rm_sel == 4'd8  ? r8_out  :
315
              i_rm_sel == 4'd9  ? r9_out  :
316
              i_rm_sel == 4'd10 ? r10_out :
317
              i_rm_sel == 4'd11 ? r11_out :
318
              i_rm_sel == 4'd12 ? r12_out :
319
              i_rm_sel == 4'd13 ? r13_out :
320
              i_rm_sel == 4'd14 ? r14_out :
321
                                  r15_out_rm ;
322
 
323
 
324
// ========================================================
325
// Rds Selector
326
// ========================================================
327
always @*
328
    case ( i_rs_sel )
329
       4'd0  :  o_rs = r0_out  ;
330
       4'd1  :  o_rs = r1_out  ;
331
       4'd2  :  o_rs = r2_out  ;
332
       4'd3  :  o_rs = r3_out  ;
333
       4'd4  :  o_rs = r4_out  ;
334
       4'd5  :  o_rs = r5_out  ;
335
       4'd6  :  o_rs = r6_out  ;
336
       4'd7  :  o_rs = r7_out  ;
337
       4'd8  :  o_rs = r8_rds  ;
338
       4'd9  :  o_rs = r9_rds  ;
339
       4'd10 :  o_rs = r10_rds ;
340
       4'd11 :  o_rs = r11_rds ;
341
       4'd12 :  o_rs = r12_rds ;
342
       4'd13 :  o_rs = r13_rds ;
343
       4'd14 :  o_rs = r14_rds ;
344
       4'd15 :  o_rs = r15_out_rn ;
345
       default: o_rs = r15_out_rn ;
346
    endcase
347
 
348
 
349
// ========================================================
350
// Rd Selector
351
// ========================================================
352
always @*
353
    case ( i_rs_sel )
354
       4'd0  :  o_rd = r0_out  ;
355
       4'd1  :  o_rd = r1_out  ;
356
       4'd2  :  o_rd = r2_out  ;
357
       4'd3  :  o_rd = r3_out  ;
358
       4'd4  :  o_rd = r4_out  ;
359
       4'd5  :  o_rd = r5_out  ;
360
       4'd6  :  o_rd = r6_out  ;
361
       4'd7  :  o_rd = r7_out  ;
362
       4'd8  :  o_rd = r8_rds  ;
363
       4'd9  :  o_rd = r9_rds  ;
364
       4'd10 :  o_rd = r10_rds ;
365
       4'd11 :  o_rd = r11_rds ;
366
       4'd12 :  o_rd = r12_rds ;
367
       4'd13 :  o_rd = r13_rds ;
368
       4'd14 :  o_rd = r14_rds ;
369
       4'd15 :  o_rd = r15_out_rm_nxt ;
370
       default: o_rd = r15_out_rm_nxt ;
371
    endcase
372
 
373
 
374
// ========================================================
375
// Rn Selector
376
// ========================================================
377
assign o_rn = i_rn_sel == 4'd0  ? r0_out  :
378
              i_rn_sel == 4'd1  ? r1_out  :
379
              i_rn_sel == 4'd2  ? r2_out  :
380
              i_rn_sel == 4'd3  ? r3_out  :
381
              i_rn_sel == 4'd4  ? r4_out  :
382
              i_rn_sel == 4'd5  ? r5_out  :
383
              i_rn_sel == 4'd6  ? r6_out  :
384
              i_rn_sel == 4'd7  ? r7_out  :
385
              i_rn_sel == 4'd8  ? r8_out  :
386
              i_rn_sel == 4'd9  ? r9_out  :
387
              i_rn_sel == 4'd10 ? r10_out :
388
              i_rn_sel == 4'd11 ? r11_out :
389
              i_rn_sel == 4'd12 ? r12_out :
390
              i_rn_sel == 4'd13 ? r13_out :
391
              i_rn_sel == 4'd14 ? r14_out :
392
                                  r15_out_rn ;
393
 
394
 
395
endmodule
396
 
397
 

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